From patchwork Fri Mar 27 04:18:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 11461611 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA703161F for ; Fri, 27 Mar 2020 04:18:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A03AC20705 for ; Fri, 27 Mar 2020 04:18:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="0g1fmZue" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725904AbgC0ESP (ORCPT ); Fri, 27 Mar 2020 00:18:15 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:55486 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726106AbgC0ESP (ORCPT ); Fri, 27 Mar 2020 00:18:15 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 901B280237; Fri, 27 Mar 2020 17:18:12 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1585282692; bh=rWzErC/ba66zHapfPKXI81c1IflcLBV+nnSryfHwXwA=; h=From:To:Cc:Subject:Date; b=0g1fmZueMk51yLex3C8s+GfM70ah49mp6CsZ615iF/Ze/vGwxjtc6y+RAE6rmvpA9 K89f1DjkMXk6dd/v0Z4V+OxeqlM8LByiktTt+9IPeFCXwh7oo8iG+Ehot9/+6N6xyK S0Bzl+bj//6he8p9muhxkfpnmQjnT5g72wweAp/fDZljEjhX7fcYA4Ln3uwyUZoRGa N/ZCvJOPJvJnK7c82334d9pVRZfqwH77ocdB+4K/FojrpYFGlIfjJjP2Gb85vDZFwD grUCyRn3KVwlUtF48WryAy+JZbueUKsA5fpNfQNVvjBk22b/rjBCHhhGA9sbxaZiYh OwYwDnAAwHVYw== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 27 Mar 2020 17:18:12 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.20]) by smtp (Postfix) with ESMTP id 63BF913EEB7; Fri, 27 Mar 2020 17:18:11 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 96C7128006C; Fri, 27 Mar 2020 17:18:11 +1300 (NZDT) From: Chris Packham To: a.zummo@towertech.it, alexandre.belloni@bootlin.com, wim@linux-watchdog.org, linux@roeck-us.net Cc: linux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2] rtc: ds1307: add support for watchdog timer on ds1388 Date: Fri, 27 Mar 2020 17:18:09 +1300 Message-Id: <20200327041809.2029-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 x-atlnz-ls: pat Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org The DS1388 variant has watchdog timer capabilities. When using a DS1388 and having enabled CONFIG_WATCHDOG_CORE register a watchdog device for the DS1388. Signed-off-by: Chris Packham --- This is going to the linux-watchdog list as well this time so it's probably the first time the watchdog maintainers have seen it. Changes in v2: - Address review comments from Alexandre, the only functional change is setting the hundredths of seconds to 0 instead of 99. drivers/rtc/rtc-ds1307.c | 97 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c index 31a38d468378..1452982c3a6a 100644 --- a/drivers/rtc/rtc-ds1307.c +++ b/drivers/rtc/rtc-ds1307.c @@ -22,6 +22,7 @@ #include #include #include +#include /* * We can't determine type by probing, but if we expect pre-Linux code @@ -144,8 +145,15 @@ enum ds_type { # define M41TXX_BIT_CALIB_SIGN BIT(5) # define M41TXX_M_CALIBRATION GENMASK(4, 0) +#define DS1388_REG_WDOG_HUN_SECS 0x08 +#define DS1388_REG_WDOG_SECS 0x09 #define DS1388_REG_FLAG 0x0b +# define DS1388_BIT_WF BIT(6) # define DS1388_BIT_OSF BIT(7) +#define DS1388_REG_CONTROL 0x0c +# define DS1388_BIT_RST BIT(0) +# define DS1388_BIT_WDE BIT(1) + /* negative offset step is -2.034ppm */ #define M41TXX_NEG_OFFSET_STEP_PPB 2034 /* positive offset step is +4.068ppm */ @@ -166,6 +174,9 @@ struct ds1307 { #ifdef CONFIG_COMMON_CLK struct clk_hw clks[2]; #endif +#ifdef CONFIG_WATCHDOG_CORE + struct watchdog_device wdt; +#endif }; struct chip_desc { @@ -854,6 +865,58 @@ static int m41txx_rtc_set_offset(struct device *dev, long offset) ctrl_reg); } +#ifdef CONFIG_WATCHDOG_CORE +static int ds1388_wdt_start(struct watchdog_device *wdt_dev) +{ + struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); + u8 regs[2]; + int ret; + + ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG, + DS1388_BIT_WF, 0); + if (ret) + return ret; + + ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, + DS1388_BIT_WDE | DS1388_BIT_RST, 0); + if (ret) + return ret; + + /* + * watchdog timeouts are measured in seconds. So ignore hundreths of + * seconds field. + */ + regs[0] = 0; + regs[1] = bin2bcd(wdt_dev->timeout); + + ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, + sizeof(regs)); + if (ret) + return ret; + + return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, + DS1388_BIT_WDE | DS1388_BIT_RST, + DS1388_BIT_WDE | DS1388_BIT_RST); +} + +static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) +{ + struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); + + return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL, + DS1388_BIT_WDE | DS1388_BIT_RST, 0); +} + +static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) +{ + struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev); + u8 regs[2]; + + return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs, + sizeof(regs)); +} +#endif + static const struct rtc_class_ops rx8130_rtc_ops = { .read_time = ds1307_get_time, .set_time = ds1307_set_time, @@ -1576,6 +1639,39 @@ static void ds1307_clks_register(struct ds1307 *ds1307) #endif /* CONFIG_COMMON_CLK */ +#ifdef CONFIG_WATCHDOG_CORE +static const struct watchdog_info ds1388_wdt_info = { + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, + .identity = "DS1388 watchdog", +}; + +static const struct watchdog_ops ds1388_wdt_ops = { + .owner = THIS_MODULE, + .start = ds1388_wdt_start, + .stop = ds1388_wdt_stop, + .ping = ds1388_wdt_ping, +}; + +static void ds1307_wdt_register(struct ds1307 *ds1307) +{ + if (ds1307->type != ds_1388) + return; + + ds1307->wdt.info = &ds1388_wdt_info; + ds1307->wdt.ops = &ds1388_wdt_ops; + ds1307->wdt.max_timeout = 99; + ds1307->wdt.min_timeout = 1; + + watchdog_init_timeout(&ds1307->wdt, 99, ds1307->dev); + watchdog_set_drvdata(&ds1307->wdt, ds1307); + watchdog_register_device(&ds1307->wdt); +} +#else +static void ds1307_wdt_register(struct ds1307 *ds1307) +{ +} +#endif /* CONFIG_WATCHDOG_CORE */ + static const struct regmap_config regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -1865,6 +1961,7 @@ static int ds1307_probe(struct i2c_client *client, ds1307_hwmon_register(ds1307); ds1307_clks_register(ds1307); + ds1307_wdt_register(ds1307); return 0;