From patchwork Mon Mar 30 07:14:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11464869 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BFDA3912 for ; Mon, 30 Mar 2020 07:15:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9993920781 for ; Mon, 30 Mar 2020 07:15:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GWy51g62" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729446AbgC3HP6 (ORCPT ); Mon, 30 Mar 2020 03:15:58 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:35287 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729378AbgC3HP5 (ORCPT ); Mon, 30 Mar 2020 03:15:57 -0400 Received: by mail-pg1-f196.google.com with SMTP id k5so6041510pga.2; Mon, 30 Mar 2020 00:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xKFpCudKYBZvQ8EtOLejOUBPW7N9bLRf634sMMnnRrc=; b=GWy51g62XQ0ENEstd2CAEa3+Lm2sMACdR2HSAjoFunAeSW1e1jlU9YtRvAmH4VDeVH lT0iLBSa711U7LgegLu8aen0+NwhcJMUx0e0i/5Ovw6nqLgR9ytuZSHedrFv3VcPbNEi zOnNKDjraXuaASIP7pQESNyRbAK324w+YnAdPLCdT4WqjagLOurMb+wsrdmR0XUeSZLX dv3mU9s3fV30OlY+8nT/DK7E9tnTWMRrQ4u81dMgKPjjuS6z/Xul0NcFNIdKNc0+vhmy 5Tgrd2R0u2u9e1cN3kTfb5Wgt+v50JTsriF4jvsxcHcjwWYvBHqgbxEa7c1L+6Qt8K2C Px8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xKFpCudKYBZvQ8EtOLejOUBPW7N9bLRf634sMMnnRrc=; b=jb4GrylzoGu1q2HdCrEZBsGa4Mvzmz8KhzBJzz+JAQJ3j8Ww0nebMyzmWh0Z+fmW44 kxKDT4mZvvr/ZtEUE0qGBjAv9SYMzT+ktEjGNlPTMuwz/zroUO0/ZhaoYNUTQqAf7m0M pmGIwtspgrvwfK320RmVIdEby9CmBpL3VLRU4qnO1Mc/uWXdxcHZPNvcemiFPiLArGda CNPvusSZRQ2+uK/rU2kTtdcKsTQWOs4joWjI4+2jfO+upD0AXAYt+kItutQtVUmfsVld DTAtvnX3+z3PEFhEwdIau6diIJNk+QFBNpxNQqmUSkrplYzYc4d2+QHWu9OnMmcPRYtj 5xjw== X-Gm-Message-State: ANhLgQ1NTSc72YNsnzen2gMYAuGe6LI1tNpxnl/hF7nGK3xZFYwlf3kw SpYCnVroj4N7GHpHBW5xtfY= X-Google-Smtp-Source: ADFU+vvCnOik/ZUB/hjFhj7+4XkZB4/brE92p7sVx/jl5qOfFLzBRfapvqLjqu1OUHKtzsybZLeY8A== X-Received: by 2002:a63:a74e:: with SMTP id w14mr11341668pgo.231.1585552556128; Mon, 30 Mar 2020 00:15:56 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id l1sm9490484pje.9.2020.03.30.00.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 00:15:55 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH 1/4] clk: sprd: check its parent status before reading gate clock Date: Mon, 30 Mar 2020 15:14:48 +0800 Message-Id: <20200330071451.7899-2-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200330071451.7899-1-zhang.lyra@gmail.com> References: <20200330071451.7899-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang Some clocks only can be accessed if their parent is enabled. mipi_csi_xx clocks on SC9863A are examples. We have to ensure the parent clock is enabled when reading those clocks. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/gate.c | 8 ++++++++ drivers/clk/sprd/gate.h | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c index 574cfc116bbc..8d14073b9cb8 100644 --- a/drivers/clk/sprd/gate.c +++ b/drivers/clk/sprd/gate.c @@ -5,6 +5,7 @@ // Copyright (C) 2017 Spreadtrum, Inc. // Author: Chunyan Zhang +#include #include #include @@ -94,8 +95,15 @@ static int sprd_gate_is_enabled(struct clk_hw *hw) { struct sprd_gate *sg = hw_to_sprd_gate(hw); struct sprd_clk_common *common = &sg->common; + struct clk_hw *parent; unsigned int reg; + if (sg->flags & SPRD_GATE_NON_AON) { + parent = clk_hw_get_parent(hw); + if (!parent || !clk_hw_is_enabled(parent)) + return 0; + } + regmap_read(common->regmap, common->reg, ®); if (sg->flags & CLK_GATE_SET_TO_DISABLE) diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h index b55817869367..aa4d72381788 100644 --- a/drivers/clk/sprd/gate.h +++ b/drivers/clk/sprd/gate.h @@ -19,6 +19,15 @@ struct sprd_gate { struct sprd_clk_common common; }; +/* + * sprd_gate->flags is used for: + * CLK_GATE_SET_TO_DISABLE BIT(0) + * CLK_GATE_HIWORD_MASK BIT(1) + * CLK_GATE_BIG_ENDIAN BIT(2) + * so we define new flags from BIT(3) + */ +#define SPRD_GATE_NON_AON BIT(3) /* not alway on, need to check before read */ + #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ _sc_offset, _enable_mask, _flags, \ _gate_flags, _udelay, _ops, _fn) \ From patchwork Mon Mar 30 07:14:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11464871 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09DED15AB for ; Mon, 30 Mar 2020 07:16:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D8CE02073B for ; Mon, 30 Mar 2020 07:16:04 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 30 Mar 2020 00:15:59 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH 2/4] dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A Date: Mon, 30 Mar 2020 15:14:49 +0800 Message-Id: <20200330071451.7899-3-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200330071451.7899-1-zhang.lyra@gmail.com> References: <20200330071451.7899-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml index bb3a78d8105e..87e8349a539a 100644 --- a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml @@ -28,6 +28,7 @@ properties: - sprd,sc9863a-rpll - sprd,sc9863a-dpll - sprd,sc9863a-mm-gate + - sprd,sc9863a-mm-clk - sprd,sc9863a-apapb-gate clocks: From patchwork Mon Mar 30 07:14:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11464873 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33454912 for ; Mon, 30 Mar 2020 07:16:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 114A420787 for ; Mon, 30 Mar 2020 07:16:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FMp7NcWm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729474AbgC3HQG (ORCPT ); Mon, 30 Mar 2020 03:16:06 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:37916 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729378AbgC3HQF (ORCPT ); Mon, 30 Mar 2020 03:16:05 -0400 Received: by mail-pg1-f195.google.com with SMTP id x7so8252612pgh.5; Mon, 30 Mar 2020 00:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zf318LKZ+rY1+2PNaHw1wx9Zylx8ChMocj3SCcUJF74=; b=FMp7NcWmv8vjZvxGOHZpB+PA6z+v+TcpLQeQFUdatEY3xc02Li4mEIPyUz4EKzoIr+ rcvWNfBK3vRV3Nr9Bna7sE70SIE0IiP+CH0paqsLjwEU8bUg7YcIa42QQ/iuq4InyA+Y 5AEEG/mrtf0w8vDlqrZasFk3Vhp8DrFo7IQzHzG6KDeE8IeVIIvTXLGZLHcNXC1+nKo/ GvbdT5tipW0VB71JuGCmyqGsRqyHFkFP9Wu343ao6sfp5OxDKACBHbQPVTPuMOCSOsxY WFh09RTacLF0N9xsva+eUwAhoGROvefpLyJJ06EJmO298M5HgJJH4eL1+AyVt39qImYJ /cCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zf318LKZ+rY1+2PNaHw1wx9Zylx8ChMocj3SCcUJF74=; b=iFO+UHi1c4bc+a+F7YSjMbcu/3rTS65OYIq0hjEMtTc4hrwFPEtnPYtTGJ1zoeJiDE CLE85zMPwwwZ3v0mLFGohMaWmyr4BpE1VewFNoDlr1/Lf1VfZ3iMqaK9yOP0K1udRAeM mO3JOrdfNGnyfKYH+ygmQZMAFUJwepQ2MRmf65lo3rX6AqBBzeYatSEIsgBMczg7/Pdc SaMOtp4Mya+EN0xfxIYCtxCjuDDyCNrPUtrZFW0B8QVbBVZ4nGWCGXvhQWFeMzPk5swZ BjtOluyDzM5PTLyofc71J7yEo1FR77Iq2JIx4nDuXCwa+ZHnDLgIjvIucbqysa4KuoDD l7xw== X-Gm-Message-State: ANhLgQ1fzrYLbvPnjiS5iT0WGzhezpENbroapcynVXyNguBtXOfQd2l5 NcZZXKhRYFXkuuvYdTZeNtE= X-Google-Smtp-Source: ADFU+vu0uBcmfyfqGGWsPG3Ofmh7TXNtcF7yPEmGrzqO5HpHYU0VQGgkVK956IGOcqWc99M3M9YDJA== X-Received: by 2002:aa7:9433:: with SMTP id y19mr11665500pfo.233.1585552564353; Mon, 30 Mar 2020 00:16:04 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id l1sm9490484pje.9.2020.03.30.00.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 00:16:03 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH 3/4] clk: sprd: add dt-bindings include for mipi_csi_xx clocks Date: Mon, 30 Mar 2020 15:14:50 +0800 Message-Id: <20200330071451.7899-4-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200330071451.7899-1-zhang.lyra@gmail.com> References: <20200330071451.7899-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang Acked-by: Rob Herring --- include/dt-bindings/clock/sprd,sc9863a-clk.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/sprd,sc9863a-clk.h b/include/dt-bindings/clock/sprd,sc9863a-clk.h index 901ba59676c2..4e030421641f 100644 --- a/include/dt-bindings/clock/sprd,sc9863a-clk.h +++ b/include/dt-bindings/clock/sprd,sc9863a-clk.h @@ -308,6 +308,11 @@ #define CLK_MCPHY_CFG_EB 14 #define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) +#define CLK_MIPI_CSI 0 +#define CLK_MIPI_CSI_S 1 +#define CLK_MIPI_CSI_M 2 +#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1) + #define CLK_SIM0_EB 0 #define CLK_IIS0_EB 1 #define CLK_IIS1_EB 2 From patchwork Mon Mar 30 07:14:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 11464875 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C3A9D15AB for ; Mon, 30 Mar 2020 07:16:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A258A20787 for ; Mon, 30 Mar 2020 07:16:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TZL3JFXi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729486AbgC3HQJ (ORCPT ); Mon, 30 Mar 2020 03:16:09 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:35305 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729460AbgC3HQJ (ORCPT ); Mon, 30 Mar 2020 03:16:09 -0400 Received: by mail-pg1-f195.google.com with SMTP id k5so6041755pga.2; Mon, 30 Mar 2020 00:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gcJfZUp4ynRYK76cXvZbCVqckHbyLVdV4ZyTuUAfMgw=; b=TZL3JFXiPGpYtlMni4teQYa0b9hmam1TZOnRqX2AhjSOrveUjcyMMyhYP7SEHeY31n K0gx/euv6jphTSmPqfGnjRSFjIdvXxPhUQ6SOKVDoZXi6MDtbXXCWOhPa0NCOZieJ2dm XO2Vfc/Zk35vB2pDlwhJNEOo0NSdjg+WoJgKO/jWaYXh/9oAhWCpgjLmXyRo+MeUbuBb vLRSaTHn5n422pD2nrWa7SQAFA7Y06Ev64G/0hAFuDAbRUQJ8Q+TJZxkLYMnXSnW8w+U D0tbVCYUjp73sp8a1mXwE1LN9bMJtHwHjEUhb4iaZuV6xQXJtpSiQWSuBJqXrfF4a+Xm JqoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gcJfZUp4ynRYK76cXvZbCVqckHbyLVdV4ZyTuUAfMgw=; b=FAblaruxmZ9+ddsgqcJaud2ZtUyxFrakA1NEQ385eAxFQwB//P7VoMkEnSJHVp3PUe P/Z1la+WbmECkTTDQrcn+EgnwAMFTk/Egok+cRhbv+Z2Py1371+wvhIcFIzbUXuDqHNo arE3gl2altfPdnQvItgyDxVMJfnf2e5LpJH5JD8da2Upy5nb/wxNyJjkhjm9OqhFoHcy AP3cPmAk3giwmdVIxYY9/vZfJ/hJ4ubex4kERbYLHEzkin/F2awZ3WpJNYrTZTD5a8da huJ0oaOJ0AlDySD4RE/3nxPvjrPlJPcZbbZo8+x0BDvG1yYTIlwaF9ikGBbWw82pSci1 RQxQ== X-Gm-Message-State: AGi0Pua8wWo719eKGjiPVl85RoS4ibg4GiFRew9cuxl3wKXs/28ozcC1 YK7mpABR+AD4UcP8c7ixAQedr4Ql X-Google-Smtp-Source: APiQypL4b9Yt1C3OKYXQ85WYhYCwCkwrZ7hOQkmE+Ysqu7PDnWNX4HLoSA5p8CkcG0mTLVvmSKEYGg== X-Received: by 2002:a62:870c:: with SMTP id i12mr4742503pfe.41.1585552568504; Mon, 30 Mar 2020 00:16:08 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id l1sm9490484pje.9.2020.03.30.00.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 00:16:07 -0700 (PDT) From: Chunyan Zhang To: Stephen Boyd , Michael Turquette , Rob Herring , Mark Rutland Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Chunyan Zhang , Chunyan Zhang Subject: [PATCH 4/4] clk: sprd: add mipi_csi_xx gate clocks Date: Mon, 30 Mar 2020 15:14:51 +0800 Message-Id: <20200330071451.7899-5-zhang.lyra@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200330071451.7899-1-zhang.lyra@gmail.com> References: <20200330071451.7899-1-zhang.lyra@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Chunyan Zhang mipi_csi_xx clocks are used by camera sensors. Signed-off-by: Chunyan Zhang --- drivers/clk/sprd/sc9863a-clk.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c index a0631f7756cf..24f064262814 100644 --- a/drivers/clk/sprd/sc9863a-clk.c +++ b/drivers/clk/sprd/sc9863a-clk.c @@ -1615,6 +1615,36 @@ static const struct sprd_clk_desc sc9863a_mm_gate_desc = { .hw_clks = &sc9863a_mm_gate_hws, }; +/* mm clocks */ +static SPRD_GATE_CLK_HW(mipi_csi_clk, "mipi-csi-clk", &mahb_ckg_eb.common.hw, + 0x20, BIT(16), 0, SPRD_GATE_NON_AON); +static SPRD_GATE_CLK_HW(mipi_csi_s_clk, "mipi-csi-s-clk", &mahb_ckg_eb.common.hw, + 0x24, BIT(16), 0, SPRD_GATE_NON_AON); +static SPRD_GATE_CLK_HW(mipi_csi_m_clk, "mipi-csi-m-clk", &mahb_ckg_eb.common.hw, + 0x28, BIT(16), 0, SPRD_GATE_NON_AON); + +static struct sprd_clk_common *sc9863a_mm_clk_clks[] = { + /* address base is 0x60900000 */ + &mipi_csi_clk.common, + &mipi_csi_s_clk.common, + &mipi_csi_m_clk.common, +}; + +static struct clk_hw_onecell_data sc9863a_mm_clk_hws = { + .hws = { + [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, + [CLK_MIPI_CSI_S] = &mipi_csi_s_clk.common.hw, + [CLK_MIPI_CSI_M] = &mipi_csi_m_clk.common.hw, + }, + .num = CLK_MM_CLK_NUM, +}; + +static const struct sprd_clk_desc sc9863a_mm_clk_desc = { + .clk_clks = sc9863a_mm_clk_clks, + .num_clk_clks = ARRAY_SIZE(sc9863a_mm_clk_clks), + .hw_clks = &sc9863a_mm_clk_hws, +}; + static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0, 0x1000, BIT(0), 0, 0); static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0, @@ -1737,6 +1767,8 @@ static const struct of_device_id sprd_sc9863a_clk_ids[] = { .data = &sc9863a_aonapb_gate_desc }, { .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */ .data = &sc9863a_mm_gate_desc }, + { .compatible = "sprd,sc9863a-mm-clk", /* 0x60900000 */ + .data = &sc9863a_mm_clk_desc }, { .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */ .data = &sc9863a_apapb_gate_desc }, { }