From patchwork Mon Mar 30 22:11:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11466401 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8F5814B4 for ; Mon, 30 Mar 2020 22:11:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 86C2220784 for ; Mon, 30 Mar 2020 22:11:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="EF4TwF51" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730982AbgC3WLc (ORCPT ); Mon, 30 Mar 2020 18:11:32 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:37082 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729142AbgC3WLb (ORCPT ); Mon, 30 Mar 2020 18:11:31 -0400 Received: by mail-wr1-f66.google.com with SMTP id w10so23652435wrm.4; Mon, 30 Mar 2020 15:11:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PKd+/SwaFc/8uopc54d2zl4DkYvufR8oUaq7MhGEZW0=; b=EF4TwF51AfUN1lIwRYek6+eBZzsQcUmm8bYWbbXGb2mnRZLl1bp+BFHcJbg2P+stbv NFnVkDzaV5X/I1su61qbHRah5jskYUf8kzjpDHNCjDHsl+rLSdm2aNoiJHyHtUwCWlGb laEVNC+Lv9Y6JUG3Dm0b2NdJ1OOB7+C0q7JHoFjrKJJlk2OKm4D9OdSM+K3TIPl9PnqJ a+XHAid03t4cTctRHHHdyUgvwvRMn1GUeHsB8hQYKgRFEcto6iQQc4cV83R+otSC1b61 cavCZ78jaDH7OScxrngocBBYwK5PTlB9YVMNqmftrhkqdokN79IZHIkPZIHP06aKzdga BaAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PKd+/SwaFc/8uopc54d2zl4DkYvufR8oUaq7MhGEZW0=; b=ajhQV5fqdqHdh38EDzTZAbFOpYynBoNj4p5UIflgVvEI1/VfOMLObfdvm1h1goqZLk VhNPa3v7/g3CTwHn8m4E0XGislVjADZ4s9BMNDx8nKEohnTg1gGmI4l/zm6AagUEHwhh 5szFzB1fUG4UMHSRM0T+DPflmbanrB4mEfWADgKu+sarGmugaTE+pSu1SZW6orwnvbZ4 HUiNIhPlIXzZ5nSVaJeqD069rf1w7lLxG+A33T0SszZwioyUQcbFxLokb+NXID62xqno 7mM3qiUAwUGd01IJJhei5VcHbx1Fh8EBxtkwDhaHpJObyWsGRLasr6WD0EUXudL3PCet dbVg== X-Gm-Message-State: ANhLgQ2zixfJnue0b7yP6N7JBEpiww0fbpct3Tb+uYGda3KqWWEBAXgO a4Gr84Bs8mZujgRjXYBaMqs= X-Google-Smtp-Source: ADFU+vuzqjpSAFP9jLZ0jvH6APY0YiXy3oxdro+kCvlvWkDnfGPkNvMs4WdyNjCnUsk3/+L+tWmfGA== X-Received: by 2002:a5d:630b:: with SMTP id i11mr16188951wru.94.1585606289301; Mon, 30 Mar 2020 15:11:29 -0700 (PDT) Received: from localhost.localdomain (p200300F13710ED00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:28 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [RFC v1 1/5] clk: meson: gxbb: Prepare the GPU clock tree to change at runtime Date: Tue, 31 Mar 2020 00:11:00 +0200 Message-Id: <20200330221104.3163788-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also populate set_rate requests from the divider to the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/gxbb.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 5fd6a574f8c3..0a68af6eec3d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -957,7 +957,9 @@ static struct clk_regmap gxbb_sar_adc_clk = { /* * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) - * muxed by a glitch-free switch. + * muxed by a glitch-free switch. The CCF can manage this glitch-free + * mux because it does top-to-bottom updates the each clock tree and + * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { @@ -980,14 +982,15 @@ static struct clk_regmap gxbb_mali_0_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", .ops = &clk_regmap_mux_ops, - /* - * bits 10:9 selects from 8 possible parents: - * xtal, gp0_pll, mpll2, mpll1, fclk_div7, - * fclk_div4, fclk_div3, fclk_div5 - */ .parent_data = gxbb_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -1004,7 +1007,7 @@ static struct clk_regmap gxbb_mali_0_div = { &gxbb_mali_0_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -1020,7 +1023,7 @@ static struct clk_regmap gxbb_mali_0 = { &gxbb_mali_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -1033,14 +1036,15 @@ static struct clk_regmap gxbb_mali_1_sel = { .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", .ops = &clk_regmap_mux_ops, - /* - * bits 10:9 selects from 8 possible parents: - * xtal, gp0_pll, mpll2, mpll1, fclk_div7, - * fclk_div4, fclk_div3, fclk_div5 - */ .parent_data = gxbb_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -1057,7 +1061,7 @@ static struct clk_regmap gxbb_mali_1_div = { &gxbb_mali_1_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -1073,7 +1077,7 @@ static struct clk_regmap gxbb_mali_1 = { &gxbb_mali_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -1093,7 +1097,7 @@ static struct clk_regmap gxbb_mali = { .ops = &clk_regmap_mux_ops, .parent_hws = gxbb_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Mon Mar 30 22:11:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11466403 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D53E281 for ; Mon, 30 Mar 2020 22:11:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B2BBF20784 for ; Mon, 30 Mar 2020 22:11:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="EejkddiJ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730987AbgC3WLd (ORCPT ); Mon, 30 Mar 2020 18:11:33 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36804 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728987AbgC3WLc (ORCPT ); Mon, 30 Mar 2020 18:11:32 -0400 Received: by mail-wr1-f66.google.com with SMTP id 31so23568696wrs.3; Mon, 30 Mar 2020 15:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MdDlaK3jLN/q9KcoyP33Chc7uvr3eCaMbY+7EESj0As=; b=EejkddiJCEPU8jCPYEqGgLrI766UTSVP81xsECLV/sI5ZxSNQI+IBeTYqywvQiQwpd jizrNf5HboqfV1xdwyv9bR/1B+GDxkQ/oNit9/Cz/4jFBonU7K4TuFHcUmoRDocz77mZ A7nfupQ7qilNBOA/PiQxGhiDHCtPuLDrMB+89iaatZlN1RkKwVLJRtgLbPFHII9JZOsV Fo/5pJ2w8Dx3lBz3om4roa1BHfL+JgvG86CwfM730MoQBABygMPLBBCbC3MMQoLrbZb7 /Gt4dwYUFDL8WRM5vsLMdpPIByS7GMShGaFjei5C5xaHLoQ9A1YxmbqURvF4UpI5omsn Pv/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MdDlaK3jLN/q9KcoyP33Chc7uvr3eCaMbY+7EESj0As=; b=hLr4YqLL6+DQAXwwilAMgCo7PPNWZydg8/Sis7QeBQbcupO9ENiPf7DzM32E/cdRnF Q9ijughANSFoseBBUgcrfjcb0MdXsLDZ7/3gOB3VOXfZJhn1CTYS+/INeV+8d6RHy6He W5d+KlOi02fCbj0rnrL7O1x1NK/eSiDZE31ZjDqz3Du8esnVyYIpTPTGzWXuiwRVIXqx 1MNNsdWqn/ZtKckbP5ynAZ3MUprYqN2UhEOx1ntflXmuIB0uNujJ4gK5Uc3e4+JAeFp/ sCr9FgMvKLAFGObkIw61hDNpjhSSyfiQNDxmPHi1N8ND8A+HYN8nyEpDv3uahiiEJGUu HLSw== X-Gm-Message-State: ANhLgQ17ywB+7M9OiPC2jTuGQjwpNx3inPLoRUh04x7RoYw+h+OyYVdt jUnkfQ1SZSrwDhe5P8UlfvE= X-Google-Smtp-Source: ADFU+vvgELv6WlxBfdmfHasYH7xckVLjjI/gfkH1djbfjyg5T6s6EazSzp1kVoD4jaIVPog2bhKWUQ== X-Received: by 2002:a5d:5228:: with SMTP id i8mr17301089wra.156.1585606290341; Mon, 30 Mar 2020 15:11:30 -0700 (PDT) Received: from localhost.localdomain (p200300F13710ED00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:29 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [RFC v1 2/5] clk: meson: g12a: Prepare the GPU clock tree to change at runtime Date: Tue, 31 Mar 2020 00:11:01 +0200 Message-Id: <20200330221104.3163788-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also populate set_rate requests from the divider to the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/g12a.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index fad616cac01e..30c15766ebb1 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3702,7 +3702,9 @@ static struct clk_regmap g12a_hdmi = { /* * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) - * muxed by a glitch-free switch. + * muxed by a glitch-free switch. The CCF can manage this glitch-free + * mux because it does top-to-bottom updates the each clock tree and + * switches to the "inactive" one when CLK_SET_RATE_GATE is set. */ static const struct clk_parent_data g12a_mali_0_1_parent_data[] = { { .fw_name = "xtal", }, @@ -3726,7 +3728,13 @@ static struct clk_regmap g12a_mali_0_sel = { .ops = &clk_regmap_mux_ops, .parent_data = g12a_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -3743,7 +3751,7 @@ static struct clk_regmap g12a_mali_0_div = { &g12a_mali_0_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3759,7 +3767,7 @@ static struct clk_regmap g12a_mali_0 = { &g12a_mali_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -3774,7 +3782,13 @@ static struct clk_regmap g12a_mali_1_sel = { .ops = &clk_regmap_mux_ops, .parent_data = g12a_mali_0_1_parent_data, .num_parents = 8, - .flags = CLK_SET_RATE_NO_REPARENT, + /* + * Don't request the parent to change the rate because + * all GPU frequencies can be derived from the fclk_* + * clocks and one special GP0_PLL setting. This is + * important because we need the MPLL clocks for audio. + */ + .flags = 0, }, }; @@ -3791,7 +3805,7 @@ static struct clk_regmap g12a_mali_1_div = { &g12a_mali_1_sel.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -3807,7 +3821,7 @@ static struct clk_regmap g12a_mali_1 = { &g12a_mali_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -3827,7 +3841,7 @@ static struct clk_regmap g12a_mali = { .ops = &clk_regmap_mux_ops, .parent_hws = g12a_mali_parent_hws, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Mon Mar 30 22:11:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11466409 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 09AA514B4 for ; Mon, 30 Mar 2020 22:11:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD40620786 for ; Mon, 30 Mar 2020 22:11:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="O2VkcrLo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730994AbgC3WLe (ORCPT ); Mon, 30 Mar 2020 18:11:34 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:40789 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730980AbgC3WLd (ORCPT ); Mon, 30 Mar 2020 18:11:33 -0400 Received: by mail-wm1-f66.google.com with SMTP id a81so506908wmf.5; Mon, 30 Mar 2020 15:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rH18uADPcvY9iN4ZlqKSVAo4EwI8zrMKYS+ddwe06gM=; b=O2VkcrLoK9at2xeoNDR0dKr6GCXJ6GvgAIt8d5J00iWaeidqCAgYA/Ecvmzx7KpyPk iY1iMNaGQDy8uz5sxfZ/Kpuz9DSKPPj9ViKBS4lc0d1Oz5X1qMtEeIV/MNqjgG2CoaXv umHsW1zY/2z+M2ELF1oj5boUhcs1Koxg9hjF+ASA/LHYFXUlgH7LFXRqX/YHma5fdRMi Ls6kcDu9tq92JUWxW2Xdd78Q/DDCyRG+Oj+jmR9j7X8R8eIRQhbAiz6IZn2ECqJq2zFV 54l5hYPtp8ork5A5rJEeXBKUdtVG+FuDrOJl+mibehlFUSKKiT9qngF9ejLc3puUy0yp Tz+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rH18uADPcvY9iN4ZlqKSVAo4EwI8zrMKYS+ddwe06gM=; b=JARoWeswA5LAEWTncfDmattExH/SIy+16i+c14zhGMRQYJrFBxN+8opgxu+csXP+In 9qABD3UKZV6gkawzfs94oduAgKqbK8zGo6VGC464a0aVkn2zl+0PTKO4/OSE1A48ibNE Kq0mJDbFxf4bxDZEn+yloPfOuwjd2eJN11Lhyt5Jhjcnw+1pqmSuRxo5wdsbbXrG3rML g+6oF//FZZmLTcsuWtilQwCwXJGuoHej/ja8W7ORdFlMJvzWZAtctQDgHlMJVNTQygdB Vzmrsh+o51XuAmDZd7HwPm7v6PXvGBDXk6qIHm3tsVZASTcF45K9EGc9S9i8o5RJDfh0 WpGw== X-Gm-Message-State: ANhLgQ0J8JyMB/vxI6d3SkmEym7dCJHvlOPugSEsjCW1frnAISWDDCO8 Khdai9qHt1p06k+C/uaDATaeDF9O X-Google-Smtp-Source: ADFU+vv/JR5vRCpxN4sqzSkYjKWLWQFcPK5nZzBQVW0eC/j4OvXq+vgaLQoqul21ksctM5TC0GQyXg== X-Received: by 2002:a1c:e904:: with SMTP id q4mr234551wmc.84.1585606291646; Mon, 30 Mar 2020 15:11:31 -0700 (PDT) Received: from localhost.localdomain (p200300F13710ED00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:31 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [RFC v1 3/5] arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFS Date: Tue, 31 Mar 2020 00:11:02 +0200 Message-Id: <20200330221104.3163788-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl --- .../boot/dts/amlogic/meson-gx-mali450.dtsi | 61 +++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 51 ++++------------ .../boot/dts/amlogic/meson-gxl-mali.dtsi | 46 +++----------- 3 files changed, 81 insertions(+), 77 deletions(-) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi new file mode 100644 index 000000000000..f9771b51c852 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gx-mali450.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 BayLibre SAS + * Author: Neil Armstrong + */ + +/ { + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <950000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <950000>; + }; + opp-285714285 { + opp-hz = /bits/ 64 <285714285>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + }; + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <950000>; + }; + opp-744000000 { + opp-hz = /bits/ 64 <744000000>; + opp-microvolt = <950000>; + }; + }; +}; + +&apb { + mali: gpu@c0000 { + compatible = "arm,mali-450"; + reg = <0x0 0xc0000 0x0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp", "pmu", + "pp0", "ppmmu0", "pp1", "ppmmu1", + "pp2", "ppmmu2"; + operating-points-v2 = <&gpu_opp_table>; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 0cb40326b0d3..e43b330129c7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -4,6 +4,7 @@ */ #include "meson-gx.dtsi" +#include "meson-gx-mali450.dtsi" #include #include #include @@ -241,46 +242,6 @@ mux { }; }; -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; -}; - &cbus { spifc: spi@8c80 { compatible = "amlogic,meson-gxbb-spifc"; @@ -362,6 +323,16 @@ &i2c_C { clocks = <&clkc CLKID_I2C>; }; +&mali { + compatible = "amlogic,meson-gxbb-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; +}; + &periphs { pinctrl_periphs: pinctrl@4b0 { compatible = "amlogic,meson-gxbb-periphs-pinctrl"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi index 6aaafff674f9..478e755cc87c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-mali.dtsi @@ -4,42 +4,14 @@ * Author: Neil Armstrong */ -&apb { - mali: gpu@c0000 { - compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; - reg = <0x0 0xc0000 0x0 0x40000>; - interrupts = , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", "gpmmu", "pp", "pmu", - "pp0", "ppmmu0", "pp1", "ppmmu1", - "pp2", "ppmmu2"; - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; +#include "meson-gx-mali450.dtsi" - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_GP0_PLL>, - <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <0>, /* Do Nothing */ - <&clkc CLKID_GP0_PLL>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <744000000>, - <0>, /* Do Nothing */ - <744000000>, - <0>; /* Do Nothing */ - }; +&mali { + compatible = "amlogic,meson-gxl-mali", "arm,mali-450"; + + clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; + clock-names = "bus", "core"; + + assigned-clocks = <&clkc CLKID_GP0_PLL>; + assigned-clock-rates = <744000000>; }; From patchwork Mon Mar 30 22:11:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11466411 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3DA241667 for ; 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[2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:32 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [RFC v1 4/5] arm64: dts: amlogic: meson-gxm: add the Mali OPP table and use DVFS Date: Tue, 31 Mar 2020 00:11:03 +0200 Message-Id: <20200330221104.3163788-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the OPP table for the Mali-T820 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Signed-off-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 45 ++++++++++++++-------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index b6f89f108e28..0f1d1cf4248f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -82,6 +82,35 @@ cpu7: cpu@103 { #cooling-cells = <2>; }; }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <950000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <950000>; + }; + opp-285714285 { + opp-hz = /bits/ 64 <285714285>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + }; + opp-666666666 { + opp-hz = /bits/ 64 <666666666>; + opp-microvolt = <950000>; + }; + }; }; &apb { @@ -106,21 +135,7 @@ mali: gpu@c0000 { interrupt-names = "job", "mmu", "gpu"; clocks = <&clkc CLKID_MALI>; resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <666666666>, - <0>; /* Do Nothing */ + operating-points-v2 = <&gpu_opp_table>; }; }; From patchwork Mon Mar 30 22:11:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11466407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B45E381 for ; Mon, 30 Mar 2020 22:11:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 935D12082F for ; Mon, 30 Mar 2020 22:11:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="B1Yi4hJe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728987AbgC3WLg (ORCPT ); Mon, 30 Mar 2020 18:11:36 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:35267 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730993AbgC3WLg (ORCPT ); Mon, 30 Mar 2020 18:11:36 -0400 Received: by mail-wm1-f68.google.com with SMTP id i19so539145wmb.0; Mon, 30 Mar 2020 15:11:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qzCUFuMkzWlLXqOmVXLBXxeE6kPrzuWsI5J2b3JrmKY=; b=B1Yi4hJe9+jP1oYxumDlnQbGxnGbQdeD6mr579nVjX9OZZyUZ8ZLyJ6jYNz9MBj1bx 7maTetDDohQQUmSd5H3Bo71qQkiExseTWyE69vSfxXUpIQkBoYOVsVLlHvz2160L3s55 QaLzK0+XdB+D2QBN7ymd6vDgY6yu1wRmxSHDMRiSB9Nnqd4vMeAB7BovKAoK7v5uVF5M F65EwRTVh0KZvIv/uND1prJXmqY3a7Gvnhv3sdr4QtyqwhfGlfGtEqPjiwzXgfzWyby5 CovMn2lfBAf/Nte7H15w0e2jvI0kcYNhtrItVakqPwm7VHgAG/xsERYOQRHXXpeCZUOW ytfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qzCUFuMkzWlLXqOmVXLBXxeE6kPrzuWsI5J2b3JrmKY=; b=eF9u2Q/iLFl3NM8TKDV8vYeZDuFmOKHFTj4C5eiU1dmcIWtgbUbo4jLqOqN77oDbNv ilFEdvv/eXaU1qchhNpt1VgEbmIJp36gvtCUK/xI0/dnq3GY/mbPOvKGx4n1tmNjWiV5 G1bKGB6ip6CK6rc7/3NKlbpNXW0JjNGJS4CrljlRzPANZYd0g9PvOdPJvWowqsHlMxjP aY8AOAc5wDZ3OWOt8wPzjuPtbki/vG+z9ZcMSBLN4Xo3ZH2gzFVBDDrltEqclfyhWD7y jpyjcyLbWqnioWeM/AfRKGD6pvquoRirLYNM7NMHR+lwPN45oKJRfQ/IyXdnedLszIAF ewnA== X-Gm-Message-State: ANhLgQ0JsOw7FXHartU83Ur9fHBqVEtrHgC7Hh6wVHuT5PUOGlDceqI5 qJA6FKJCyjs4haJe8cgMluE= X-Google-Smtp-Source: ADFU+vv9tfk0eQLYelRcKNSFwd6CAWgH4qjrJ4Aiglq2T0D+CdLr1vDM+HDBUlMkqJzRgb5BkDwq+g== X-Received: by 2002:a1c:e203:: with SMTP id z3mr216866wmg.71.1585606293721; Mon, 30 Mar 2020 15:11:33 -0700 (PDT) Received: from localhost.localdomain (p200300F13710ED00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3710:ed00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id b187sm1260509wmc.14.2020.03.30.15.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2020 15:11:33 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, jbrunet@baylibre.com, narmstrong@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Martin Blumenstingl Subject: [RFC v1 5/5] arm64: dts: amlogic: meson-g12: add the Mali OPP table and use DVFS Date: Tue, 31 Mar 2020 00:11:04 +0200 Message-Id: <20200330221104.3163788-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> References: <20200330221104.3163788-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add the OPP table for the Mali Bifrost GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Signed-off-by: Martin Blumenstingl --- .../boot/dts/amlogic/meson-g12-common.dtsi | 49 +++++++++++++------ 1 file changed, 34 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 0882ea215b88..3f2c7d0802af 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -52,6 +52,39 @@ efuse: efuse { secure-monitor = <&sm>; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-124999998 { + opp-hz = /bits/ 64 <124999998>; + opp-microvolt = <800000>; + }; + opp-249999996 { + opp-hz = /bits/ 64 <249999996>; + opp-microvolt = <800000>; + }; + opp-285714281 { + opp-hz = /bits/ 64 <285714281>; + opp-microvolt = <800000>; + }; + opp-399999994 { + opp-hz = /bits/ 64 <399999994>; + opp-microvolt = <800000>; + }; + opp-499999992 { + opp-hz = /bits/ 64 <499999992>; + opp-microvolt = <800000>; + }; + opp-666666656 { + opp-hz = /bits/ 64 <666666656>; + opp-microvolt = <800000>; + }; + opp-799999987 { + opp-hz = /bits/ 64 <799999987>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -2349,21 +2382,7 @@ mali: gpu@ffe40000 { interrupt-names = "job", "mmu", "gpu"; clocks = <&clkc CLKID_MALI>; resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; - - /* - * Mali clocking is provided by two identical clock paths - * MALI_0 and MALI_1 muxed to a single clock by a glitch - * free mux to safely change frequency while running. - */ - assigned-clocks = <&clkc CLKID_MALI_0_SEL>, - <&clkc CLKID_MALI_0>, - <&clkc CLKID_MALI>; /* Glitch free mux */ - assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, - <0>, /* Do Nothing */ - <&clkc CLKID_MALI_0>; - assigned-clock-rates = <0>, /* Do Nothing */ - <800000000>, - <0>; /* Do Nothing */ + operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; }; };