From patchwork Tue Mar 31 21:46:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11468417 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E823015AB for ; Tue, 31 Mar 2020 21:46:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C6A3420838 for ; Tue, 31 Mar 2020 21:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728245AbgCaVqU (ORCPT ); Tue, 31 Mar 2020 17:46:20 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:50362 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730014AbgCaVqU (ORCPT ); Tue, 31 Mar 2020 17:46:20 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 25A652970A8 From: Enric Balletbo i Serra To: mark.rutland@arm.com, ck.hu@mediatek.com, sboyd@kernel.org, ulrich.hecht+renesas@gmail.com Cc: matthias.bgg@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Collabora Kernel ML , Matthias Brugger , linux-clk@vger.kernel.org, matthias.bgg@gmail.com, drinkcat@chromium.org, hsinyi@chromium.org, linux-mediatek@lists.infradead.org Subject: [PATCH 1/4] soc: mediatek: Enable mmsys driver by default if Mediatek arch is selected Date: Tue, 31 Mar 2020 23:46:06 +0200 Message-Id: <20200331214609.1742152-1-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The mmsys driver supports only MT8173 device for now, but like other system controllers is an important piece for other Mediatek devices. Actually it depends on the mt8173 clock specific driver but that dependency is not real as it can build without the clock driver. Instead of depends on a specific model, make the driver depends on the generic ARCH_MEDIATEK and enable by default so other Mediatek devices can start using it without flood the Kconfig. Signed-off-by: Enric Balletbo i Serra --- drivers/soc/mediatek/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index e84513318725..59a56cd790ec 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -46,8 +46,7 @@ config MTK_SCPSYS config MTK_MMSYS bool "MediaTek MMSYS Support" - depends on COMMON_CLK_MT8173_MMSYS - default COMMON_CLK_MT8173_MMSYS + default ARCH_MEDIATEK help Say yes here to add support for the MediaTek Multimedia Subsystem (MMSYS). From patchwork Tue Mar 31 21:46:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11468425 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC0E917EA for ; Tue, 31 Mar 2020 21:46:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C52962080C for ; Tue, 31 Mar 2020 21:46:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731501AbgCaVqX (ORCPT ); Tue, 31 Mar 2020 17:46:23 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:50386 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730014AbgCaVqW (ORCPT ); Tue, 31 Mar 2020 17:46:22 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 4DA9B2970AB From: Enric Balletbo i Serra To: mark.rutland@arm.com, ck.hu@mediatek.com, sboyd@kernel.org, ulrich.hecht+renesas@gmail.com Cc: matthias.bgg@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Collabora Kernel ML , Matthias Brugger , linux-clk@vger.kernel.org, matthias.bgg@gmail.com, drinkcat@chromium.org, hsinyi@chromium.org, linux-mediatek@lists.infradead.org, Allison Randal , Greg Kroah-Hartman , Kate Stewart , Michael Turquette , Richard Fontana , Thomas Gleixner Subject: [PATCH 2/4] clk / soc: mediatek: Bind clock and gpu driver for mt2712 Date: Tue, 31 Mar 2020 23:46:07 +0200 Message-Id: <20200331214609.1742152-2-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200331214609.1742152-1-enric.balletbo@collabora.com> References: <20200331214609.1742152-1-enric.balletbo@collabora.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that the mmsys driver is the top-level entry point for the multimedia subsystem, we could bind the clock and the gpu driver on those devices that is expected to work, so the drm driver is intantiated by the mmsys driver and display, hopefully, working again on those devices. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chun-Kuang Hu --- If you have this hardware, please kindly provide your tested tag. Only build tested. drivers/clk/mediatek/clk-mt2712-mm.c | 8 ++------ drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c index 1c5948be35f3..660c1f63293f 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -128,9 +128,10 @@ static const struct mtk_gate mm_clks[] = { static int clk_mt2712_mm_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; struct clk_onecell_data *clk_data; int r; - struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); @@ -146,11 +147,6 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev) return r; } -static const struct of_device_id of_match_clk_mt2712_mm[] = { - { .compatible = "mediatek,mt2712-mmsys", }, - {} -}; - static struct platform_driver clk_mt2712_mm_drv = { .probe = clk_mt2712_mm_probe, .driver = { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 05e322c9c301..c7d3b7bcfa32 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -80,6 +80,10 @@ struct mtk_mmsys_driver_data { const char *clk_driver; }; +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .clk_driver = "clk-mt2712-mm", +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", }; @@ -319,6 +323,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data, + }, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data, From patchwork Tue Mar 31 21:46:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11468427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A33B15AB for ; Tue, 31 Mar 2020 21:46:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E58E120838 for ; Tue, 31 Mar 2020 21:46:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731516AbgCaVq0 (ORCPT ); Tue, 31 Mar 2020 17:46:26 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:50416 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731429AbgCaVqY (ORCPT ); Tue, 31 Mar 2020 17:46:24 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 015C3297173 From: Enric Balletbo i Serra To: mark.rutland@arm.com, ck.hu@mediatek.com, sboyd@kernel.org, ulrich.hecht+renesas@gmail.com Cc: matthias.bgg@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Collabora Kernel ML , Matthias Brugger , linux-clk@vger.kernel.org, matthias.bgg@gmail.com, drinkcat@chromium.org, hsinyi@chromium.org, linux-mediatek@lists.infradead.org, Allison Randal , Greg Kroah-Hartman , Kate Stewart , Michael Turquette , Richard Fontana , Thomas Gleixner Subject: [PATCH 3/4] clk / soc: mediatek: Bind clock and gpu driver for mt2701 Date: Tue, 31 Mar 2020 23:46:08 +0200 Message-Id: <20200331214609.1742152-3-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200331214609.1742152-1-enric.balletbo@collabora.com> References: <20200331214609.1742152-1-enric.balletbo@collabora.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that the mmsys driver is the top-level entry point for the multimedia subsystem, we could bind the clock and the gpu driver on those devices that is expected to work, so the drm driver is intantiated by the mmsys driver and display, hopefully, working again. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chun-Kuang Hu --- If you have this hardware, please kindly provide your tested tag. Only build tested. drivers/clk/mediatek/clk-mt2701-mm.c | 8 ++------ drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/clk-mt2701-mm.c index 054b597d4a73..3a4e895a3d0f 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -79,16 +79,12 @@ static const struct mtk_gate mm_clks[] = { GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14), }; -static const struct of_device_id of_match_clk_mt2701_mm[] = { - { .compatible = "mediatek,mt2701-mmsys", }, - {} -}; - static int clk_mt2701_mm_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; + struct device_node *node = dev->parent->of_node; struct clk_onecell_data *clk_data; int r; - struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_MM_NR); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index c7d3b7bcfa32..cacafe23c823 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -80,6 +80,10 @@ struct mtk_mmsys_driver_data { const char *clk_driver; }; +static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { + .clk_driver = "clk-mt2701-mm", +}; + static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { .clk_driver = "clk-mt2712-mm", }; @@ -323,6 +327,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } static const struct of_device_id of_match_mtk_mmsys[] = { + { + .compatible = "mediatek,mt2701-mmsys", + .data = &mt2701_mmsys_driver_data, + }, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data, From patchwork Tue Mar 31 21:46:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11468419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A45E5159A for ; Tue, 31 Mar 2020 21:46:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B0B92080C for ; Tue, 31 Mar 2020 21:46:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731426AbgCaVq1 (ORCPT ); Tue, 31 Mar 2020 17:46:27 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:50432 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731511AbgCaVqZ (ORCPT ); Tue, 31 Mar 2020 17:46:25 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 80572297179 From: Enric Balletbo i Serra To: mark.rutland@arm.com, ck.hu@mediatek.com, sboyd@kernel.org, ulrich.hecht+renesas@gmail.com Cc: matthias.bgg@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Collabora Kernel ML , Matthias Brugger , linux-clk@vger.kernel.org, matthias.bgg@gmail.com, drinkcat@chromium.org, hsinyi@chromium.org, linux-mediatek@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org Subject: [PATCH 4/4] arm64: dts: mt8173: Fix mmsys node name Date: Tue, 31 Mar 2020 23:46:09 +0200 Message-Id: <20200331214609.1742152-4-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200331214609.1742152-1-enric.balletbo@collabora.com> References: <20200331214609.1742152-1-enric.balletbo@collabora.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Node names are supposed to match the class of the device, mmsys is a system controller (syscon) not a clock controller, so change the node name accordingly. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chun-Kuang Hu --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 8b4e806d5119..a55e8c177832 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -908,7 +908,7 @@ u2port1: usb-phy@11291000 { }; }; - mmsys: clock-controller@14000000 { + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;