From patchwork Thu Apr 2 12:11:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26BF6159A for ; Thu, 2 Apr 2020 12:12:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEABA20757 for ; Thu, 2 Apr 2020 12:12:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TQxW9jZa" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388233AbgDBMMB (ORCPT ); Thu, 2 Apr 2020 08:12:01 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:43767 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387937AbgDBMMA (ORCPT ); Thu, 2 Apr 2020 08:12:00 -0400 Received: by mail-ed1-f66.google.com with SMTP id bd14so3768705edb.10; Thu, 02 Apr 2020 05:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LRlrYBCdZcwWb03ZprO8ychzrcB476+VJ1UlnxZ2m10=; b=TQxW9jZaa+wrh9KjiHx179fg9oGdn4GxO+8hkR7A5O77/1lguXBzDIGKMy2QtZFkr7 oPsNGTDlqbNES1TGkDjhOVgRXTxopGu9LKpnf+3RnC3rrwOlb6ChrPWTNp6cDki1FeiY LYXx/FZVbN9HsGCHnnPpDIMhFKOoj5qzOacyz6F49Dv5CJRFouSScdHY0zNRWCOfYIFu xh4ipTGayZpAlquTuTUEZymfHHrP6twIFegpkwQgv9OcUgJ5stH1/ofDicEy5Kvjm/Sg VSQIt9Zonjv05IcBKJbEakrXUolg7LkXdCBa07ACnKczupACaKTJ9lriXeUtnf8nk1kY itQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LRlrYBCdZcwWb03ZprO8ychzrcB476+VJ1UlnxZ2m10=; b=r6QmcMUFEPaNtZovlDf3YGfR5t9S1VwJmSFcQXTDuSTec0H3Hd37HnnalHw/pXcFXd ryuPtpG9KUSLBLE8yiNrjPqXt0K0A2vrQ8IMFXTWRedK3CO0uj8ls7hiR+RLg/qeAAMR pQm2OeMBxIv1h7+J0PMlk8Bvc35+szeRyTPOmHztW/cDgmN4X1f33+QST+pna7gaZdZ1 VBkopgJygZnLBMoOSkrbaAgIrfMA8JTfAYg6C3UiUd2dfqO8IisqWbEau5MGKOvS9yEj KsMPaAEwT/jjWORESYPYNdXfLch36CnAxyhWIBK5IuNmBkH594E0HPkNgAsX3p4nmsxN uDqQ== X-Gm-Message-State: AGi0PuYAEGDUCla0JOmRgQqTcBAtNbObOr0rr9Vizdrd5B+w/WYucY5h tJVqmra4gdq9fsB7eDno2CE= X-Google-Smtp-Source: APiQypIVPsuxwUmgrlYcT74yZAWLYg4LgP32sTqKUWFQ5nLWkPN8O2DDt3wLLO2I85DElok5l5lFIw== X-Received: by 2002:a50:e007:: with SMTP id e7mr2532354edl.361.1585829518018; Thu, 02 Apr 2020 05:11:58 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:11:57 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Sham Muthayyan , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver Date: Thu, 2 Apr 2020 14:11:38 +0200 Message-Id: <20200402121148.1767-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Aux and Ref clk are missing in pcie qcom driver. Add support in the driver to fix pcie inizialization in ipq806x. Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..f958c535de6e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Thu Apr 2 12:11:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470625 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E048B14B4 for ; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:11:59 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Rob Herring , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom,pcie Date: Thu, 2 Apr 2020 14:11:39 +0200 Message-Id: <20200402121148.1767-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document missing clks used in ipq806x soc. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Thu Apr 2 12:11:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470619 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E06714B4 for ; Thu, 2 Apr 2020 12:12:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7BC752078B for ; Thu, 2 Apr 2020 12:12:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DbAA1ASm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388260AbgDBMMF (ORCPT ); Thu, 2 Apr 2020 08:12:05 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:33995 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387937AbgDBMMF (ORCPT ); Thu, 2 Apr 2020 08:12:05 -0400 Received: by mail-ed1-f67.google.com with SMTP id o1so3841884edv.1; Thu, 02 Apr 2020 05:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KsFq7yQU1rlzNMJrGzP0f6VuMClLu/ToR/AF+zEb8qI=; b=DbAA1ASmX06fN4fhcKuLmpG395IJaD5OzO2OkAiIl3DUn6qMG8A4hu6nPEdiRCy7qS LUAx5RFECtsHPfmAvq/jS+h69W4IoCvCC39zMgpLoonFBTN9bkgKuV046V8nKC5a3pp1 GbpFsy/t/M/WH9bVudqmABrVTR3ubeyKcGUC81SUv9egWRY4uAe9km7lOzqbw9M9FkeB tv0Ejc/l0+FeXM5Tf1OaLrcBIUNWxN2+GTojdYe+/yfD+uWbkr/370kF9IgxgbIw+Dob gofwLkhJV9J8fxs72AqfRyaHTut5OimKD6Gumrr+d+on8LtR1JrT5I65/iuHfxKu1NTm I19g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KsFq7yQU1rlzNMJrGzP0f6VuMClLu/ToR/AF+zEb8qI=; b=aHPB3/uWoLz31tJTNgiXAowuPspiS1FmkwnG3b4rhGlMsdrPvmq852k4wXPu5iNYE3 eMT/UBOhqB1Di4ndm5mSvd8fLYXYsfZ5I3UtI4qEIfZCaJu0KDPkej7p1BgBewmNr3IB Ngl01m4a5bnGiKPiDyLDxm7sowu6mwJ7KOhGqZ5+yD1CmVIVisIL6fiEs6lqaFUuGmha mmPrGZDREyFzIv4xbWUOdepRVXbR8Wmc0nlxnu9JNYFg/sFhL/PuzcJ6qedUjGO6PJ53 SgR7E2RfP9N3UpRIU8eb/J5RFsowKxhe4rCN/LlUrsjKUDT0IjKeSNXIROAGkkzcfZJx mR0g== X-Gm-Message-State: AGi0PuaI7GGoMY3eaLt1weaJDuARSTUYoOGItkFZIwkv2DW/AkGWgumq +DSo5BpzQh9Ss7/xabGn4j2EeSgMZxUyCTz7 X-Google-Smtp-Source: APiQypIvBMbr8/OcVfmbOg/N7gt60xcGNaW9v5EquvvNuFHwtAY2cx8E5B83GtZqK9UIvLjtxRP+eA== X-Received: by 2002:aa7:d91a:: with SMTP id a26mr2622190edr.236.1585829522548; Thu, 02 Apr 2020 05:12:02 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:02 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Abhishek Sahu , Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/10] PCIe: qcom: change duplicate PCI reset to phy reset Date: Thu, 2 Apr 2020 14:11:40 +0200 Message-Id: <20200402121148.1767-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for pci twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f958c535de6e..1fcc7fed8443 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -284,7 +284,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); From patchwork Thu Apr 2 12:11:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470617 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2AEC159A for ; Thu, 2 Apr 2020 12:12:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B07A7206F6 for ; Thu, 2 Apr 2020 12:12:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RgRQbPEz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388279AbgDBMMI (ORCPT ); Thu, 2 Apr 2020 08:12:08 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:41582 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388270AbgDBMMH (ORCPT ); Thu, 2 Apr 2020 08:12:07 -0400 Received: by mail-ed1-f68.google.com with SMTP id v1so3778621edq.8; Thu, 02 Apr 2020 05:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=RgRQbPEzT5t5qyUie+NZNDm7W//5r0zMUaVjO0vTHJXLn1Jq+AFFTQ8NF6cuRQg3+r jw/UZ0DJckiTbrsc2w+LRw9hB6+7eL355HC2PuA/h9kNI0v/BB7GMtLZFI2h2ggYUkzO 2kWywja4BJWC6XJrGLixUBQ3ljfSuaSCOndwZ2/U0e7YWUQaq8COd31WDAGmAdJ/94yh yPe70XqwKy2yEEQjQyKtkqApsUALuBjY6nHOPvhtvtaWRIVWjeRoSSxZQDNQ7g4CPmMb xx/RPHnWVJ8675BRNXgFsSccucnSRJBTzypSeCXH6FRq5vzNuJuKye5C6I5dMdtdtYeK 3k9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QTJvUrUZh6Asz0TpkI0T8aoHyYL8TgG05bomTjzSOyM=; b=uc3AlM4XzV/n30xVL7NjtLsyGSQTIW8McC753TdFZ6U4S0f/SaygdwI0d0ab6EVwyl hWrhJGD+r4ExHc+xUlSeojeIRPXvylx0HG/5id9KqDJ21q69/e5L67x/WJr4OTsQl+Tg iCh+MZG5rmSbMXg5ysq+i032jtXRwohGQ1lZTHgEXj4uq+LFonAcuULep4xO6jOXDirw /76HgHgSE9POuKB4fmmYBUOAMfdTepUHt/QS8uVhvEOwBbskQBbQ26UZ7EEHcPjLh38Q GanjOsLeBALiV9a29U7CX+bSMskg/zZHc2Zrr6TB7XqooPv6HfkON5PlCuzjYKI+kXlV tUYQ== X-Gm-Message-State: AGi0PuZXCAisRoNnXecsqQjTsM2A1hE9t8YuKoPL+2CC0gAW/Vejt4Ok shWmWKwm3RC+xrx7pEU95Uo= X-Google-Smtp-Source: APiQypIapMX5g/RNGOzYfHeGKlNQ8T/bL6HvSioskJYSxgPjXIMKz7gAV5jsSa4/pYer1Ua7q64ybQ== X-Received: by 2002:a05:6402:705:: with SMTP id w5mr2585708edx.288.1585829524941; Thu, 02 Apr 2020 05:12:04 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:04 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Abhishek Sahu , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue Date: Thu, 2 Apr 2020 14:11:41 +0200 Message-Id: <20200402121148.1767-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Following backtraces are observed in PCIe deinit operation. Hardware name: Qualcomm (Flattened Device Tree) (unwind_backtrace) from [] (show_stack+0x10/0x14) (show_stack) from [] (dump_stack+0x84/0x98) (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8) (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40) (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120) (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4) (clk_core_disable) from [] (clk_disable+0x24/0x30) (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8) (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8) (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538) (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4) pcie_phy_clk is generated for PCIe controller itself and the GCC controls its branch operation. This error is coming since the assert operations turn off the parent clock before branch clock. Now this patch moves clk_disable_unprepare before assert operations. Similarly, during probe function, the clock branch operation should be done after dessert operation. Currently, it does not generate any error since bootloader enables the pcie_phy_clk but the same error is coming during probe, if bootloader disables pcie_phy_clk. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 1fcc7fed8443..596731b54728 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); @@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Thu Apr 2 12:11:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A8D415AB for ; Thu, 2 Apr 2020 12:12:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 18AC321835 for ; Thu, 2 Apr 2020 12:12:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="vGv46Fzw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388302AbgDBMML (ORCPT ); Thu, 2 Apr 2020 08:12:11 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:33325 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387937AbgDBMMJ (ORCPT ); Thu, 2 Apr 2020 08:12:09 -0400 Received: by mail-ed1-f66.google.com with SMTP id z65so3841800ede.0; Thu, 02 Apr 2020 05:12:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jDYxV67s8P5RgobB2MSQS+2SI1Pzl0kBmeEF5B8gAR8=; b=vGv46FzwXEGLJw8mRO55Ylg5m9OIyZAnDw1z2dVQ8iKg/h31tQKamcQhTbMH5hhCU2 e78cgHcWuqWUwuWJS3VuOckj37vERlfSxdqn/AOL/lTFF+upUy641boO2llgVNrXCZ5O ApAoo2uXz+HKIME05jcICx4GbUPI8kanLPteAU3sG0l0lIgY6lbWzV9Xk4XWTIfkMIt4 kG0O5qet6Wgq4yKSwvaIUmg0L29BhrQGfekYVKk2rnkpX3Le1FWa50L7Vk9sDyielU16 EcT31ajnaiHq05plJIVRMFTANdIzFwmbZTAHFAKSUxMWhVtLDR/E7DnkBW+98w9eTZu2 KVWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jDYxV67s8P5RgobB2MSQS+2SI1Pzl0kBmeEF5B8gAR8=; b=PE37ke8ZVURBoxSDxMAo6zXrKAImeUaYXHRlioX03GLX7jBEKufy+6cjS3ExY1asIp qMpEHKXSIK+v5knjf9NC35SV3BgvM1qF1eQ+lA2rp9eXFL3typDCPfhhBh3OvCLoMsme MZT+PzA/uE8smE8g5DN47gkgzMANPl0f8xypalSXq3FSbeInFvKaiFcBWx1Gs5kAdU8B aOE6XSAqj50UGj3czUzYrB3sJzk1AmcLrqdL9/ZMcPxzl+pwMF2yunl0EA/WVziDr/be i0SNVKmUUa07C/iE6butE/2b5nh87ynrzcadgpNGSLYKkzTT1XLNGe7yJ8n9qcq4Lntf 9VQQ== X-Gm-Message-State: AGi0PuahOHLxe67Qafcu0fQ6Xz5ntHsKSYHkTrHFFXSn67mNSqbQ9Qat gs24Jzl6xPFrL8jxdwa1KlA= X-Google-Smtp-Source: APiQypJWUSMKw1fpV8OosLT3iblRQBPuFwagUnBBdYDxqBWaoTGAjxGCq5AJ2rX4sedeCqmrLf0Faw== X-Received: by 2002:a50:d987:: with SMTP id w7mr2501574edj.276.1585829527306; Thu, 02 Apr 2020 05:12:07 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:06 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Sham Muthayyan , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 05/10] PCIe: qcom: add missing reset for ipq806x Date: Thu, 2 Apr 2020 14:11:42 +0200 Message-Id: <20200402121148.1767-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing ext reset used by ipq806x SoC in PCIe qcom driver. Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 596731b54728..211a1aa7d0f1 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot assert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Thu Apr 2 12:11:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E469A15AB for ; Thu, 2 Apr 2020 12:12:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C1EA02080C for ; Thu, 2 Apr 2020 12:12:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FZBpLA0h" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387937AbgDBMMM (ORCPT ); Thu, 2 Apr 2020 08:12:12 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:40590 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388270AbgDBMML (ORCPT ); Thu, 2 Apr 2020 08:12:11 -0400 Received: by mail-ed1-f66.google.com with SMTP id w26so3792517edu.7; Thu, 02 Apr 2020 05:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vd/7p4psEqL2YZP7WmH2AZNx5b6REDy2Ojzsc3JW1kE=; b=FZBpLA0hmzAKapT1JIktWT7j8Y3qsqYiFmbhovbsq2vyB8+043GUlaMPNT7HkDy4f8 2sEqIiyeMkE9xDQd6UXO5ovpzZfOTri9/cMh4iuoCsqY1WVc7P0fQcwljHHJtkC7bCFO ey+IWTyAZhPrCFL/LuiH9aoxMXI+Z6TaUt9r/VghZP0z832+Dvg8Yb2mG/bYbaw2PRYP XEGhekc2Y7wVUKHTi9w76sb78nn3WbA6AW5OaXG5F0yWzDl5ez9FkLTg3vk/W/B8VSge PQum1kZ5taobwiMoHy4Pkvc8k9CE2xcgLwrjTniz88XQdTFn5XWhSRcVwIWxYDVR8uOt /CBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vd/7p4psEqL2YZP7WmH2AZNx5b6REDy2Ojzsc3JW1kE=; b=OHfueIDubw0oC36v4j9iM6qY0iC3hRbaXEy2qXJJDtCO5jXKxWCgSvTAyrpoPynbV4 uDX34H9u2ZO7FRz4ACUtlpZOVMzAtixKZpNvMEry9809m23ofcdgu8hU0C3tB3OBGeMH vco/bwmb6GWTG2OkEio05ZWCzq187RF5lULKZLrwnWQ+GvqOB2aNWegBQLIkDSSw4apz O/wFJrFimFA6/6HQ4XfE3iVC/XB8psSzK9WPi3kwlsyKgUxogN2TswgErE303rE7bmdj +WkKbqBk9SJRYTUHU1Imgk0iMRv7ixKyy2XT5mMh0BkhRLq7XsZ1C7Kzrv7gDmvfFMP/ 78gA== X-Gm-Message-State: AGi0PuZLLe/4vlhKr+hLYdErwihoLGkFkgRZvItuWrv6wuEOdQvFXE69 ENQvVZxSBn7LhVZcEagk84o= X-Google-Smtp-Source: APiQypJWnJ2q62yiU2KO5ZU6Luhejv2WdT8MZLMdKktQicVY32+VFVKljTVTVeAsE/JmaXnKzGORaQ== X-Received: by 2002:a17:906:1e4a:: with SMTP id i10mr2801762ejj.169.1585829529575; Thu, 02 Apr 2020 05:12:09 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:09 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Rob Herring , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom,pcie Date: Thu, 2 Apr 2020 14:11:43 +0200 Message-Id: <20200402121148.1767-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document ext reset used in ipq806x soc by qcom pcie driver Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Thu Apr 2 12:11:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9F26714B4 for ; Thu, 2 Apr 2020 12:12:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 735582078B for ; Thu, 2 Apr 2020 12:12:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="O7yp4kXD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388332AbgDBMMO (ORCPT ); Thu, 2 Apr 2020 08:12:14 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:35342 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388318AbgDBMMO (ORCPT ); Thu, 2 Apr 2020 08:12:14 -0400 Received: by mail-ed1-f65.google.com with SMTP id a20so3823099edj.2; Thu, 02 Apr 2020 05:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=siYXJ0KfUOVO29qQPm4eyONLoVr/YpaUx1vSJEqMS2g=; b=O7yp4kXD1dc2cH7QAbryxdYwYQPDMgjZn8y06TzsMomTXOGLloWUdF0AH9tkY+fpGZ 2h6QbrctZurRQI2Qil1UeMNRpImEyIE0yZLA5usWcZz6XfqmnvoF9Uz00XLBUcQ1boxC 4RDIiNvx6TOICGasmCWQCce4dckB/WlULHsb8JA2ehg+g+4zL7YgF2Ns9VaJl5TaS1oO gePFaWScSwuhaEpJFqte+MzptMpYxvRlgkaVrzENrP8Ivihk3ZxbNDXP22tI4vjXlxvx kTinewkrlfizHQfaoY6GGb/n6ioI5mDd5ubH+CgV7BcgIBxDnN+m3qDk7sDScpdAxmvl eEYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=siYXJ0KfUOVO29qQPm4eyONLoVr/YpaUx1vSJEqMS2g=; b=URFOqU488NcS3oIMUnnFCnsZD92sT+MWdIBU+oyTLHLrZnXPrNOraaMFnFxi5cjDlw wDC/+cjFnHVp9QCsXANy5cuZROXGZPXXTdoIQM9bKQ3E0xvYvGVPa4n/TRvMjcwdnz2X uoXy+BLwh038vGBX30ddR1D7W8i0TV+6ob/hctzvR3RzIayjLaR1fgl0KUBc5OEnsQGQ sFfX+6hxgsLiiZsE+WKtVl07bMix84ETFOdENDp0ZR4Qfwg4W6/0N0oIQgIaEltm8O9/ 1/A+3EbHhslcD7bwkTWblXH1p2wCpVgJ/Ie+oHx6nUa3Fz+16IAK1FJz0GnHGxhXR459 YF3A== X-Gm-Message-State: AGi0PubHbn2vCb4VvELeD7bOffSu3aVKF74w+rSrZpK9o2UdMRsw7owS JYOpjUwwEcfqC8K4JmPGDqk= X-Google-Smtp-Source: APiQypLl21LPxvZAZ1mpYDoTheGcJsI0a0ylEMWBlnokwvYvhkS7RNpTe49pyiEln83KUEnLseNHjQ== X-Received: by 2002:a05:6402:13c8:: with SMTP id a8mr2664671edx.245.1585829531667; Thu, 02 Apr 2020 05:12:11 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:11 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming Date: Thu, 2 Apr 2020 14:11:44 +0200 Message-Id: <20200402121148.1767-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PARF programming was missing and this cause initilizzation problem on some ipq806x based device (Netgear R7800 for example). This cause a total lock of the system on kernel load. Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++----- 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 211a1aa7d0f1..77b1ab7e23a3 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -46,6 +46,9 @@ #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C +#define REF_SSP_EN BIT(16) +#define REF_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -77,6 +80,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) (x << 8) +#define PCS_SWING_TX_SWING_LOW(x) (x << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) (x << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -184,6 +199,16 @@ struct qcom_pcie { #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) +static inline void qcom_clear_and_set_dword(void __iomem *addr, + u32 clear_mask, u32 set_mask) +{ + u32 val = readl(addr); + + val &= ~clear_mask; + val |= set_mask; + writel(val, addr); +} + static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { gpiod_set_value_cansleep(pcie->reset, 1); @@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - u32 val; int ret; ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); @@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + + /* PARF programming */ + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(0x78) | + PCS_SWING_TX_SWING_LOW(0x78), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS); - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + /* enable reference clock */ + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK, + REF_USE_PAD, REF_SSP_EN); ret = reset_control_deassert(res->phy_reset); if (ret) { From patchwork Thu Apr 2 12:11:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9441514B4 for ; Thu, 2 Apr 2020 12:12:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72E462078C for ; Thu, 2 Apr 2020 12:12:31 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:13 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Sham Muthayyan , Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 08/10] PCIe: qcom: add ipq8064 rev2 variant and set tx term offset Date: Thu, 2 Apr 2020 14:11:45 +0200 Message-Id: <20200402121148.1767-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 have tx term offset set to 7. Ipq8064 v2 revision and ipq8065 have the tx term offset set to 0. Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77b1ab7e23a3..8047ac7dc8c7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,6 +45,9 @@ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 #define PCIE20_PARF_PHY_CTRL 0x40 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(12, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16) + #define PCIE20_PARF_PHY_REFCLK 0x4C #define REF_SSP_EN BIT(16) #define REF_USE_PAD BIT(12) @@ -112,6 +115,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *phy_reset; struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + uint8_t phy_tx0_term_offset; }; struct qcom_pcie_resources_1_0_0 { @@ -302,6 +306,11 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->ext_reset)) return PTR_ERR(res->ext_reset); + if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064")) + res->phy_tx0_term_offset = 7; + else + res->phy_tx0_term_offset = 0; + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -381,6 +390,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0); + /* set TX termination offset */ + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset)); + /* PARF programming */ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) | @@ -1494,6 +1508,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, From patchwork Thu Apr 2 12:11:46 2020 Content-Type: text/plain; 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[95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:16 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie Date: Thu, 2 Apr 2020 14:11:46 +0200 Message-Id: <20200402121148.1767-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset. In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's set to 0 by default. Signed-off-by: Ansuel Smith --- .../devicetree/bindings/pci/qcom,pcie.txt | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..b699f126ea29 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -5,6 +5,7 @@ Value type: Definition: Value should contain - "qcom,pcie-ipq8064" for ipq8064 + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096 @@ -295,6 +296,47 @@ pinctrl-names = "default"; }; +* Example for ipq8064 rev 2 or ipq8065 + pcie@1b500000 { + compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie"; + reg = <0x1b500000 0x1000 + 0x1b502000 0x80 + 0x1b600000 0x100 + 0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ + 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + pinctrl-0 = <&pcie_pins_default>; + pinctrl-names = "default"; + }; + * Example for apq8084 pcie0@fc520000 { compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; From patchwork Thu Apr 2 12:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11470603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 23F7A15AB for ; Thu, 2 Apr 2020 12:12:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 023EB21473 for ; Thu, 2 Apr 2020 12:12:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="uVKjtr9Z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388366AbgDBMMW (ORCPT ); Thu, 2 Apr 2020 08:12:22 -0400 Received: from mail-ed1-f65.google.com ([209.85.208.65]:46489 "EHLO mail-ed1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388344AbgDBMMW (ORCPT ); Thu, 2 Apr 2020 08:12:22 -0400 Received: by mail-ed1-f65.google.com with SMTP id cf14so3744598edb.13; Thu, 02 Apr 2020 05:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jpfK5CYxI8iAPFcZqyQcL5PaZpDr+KrVab+ErVI0E9A=; b=uVKjtr9Z2nepMqEDTiTNNduDfcQJhvvNnmcyS8yfwHjpDvWzEIMZz0lRCYqqz8EoQh MSmE0pl+mSAZNhfA9/7nz32tzqB3NOdIlvpeqtbwPGqFbk4pX1MyiMo2zFL2v/H6dEFB cPJyWiU3Wqu6OFboT+zFQj3b/26oTBr5026kW601iqMQh1wuc+LdDb4xenB5wHhgXOBx cTPErLGCyz6VGn/uTIOlXVvAV/0JR2N7jNnl0wr8rWJsIBGMEJ+JNhFNVLNOOwvjx5jb 0Pp2KFAlPvZs1D+EWdph5/O5Jx661nzq3sKTvehAq6nOvmqh2Ua936zmS58Ku64XQvn8 Hf/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jpfK5CYxI8iAPFcZqyQcL5PaZpDr+KrVab+ErVI0E9A=; b=W2pew44VtueUFF6FzjeByfHzvx70hu2Ciz56ckwzgwZfzLQhUItyhAN9dTO5ZunpBK yKYg0Oki1iqF7fYhibbcYbluCKqlsDPeSgULrY40UGr02NkTxbKwsdvlcvlYcVeyfcs4 95dIEZXe/xka65jwVCuTTII1b0ziFfolEXH2wbVANSA3t0RlZN1JTZAA/KRnzGAWgpy2 WPf8i/4j6RksMYaC0Dupvyjvx1oym4+6rdVIOBOtvqxvAVSeegSN8ue4IdieQiUfxV1P NJU24yPhr/tutWA/bOI065dSBXAIdv/CkQCiSSEofLqIFF+KRZ2RPts3KyroTF+YwV0N 77iA== X-Gm-Message-State: AGi0PuZUS4A+cXrQ/oMtV/zRPZgaAfcQsFall4oberEZCgOygEXU+bHZ Gb4nHaoCsQDb4SwBqVWoUaU= X-Google-Smtp-Source: APiQypIPnU/+DrVqHsBOAMuaMwGL5dXkm117kJM04jvdu64bzzV0k35KALXEyjji5Vk3p5vPMd/48A== X-Received: by 2002:a17:907:aab:: with SMTP id bz11mr2764943ejc.311.1585829540059; Thu, 02 Apr 2020 05:12:20 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host250-251-dynamic.250-95-r.retail.telecomitalia.it. [95.250.251.250]) by smtp.googlemail.com with ESMTPSA id w20sm1083611ejv.40.2020.04.02.05.12.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 05:12:18 -0700 (PDT) From: Ansuel Smith To: Andy Gross Cc: Sham Muthayyan , Ansuel Smith , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support Date: Thu, 2 Apr 2020 14:11:47 +0200 Message-Id: <20200402121148.1767-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com> References: <20200402121148.1767-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sham Muthayyan Add Force GEN1 support needed in some ipq806x board that needs to limit some pcie line to gen1 for some hardware limitation. This is set by the max-link-speed dts entry and needed by some soc based on ipq806x. (for example Netgear R7800 router) Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8047ac7dc8c7..2212e9498b91 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -199,6 +202,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + bool force_gen1; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->force_gen1) { + writel_relaxed((readl_relaxed( + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1), + pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ @@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + ret = of_pci_get_max_link_speed(pdev->dev.of_node); + if (ret == 1) + pcie->force_gen1 = true; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) {