From patchwork Wed Apr 8 13:09:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480089 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8C45081 for ; Wed, 8 Apr 2020 13:11:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C72C20787 for ; Wed, 8 Apr 2020 13:11:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aFWPOjD+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728401AbgDHNLK (ORCPT ); Wed, 8 Apr 2020 09:11:10 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:39793 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729069AbgDHNKv (ORCPT ); Wed, 8 Apr 2020 09:10:51 -0400 Received: by mail-wm1-f65.google.com with SMTP id y24so1316319wma.4 for ; Wed, 08 Apr 2020 06:10:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NlDlRv555GH3IWzPThM2PIkVo5dnbd1J1aXXNjhdRgU=; b=aFWPOjD+POZxqE+i+gRicc1Ttn6UlDSIUKWVEXYrw6mfX2v20gZgt82l4KRhjiIe9A b7eh6/OF5TAIN8zLoLVxFZu6TXaYtFE7/efNaS8sZKDyPnHEaYTT/n35OdxMY05APuOt rlWYwUne8HTx4HnFmTSaPsuQsXqpfgebNO4ZoJARRorQ9DkoYG3cYPagjmaYqCRxy/5p rnFMxw1K+6Rzmgrq1DW3Fnq4at0dmmS01p0cbFLJdKNnxjXp8BkfZrycWl7oUXu+s+cK d/adjUK3FZcpZfWktEdbNJoad3EocqLejBbg1sRQ265bF0LqSaopWWshBlwmpvodh1TX BEag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NlDlRv555GH3IWzPThM2PIkVo5dnbd1J1aXXNjhdRgU=; b=dGSRgOg0qS+6ih3s2kOwbvMU5AHWyu37qOtJ9l09GJgPgaqmpUDq8oM/27UWKhaD1j Ts3hoUga3nMTwgNWz9j7ta1ctsdy6jWLeO9+0i8P68lxKVGFmFhM8j1OGCX6SMYEowh+ AOrBh5E060WFzitPkh9cn1quhcgK+TN/6ZrZqxOSEUZYoolloufBRNNNDyxXvLne+BFK P4DPuu01nNgjK+zVD2BVf7kaP7YMo0jSaPG2WCO0IE5oaZ3QBy/YTHdR/08jb6fySWLy kop6KnVgvPRyTQa/Q6KmGeIpvW3grVeBQXEIl2UL9xPiYe6QvT+G+HA/n4CVr+hNatoZ qxOA== X-Gm-Message-State: AGi0Puayp1B5SWxH9rvyGzzApGPYggWNDvNL9IaGjQNvxx3EYfRp90F2 twvmeigY6puR4DIs96YCLu0/vw== X-Google-Smtp-Source: APiQypKFGiJ+gX60BLbUE1LDlC51Duk6XfC5j/frP0y9C+JdDx5KsdFSZwr18YptOjMFQlBlrJHuCg== X-Received: by 2002:a7b:c1da:: with SMTP id a26mr3107514wmj.125.1586351446839; Wed, 08 Apr 2020 06:10:46 -0700 (PDT) Received: from localhost.localdomain ([37.120.50.78]) by smtp.gmail.com with ESMTPSA id f4sm18428044wrp.80.2020.04.08.06.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2020 06:10:46 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 1/6] arm64: dts: msm8916: Add i2c-qcom-cci node Date: Wed, 8 Apr 2020 15:09:54 +0200 Message-Id: <20200408130959.2717409-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Loic Poulain The msm8916 CCI controller provides one CCI/I2C bus. Signed-off-by: Loic Poulain Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v1: - Add label to cci node - Sort cci node by address - Relabel cci0 i2c bus to cci-i2c0 arch/arm64/boot/dts/qcom/msm8916.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index a88a15f2352b..cad0ac482367 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1603,6 +1603,33 @@ ports { }; }; + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + smd { compatible = "qcom,smd"; From patchwork Wed Apr 8 13:09:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480087 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06AF51744 for ; Wed, 8 Apr 2020 13:11:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D8B6F20787 for ; Wed, 8 Apr 2020 13:11:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="m0gdP+gW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729070AbgDHNKu (ORCPT ); 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Wed, 08 Apr 2020 06:10:47 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 2/6] arm64: dts: apq8016-sbc: Add CCI/Sensor nodes Date: Wed, 8 Apr 2020 15:09:55 +0200 Message-Id: <20200408130959.2717409-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Loic Poulain Add cci device to msm8916.dtsi. Add default 96boards camera node for db410c (apq8016-sbc). Signed-off-by: Loic Poulain Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v1: - Reference CCI by label - Don't use generic node names - Move regulator nodes out of /soc - Use CCI label and move node out of /soc - Use reference for camss and move node out of /soc - Use reference for cci-i2c0 and move out of /cci - Disable camera_read by default, since no mezzanine board is guaranteed arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 76 +++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 06aab44d798c..14982762088d 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -51,6 +51,30 @@ chosen { stdout-path = "serial0"; }; + camera_vdddo_1v8: camera_vdddo_1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera_vdda_2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera_vddd_1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + reserved-memory { ramoops@bff00000{ compatible = "ramoops"; @@ -538,6 +562,58 @@ button@0 { }; }; +&camss { + status = "ok"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + status = "okay"; + }; + }; + }; +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + clock-frequency = <23880000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + /* No camera mezzanine by default */ + status = "disabled"; + + port { + ov5640_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + &spmi_bus { pm8916_0: pm8916@0 { pon@800 { From patchwork Wed Apr 8 13:09:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480075 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97EE081 for ; Wed, 8 Apr 2020 13:10:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6E08C20A8B for ; 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Wed, 08 Apr 2020 06:10:49 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 3/6] arm64: dts: sdm845: Add i2c-qcom-cci node Date: Wed, 8 Apr 2020 15:09:56 +0200 Message-Id: <20200408130959.2717409-4-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The sdm845 SOC ships with a CCI controller, which has two CCI/I2C buses. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v1: - Pad addresses to 8 bytes - Sort clock_camcc by address - Change cciX pinctrl node names - Remove pinmux/pinconf nodes from pinctrl nodes - Remove clk suffix from CCI node clock-names - Give CCI i2c-bus nodes labels arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 + arch/arm64/boot/dts/qcom/sdm845.dtsi | 92 ++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index a2e05926b429..8644a2f6095a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -866,3 +866,7 @@ pinconf-rx { bias-pull-up; }; }; + +&cci { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 8f926b5234d4..f3eb1dc11ac6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -1813,6 +1814,42 @@ tlmm: pinctrl@3400000 { gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0-default { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -3194,6 +3231,61 @@ videocc: clock-controller@ab00000 { #reset-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Wed Apr 8 13:09:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480085 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9E7D892A for ; Wed, 8 Apr 2020 13:11:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7E49920757 for ; Wed, 8 Apr 2020 13:11:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YR7kjZED" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729085AbgDHNLG (ORCPT ); Wed, 8 Apr 2020 09:11:06 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:52461 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729077AbgDHNKx (ORCPT ); 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Wed, 08 Apr 2020 06:10:51 -0700 (PDT) Received: from localhost.localdomain ([37.120.50.78]) by smtp.gmail.com with ESMTPSA id f4sm18428044wrp.80.2020.04.08.06.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2020 06:10:51 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 4/6] arm64: dts: sdm845-db845c: Add pm_8998 gpio names Date: Wed, 8 Apr 2020 15:09:57 +0200 Message-Id: <20200408130959.2717409-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add pm_8998 GPIO trace names. These names are defined in the 96boards db845c mezzanine schematic. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v1: - Move gpio-names to previous reference to pm8998_gpio label arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 8644a2f6095a..5cd06ab97b9a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -412,6 +412,34 @@ &pcie1_phy { }; &pm8998_gpio { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; From patchwork Wed Apr 8 13:09:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480083 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 416B381 for ; Wed, 8 Apr 2020 13:11:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 164082082F for ; Wed, 8 Apr 2020 13:11:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="F/eqBDnW" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729090AbgDHNK4 (ORCPT ); Wed, 8 Apr 2020 09:10:56 -0400 Received: from mail-wm1-f66.google.com ([209.85.128.66]:39814 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729081AbgDHNKz (ORCPT ); Wed, 8 Apr 2020 09:10:55 -0400 Received: by mail-wm1-f66.google.com with SMTP id y24so1316751wma.4 for ; Wed, 08 Apr 2020 06:10:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qat0qCK/sNaiO1XJkN821ruUc56J0U4eHBjYp57aVnw=; b=F/eqBDnWMTYkcbEmw5D4RotdyaUnJw6T+Vd/EspDeSxIOgoVLnh21s2NwIMjFxhr7h LdCXgZSQ7bgGw9e5ycracYGqAkeQsl5pU704RTWtpx0TD5V6/Dtt7pqLMl7lvRl7ytHH AkC7hWvICTg6DppD/PlFZZYHs23nEumJeVWFh69XRf4XXfiDtimVDpp0qYfzX194suoa fgdYu8P8n0dfV0c0u4O/0+E6aM5FJJnx8/f3QD/Pb1xymQmt3HFLT5+7S34K3/5Ty7j4 0R2X6ZENpKgdaSa9v35sJtywCfGjiLW1U4A3wKAogDv26DLzH1sDFnRPFPedlgdtS/jr R2Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qat0qCK/sNaiO1XJkN821ruUc56J0U4eHBjYp57aVnw=; b=c0oY8iqmYfATM7OcJIgAPSzxpa/SmrnUSuBeIK6mOtgXZ30/nbouZmdmr2y8AgOdjs 1mpLZAqZogq6rRY8B4WmUCI6sgHdA7e1WX+moXunkH3dhrcuyGpBRuIPqF/MVcXa1IGL 2p5+cXDDA325CSut8vwO8HHdi/N6Ui8VjDds5ro5s6sRQYz9fl2AXQck+VmbMNwi8Mjy ZohqDT3a2P0e5sf/zhBpn9/Wqai2Ds6K9MnC09bKHDgSnM5Jot19aCqJ468/yEKxuAef Wx9SIEk5LF7uxA2xESWBf2z/DTv5t62PeDtErD4NcBBsd2AJo58b/wrSTnCZVzZMmyDz RadQ== X-Gm-Message-State: AGi0PubLwip+mKMHbgEADnmMUKnFTmgl1QruDyCE9f6lwpw54ThME0jj R4y70r5T9w7wM6kUG3/lH1VqrA== X-Google-Smtp-Source: APiQypKjFYEX56XqML9jD0XcsKjVK1yhwdPHvBwzV4QZNzPFcvqo6v98XM7r+hZNdeftaqTcEaeieg== X-Received: by 2002:a7b:c1da:: with SMTP id a26mr3107901wmj.125.1586351453039; Wed, 08 Apr 2020 06:10:53 -0700 (PDT) Received: from localhost.localdomain ([37.120.50.78]) by smtp.gmail.com with ESMTPSA id f4sm18428044wrp.80.2020.04.08.06.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2020 06:10:52 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 5/6] arm64: dts: sdm845-db845c: Add ov8856 & ov7251 camera nodes Date: Wed, 8 Apr 2020 15:09:58 +0200 Message-Id: <20200408130959.2717409-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable the ov8856 main camera and the ov7251 b/w tracking camera used on the Qualcomm RB3 kit. Currently the camera nodes have not yet been attached to an to a CSI2 endpoint, since no driver currently supports the ISP that the the SDM845/db845c ships with. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v3: - Remove GPIOS property from camera nodes - Invert ov8856 reset-gpio logic to match driver Changes since v1: - Move cam0_ pinctrls subnodes into the first pm8998_gpio reference - Remove accidentally committed &tlmn node subnodes - Remove redundant tlmm pinctrl subnodes - Fix pinctrl subnode identation - Remove accidentally committed &tlmn node subnodes - Replace underscores in node names - Reference cci i2c buses by labe - Change camera node names from camX@YY to camera@YY - Remove camera@10 comment about I2C addresses - Replace GPIO_ACTIVE_HIGH with 0 in camera nodes - Removed extra newline - Remove comment about not being available always - Disable cameras as CSI driver is missing - Fix factual error in comment about vreg_s4a_1p8 - Remove dummy regulator cam3_vddd_1v2 arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 172 +++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 5cd06ab97b9a..87921a8ccf5f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -112,6 +112,40 @@ pcie0_1p05v: pcie-0-1p05v-regulator { // enable-active-high; }; + cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: reg_cam0_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: reg_cam3_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + pcie0_3p3v_dual: vldo-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VLDO_3V3"; @@ -440,6 +474,24 @@ &pm8998_gpio { "OPTION2", "PM845_SLB"; + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; @@ -601,6 +653,42 @@ &spi2 { }; &tlmm { + cam0_default: cam0_default { + rst { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3_default { + rst { + function = "gpio"; + pins = "gpio21"; + + drive-strength = <16>; + bias-disable; + }; + + mclk3 { + function = "cam_mclk"; + pins = "gpio16"; + + drive-strength = <16>; + bias-disable; + }; + }; + pcie0_default_state: pcie0-default { clkreq { pins = "gpio36"; @@ -898,3 +986,87 @@ pinconf-rx { &cci { status = "ok"; }; + +&cci_i2c0 { + camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + // CAM0_RST_N + reset-gpios = <&tlmm 9 1>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + assigned-clock-rates = <19200000>; + + /* The &vreg_s4a_1p8 trace is powered on as a, + * so it is represented by a fixed regulator. + * + * The 2.8V vdda-supply and 1.2V vddd-supply regulators + * both have to be enabled through the power management + * gpios. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + status = "disable"; + + port { + ov8856_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 + <360000000 180000000>; + data-lanes = <1 2 3 4>; +// remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + +&cci_i2c1 { + camera@60 { + compatible = "ovti,ov7251"; + + // I2C address as per ov7251.txt linux documentation + reg = <0x60>; + + // CAM3_RST_N + enable-gpios = <&tlmm 21 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + /* The &vreg_s4a_1p8 trace always powered on. + * + * The 2.8V vdda-supply regulator is enabled when the + * vreg_s4a_1p8 trace is pulled high. + * It too is represented by a fixed regulator. + * + * No 1.2V vddd-supply regulator is used. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + + status = "disable"; + + port { + ov7251_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; +// remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; From patchwork Wed Apr 8 13:09:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 11480079 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 949E181 for ; Wed, 8 Apr 2020 13:11:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7465020BED for ; Wed, 8 Apr 2020 13:11:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="jTY7ueTT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729099AbgDHNK5 (ORCPT ); Wed, 8 Apr 2020 09:10:57 -0400 Received: from mail-wm1-f68.google.com ([209.85.128.68]:40800 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729089AbgDHNK5 (ORCPT ); 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Wed, 08 Apr 2020 06:10:54 -0700 (PDT) Received: from localhost.localdomain ([37.120.50.78]) by smtp.gmail.com with ESMTPSA id f4sm18428044wrp.80.2020.04.08.06.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Apr 2020 06:10:54 -0700 (PDT) From: Robert Foss To: agross@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org, leoyang.li@nxp.com, Anson.Huang@nxp.com, olof@lixom.net, leonard.crestez@nxp.com, geert+renesas@glider.be, marcin.juszkiewicz@linaro.org, valentin.schneider@arm.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Loic Poulain , Luca Weiss Cc: Robert Foss Subject: [PATCH v4 6/6] arm64: defconfig: Enable QCOM CAMCC, CAMSS and CCI drivers Date: Wed, 8 Apr 2020 15:09:59 +0200 Message-Id: <20200408130959.2717409-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200408130959.2717409-1-robert.foss@linaro.org> References: <20200408130959.2717409-1-robert.foss@linaro.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Build camera clock, isp and controller drivers as modules. Signed-off-by: Robert Foss Reviewed-by: Bjorn Andersson --- Changes since v2: - Removed duplicated CONFIG_SDM_CAMCC_845 defconfig arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 24e534d85045..46ee13b6df27 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -410,6 +410,7 @@ CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y +CONFIG_I2C_QCOM_CCI=m CONFIG_I2C_QCOM_GENI=m CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y @@ -582,6 +583,7 @@ CONFIG_VIDEO_RENESAS_FDP1=m CONFIG_VIDEO_RENESAS_FCP=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_RCAR_DRIF=m CONFIG_DRM=m CONFIG_DRM_I2C_NXP_TDA998X=m @@ -802,6 +804,7 @@ CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y +CONFIG_SDM_CAMCC_845=m CONFIG_SDM_GCC_845=y CONFIG_SDM_GPUCC_845=y CONFIG_SDM_DISPCC_845=y