From patchwork Thu Apr 9 18:32:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean V Kelley X-Patchwork-Id: 11482191 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8819E14B4 for ; Thu, 9 Apr 2020 18:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5882820771 for ; Thu, 9 Apr 2020 18:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726620AbgDIScJ (ORCPT ); Thu, 9 Apr 2020 14:32:09 -0400 Received: from mga11.intel.com ([192.55.52.93]:23249 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726470AbgDIScJ (ORCPT ); Thu, 9 Apr 2020 14:32:09 -0400 IronPort-SDR: 4R7KpZkjPBmuS5575keRNqW7pY1GV8ToriowaI6hkCuzEXYcHf0xwFykFdKEtCfkollU8nU8uR jxcnUoNw9/zQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2020 11:32:08 -0700 IronPort-SDR: xGqOcPAFLag/5BMo2Ata9TlMt91ccaHjs6pgcbyehDFlgD/TGE3rv0Ruk+W5D0kJUHhMqw0vfv A0IJrkFH9IoQ== X-IronPort-AV: E=Sophos;i="5.72,363,1580803200"; d="scan'208";a="398663269" Received: from rlbossma-mobl.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.212.188.199]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Apr 2020 11:32:08 -0700 From: Sean V Kelley To: mj@ucw.cz, bhelgaas@google.com Cc: linux-pci@vger.kernel.org, Sean V Kelley Subject: [Patch 1/1] lspci: Add available DVSEC details Date: Thu, 9 Apr 2020 11:32:04 -0700 Message-Id: <20200409183204.328057-2-sean.v.kelley@linux.intel.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200409183204.328057-1-sean.v.kelley@linux.intel.com> References: <20200409183204.328057-1-sean.v.kelley@linux.intel.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of current generic 'unknown' output for DVSEC, add details on Vendor ID, Rev, etc. Suggested-by: Bjorn Helgaas Signed-off-by: Sean V Kelley --- lib/header.h | 4 + ls-ecaps.c | 25 +++- tests/cap-dvsec | 340 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 368 insertions(+), 1 deletion(-) create mode 100644 tests/cap-dvsec diff --git a/lib/header.h b/lib/header.h index bfdcc80..daeddeb 100644 --- a/lib/header.h +++ b/lib/header.h @@ -1042,6 +1042,10 @@ #define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */ +/* PCIe Designated Vendor-Specific Capability */ +#define PCI_DVSEC_HEADER1 4 /* Designated Vendor-Specific Header 1 */ +#define PCI_DVSEC_HEADER2 8 /* Designated Vendor-Specific Header 2 */ + /* Access Control Services */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ diff --git a/ls-ecaps.c b/ls-ecaps.c index 0021734..937dcc4 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -634,6 +634,29 @@ cap_rclink(struct device *d, int where) } } +static void +cap_dvsec(struct device *d, int where) +{ + u32 hdr; + + printf("Designated Vendor Specific Extended Capability:\n"); + if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) + { + printf("\n"); + return; + } + + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); + printf("\t\tDVSEC Vendor ID=%04x Rev=%d Len=%03x \n", + BITS(hdr, 0, 16), + BITS(hdr, 16, 4), + BITS(hdr, 20, 12)); + + hdr = get_conf_long(d, where + PCI_DVSEC_HEADER2); + printf("\t\tDVSEC ID=%04x \n", + BITS(hdr, 0, 16)); +} + static void cap_evendor(struct device *d, int where) { @@ -924,7 +947,7 @@ show_ext_caps(struct device *d, int type) printf("Readiness Time Reporting \n"); break; case PCI_EXT_CAP_ID_DVSEC: - printf("Designated Vendor-Specific \n"); + cap_dvsec(d, where); break; case PCI_EXT_CAP_ID_VF_REBAR: printf("VF Resizable BAR \n"); diff --git a/tests/cap-dvsec b/tests/cap-dvsec new file mode 100644 index 0000000..3b3558c --- /dev/null +++ b/tests/cap-dvsec @@ -0,0 +1,340 @@ +4e:00.0 Unassigned class [ff00]: Intel Corporation Device 0d93 + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- + Capabilities: [300 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed- WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [550 v1] Multicast + McastCap: MaxGroups 64, WindowSz 1 (2 bytes) McastCtl: NumGroups 1, Enable- + McastBAR: IndexPos 0, BaseAddr 0000000000000000 + McastReceiveVec: 0000000000000000 + McastBlockAllVec: 0000000000000000 + McastBlockUntransVec: 0000000000000000 + Capabilities: [588 v1] Latency Tolerance Reporting + Max snoop latency: 0ns + Max no snoop latency: 0ns + Capabilities: [5b0 v1] Transaction Processing Hints + Extended requester support + Steering table in TPH capability structure + Capabilities: [6e0 v1] Address Translation Service (ATS) + ATSCap: Invalidate Queue Depth: 00 + ATSCtl: Enable-, Smallest Translation Unit: 00 + Capabilities: [700 v1] Resizable BAR + Capabilities: [714 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 + Capabilities: [b20 v1] Page Request Interface (PRI) + PRICtl: Enable- Reset- + PRISta: RF- UPRGI- Stopped+ + Page Request Capacity: 00000000, Page Request Allocation: 00000000 + Capabilities: [b40 v1] Process Address Space ID (PASID) + PASIDCap: Exec+ Priv+, Max PASID Width: 14 + PASIDCtl: Enable- Exec- Priv- + Capabilities: [b50 v1] Precision Time Measurement + PTMCap: Requester:- Responder:- Root:- + PTMClockGranularity: Unimplemented + PTMControl: Enabled:- RootSelected:- + PTMEffectiveGranularity: Unknown + Capabilities: [d00 v1] Vendor Specific Information: ID=0040 Rev=1 Len=04c + Capabilities: [e00 v1] Designated Vendor Specific Extended Capability: + DVSEC Vendor ID=8086 Rev=0 Len=038 + DVSEC ID=0000 + Capabilities: [e38 v1] Device Serial Number 12-34-56-78-90-00-00-00 +00: 86 80 93 0d 00 00 10 00 00 00 00 ff 00 00 80 00 +10: 00 00 10 b3 00 00 00 00 01 a4 00 00 00 00 00 00 +20: 08 00 00 b1 00 00 00 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 +40: 10 80 92 00 e1 8f 00 10 10 21 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 9f 0b 78 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 a0 84 03 00 00 00 00 00 00 00 00 00 00 00 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