From patchwork Fri Oct 5 03:01:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 10627295 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1FFD112B for ; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A27062961E for ; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 96AEF2962D; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 580D12961E for ; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B7B96E6D4; Fri, 5 Oct 2018 03:04:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id AA69A6E6D5 for ; Fri, 5 Oct 2018 03:04:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2018 20:04:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,342,1534834800"; d="scan'208";a="78632659" Received: from dk-chv.jf.intel.com ([10.54.75.52]) by orsmga007.jf.intel.com with ESMTP; 04 Oct 2018 20:04:17 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Oct 2018 20:01:29 -0700 Message-Id: <20181005030130.15972-1-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.14.1 Subject: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Reduce PSR2 "frames before selective update entry" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The hardware can start selective update following capture of a full frame in the remote frame buffer, there is no need to wait any longer. Set "Frames Before SU Entry" bitfield to the default value of 1. Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 83528647b40b..105b7ea2cd98 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -424,6 +424,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; + val |= EDP_PSR2_FRAME_BEFORE_SU(1); /* FIXME: selective update is probably totally broken because it doesn't * mesh at all with our frontbuffer tracking. And the hw alone isn't @@ -432,8 +433,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE; - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) val |= EDP_PSR2_TP2_TIME_50us; From patchwork Fri Oct 5 03:01:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 10627293 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C370184E for ; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0D7AC2961E for ; Fri, 5 Oct 2018 03:04:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 01CC32962D; Fri, 5 Oct 2018 03:04:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AA5562961E for ; Fri, 5 Oct 2018 03:04:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 208516E6D5; Fri, 5 Oct 2018 03:04:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8FD776E6D4 for ; Fri, 5 Oct 2018 03:04:17 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Oct 2018 20:04:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,342,1534834800"; d="scan'208";a="78632660" Received: from dk-chv.jf.intel.com ([10.54.75.52]) by orsmga007.jf.intel.com with ESMTP; 04 Oct 2018 20:04:17 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Thu, 4 Oct 2018 20:01:30 -0700 Message-Id: <20181005030130.15972-2-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181005030130.15972-1-dhinakaran.pandiyan@intel.com> References: <20181005030130.15972-1-dhinakaran.pandiyan@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/psr: Set Y coordinate valid for Gen10+ display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP PSR2 sinks that require Y coordinates for selective update also need the Y coordinate Valid bit in VSC SDP. Spec: eDP 1.4b VSC payload extension for PSR2 operation (Table 6-12) Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 105b7ea2cd98..92672954dfef 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -431,7 +431,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * good enough. */ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - val |= EDP_Y_COORDINATE_ENABLE; + val |= EDP_Y_COORDINATE_ENABLE | EDP_Y_COORDINATE_VALID; if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)