From patchwork Wed Apr 15 13:25:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11491281 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E10B814B4 for ; Wed, 15 Apr 2020 13:25:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C117D20775 for ; Wed, 15 Apr 2020 13:25:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="IFg5skZR" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2632910AbgDONZs (ORCPT ); Wed, 15 Apr 2020 09:25:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2636097AbgDONZo (ORCPT ); Wed, 15 Apr 2020 09:25:44 -0400 Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B578C061A0C for ; Wed, 15 Apr 2020 06:25:44 -0700 (PDT) Received: by mail-pl1-x642.google.com with SMTP id z6so1235937plk.10 for ; Wed, 15 Apr 2020 06:25:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hf3xCHfH3xNg3T3scjfL+j1UjrvC8CIu881OAHKx3Lg=; b=IFg5skZRiUjZGa7Hav7YleeQZSKnR8akR2cL7Ri3s9N1F/CPqMM8VqIl/1eEhC7KqD ZIsX7ySax8/meAJXwzae68qTikgdInObrLpPpVH6wN/L4sfb3kwslP/Qvt4Si+hFHYUM CVCLD0lSrni/0hWYpfMNsxktyOt7RM8Gd7Hck= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hf3xCHfH3xNg3T3scjfL+j1UjrvC8CIu881OAHKx3Lg=; b=Gmo9NYdv7DsgasTOIUBEPoICh0NGao2M528GI1Ir1s59E0P4X5UEtqpM+e5QcuoPcU 7xrR3yElIk0FVC+OCdCOTvxRxK5NTq+EzuFGqnwk4/E43eDfB+o0ZoNa7MWICQO9pVAw JpPZ54432zD8Qvi7sHfF85n4Ve8T5oNqQrw1Ftzy/X3Stvohm/ZfrIKrNp7488lzo6Mu Mwaw86AgSt/bhJOXss7fJdC2ZcFe81e3HGZgCMhZtP/m4PMlZ65kPelsw1pZ6Kh0vPGI HlamrtUmP+jAdGQt7Ezc258rzKSib5zQBBgStF3Vm+dmhFwqbOJ3yeTQnFCIXgpkNcfL CDNg== X-Gm-Message-State: AGi0PuZyS4olLoBjRsA+prR2OqMrsmo3FzenlKAlZJ+w4zktBujoJUbl 93svSNSD85rS6qSNV7wY/L3wcDz5IKb8O44LUy51R7NSpm5wXE/6XnJEei46CvnwnDj+glO/tK0 4P/h95NcGIbq3yU/QWr5purMA9ghLOfeZVohfg2BhVf9OYfRx6U8YcPaX29HhZU+yOI9D3VYldd HbDkHN4XxAYJGzdXeI53Mr X-Google-Smtp-Source: APiQypKGnTNz1MnldXuLjE5Mah177bInjSwkRX+fuHwMRtBAnejrgeWdSImZlIcZQVzi4RVNcQGMZw== X-Received: by 2002:a17:90b:b08:: with SMTP id bf8mr5729349pjb.158.1586957143082; Wed, 15 Apr 2020 06:25:43 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id x186sm13715556pfb.151.2020.04.15.06.25.40 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2020 06:25:42 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu S Subject: [v1 1/5] mpt3sas: Don't change the dma coherent mask after allocations Date: Wed, 15 Apr 2020 09:25:21 -0400 Message-Id: <1586957125-19460-2-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Currently driver is initially setting the dma coherent mask to 32 bit and then after allocating the Reply Descriptor Post Queues(RDPQ) pools it changes the dma coherent mask to 64/63 according to HBA generation. But the DMA layer does not allow changing the DMA coherent mask after there are outstanding allocations. So, updating the driver to stop changing the dma coherent mask after allocations. Rename ioc variable "dma_mask" to "is_dma_32bit" and use it to set 32 bit DMA. Reported-by: Abdul Haleem Signed-off-by: Christoph Hellwig --- v1 Change log: 1) Incorporated the review comments from Christoph Hellwig Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 83 ++++++++++++++----------------------- drivers/scsi/mpt3sas/mpt3sas_base.h | 4 +- 2 files changed, 32 insertions(+), 55 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 663782b..8e937c8 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -2806,55 +2806,40 @@ _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge, static int _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev) { - u64 required_mask, coherent_mask; struct sysinfo s; - /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */ - int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64; + char *desc = "64"; + u64 consistent_dma_mask = DMA_BIT_MASK(64); + u64 required_mask = dma_get_required_mask(&pdev->dev); - if (ioc->is_mcpu_endpoint) - goto try_32bit; - - required_mask = dma_get_required_mask(&pdev->dev); - if (sizeof(dma_addr_t) == 4 || required_mask == 32) - goto try_32bit; - - if (ioc->dma_mask) - coherent_mask = DMA_BIT_MASK(dma_mask); - else - coherent_mask = DMA_BIT_MASK(32); - - if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) || - dma_set_coherent_mask(&pdev->dev, coherent_mask)) + if (ioc->is_mcpu_endpoint || ioc->is_dma_32bit || + sizeof(dma_addr_t) == 4 || required_mask == DMA_BIT_MASK(32)) goto try_32bit; - - ioc->base_add_sg_single = &_base_add_sg_single_64; - ioc->sge_size = sizeof(Mpi2SGESimple64_t); - ioc->dma_mask = dma_mask; - goto out; - - try_32bit: - if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) + /* + * Set 63 bit DMA mask for all SAS3 and SAS35 controllers + */ + if (ioc->hba_mpi_version_belonged > MPI2_VERSION) { + consistent_dma_mask = DMA_BIT_MASK(63); + desc = "63"; + } + if (!dma_set_mask(&pdev->dev, consistent_dma_mask) && + !dma_set_coherent_mask(&pdev->dev, consistent_dma_mask)) { + ioc->base_add_sg_single = &_base_add_sg_single_64; + ioc->sge_size = sizeof(Mpi2SGESimple64_t); + goto out; + } +try_32bit: + if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) + && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) { + ioc->base_add_sg_single = &_base_add_sg_single_32; + ioc->sge_size = sizeof(Mpi2SGESimple32_t); + desc = "32"; + } else return -ENODEV; - - ioc->base_add_sg_single = &_base_add_sg_single_32; - ioc->sge_size = sizeof(Mpi2SGESimple32_t); - ioc->dma_mask = 32; - out: +out: si_meminfo(&s); - ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", - ioc->dma_mask, convert_to_kb(s.totalram)); - - return 0; -} - -static int -_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc, - struct pci_dev *pdev) -{ - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) { - if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) - return -ENODEV; - } + ioc_info(ioc, + "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n", + desc, convert_to_kb(s.totalram)); return 0; } @@ -5169,14 +5154,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) total_sz += sz; } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); - if (ioc->dma_mask > 32) { - if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) { - ioc_warn(ioc, "no suitable consistent DMA mask for %s\n", - pci_name(ioc->pdev)); - goto out; - } - } - ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -7158,7 +7135,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc) ioc->smp_affinity_enable = smp_affinity_enable; ioc->rdpq_array_enable_assigned = 0; - ioc->dma_mask = 0; + ioc->is_dma_32bit = 0; if (ioc->is_aero_ioc) ioc->base_readl = &_base_readl_aero; else diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index e719715..396ac96 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -1026,7 +1026,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc); * @ir_firmware: IR firmware present * @bars: bitmask of BAR's that must be configured * @mask_interrupts: ignore interrupt - * @dma_mask: used to set the consistent dma mask + * @is_dma_32bit: used to set the consistent dma mask * @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and * pci resource handling * @fault_reset_work_q_name: fw fault work queue @@ -1205,7 +1205,7 @@ struct MPT3SAS_ADAPTER { u8 ir_firmware; int bars; u8 mask_interrupts; - int dma_mask; + int is_dma_32bit; /* fw fault handler */ char fault_reset_work_q_name[20]; From patchwork Wed Apr 15 13:25:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11491283 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2B8F14B4 for ; Wed, 15 Apr 2020 13:25:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8AE3E2074F for ; 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Wed, 15 Apr 2020 06:25:45 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id x186sm13715556pfb.151.2020.04.15.06.25.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2020 06:25:45 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu S Subject: [v1 2/5] mpt3sas: Rename function name is_MSB_are_same Date: Wed, 15 Apr 2020 09:25:22 -0400 Message-Id: <1586957125-19460-3-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Renamed is_MSB_are_same() to mpt3sas_check_same_4gb_region() for better readability. Signed-off-by: Suganath Prabu S Reviewed-by: Christoph Hellwig --- drivers/scsi/mpt3sas/mpt3sas_base.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 8e937c8..7f7b5af 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4920,7 +4920,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } /** - * is_MSB_are_same - checks whether all reply queues in a set are + * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are * having same upper 32bits in their base memory address. * @reply_pool_start_address: Base address of a reply queue set * @pool_sz: Size of single Reply Descriptor Post Queues pool size @@ -4930,7 +4930,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) */ static int -is_MSB_are_same(long reply_pool_start_address, u32 pool_sz) +mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) { long reply_pool_end_address; @@ -5382,7 +5382,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) * Actual requirement is not alignment, but we need start and end of * DMA address must have same upper 32 bit address. */ - if (!is_MSB_are_same((long)ioc->sense, sz)) { + if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) { //Release Sense pool & Reallocate dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma); dma_pool_destroy(ioc->sense_dma_pool); From patchwork Wed Apr 15 13:25:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11491285 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 00B57174A for ; Wed, 15 Apr 2020 13:26:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D94F520737 for ; Wed, 15 Apr 2020 13:26:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="BXqV4ofF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2636105AbgDON0A (ORCPT ); Wed, 15 Apr 2020 09:26:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2636100AbgDONZt (ORCPT ); Wed, 15 Apr 2020 09:25:49 -0400 Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7665CC061A0C for ; Wed, 15 Apr 2020 06:25:49 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id 201so31741pfv.2 for ; Wed, 15 Apr 2020 06:25:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a2Gcyt2zwERLVsg6RPGuiJE6CP/cWE63hYsQKWCW1ao=; b=BXqV4ofFVhVJFUKww4RTson2lu9JKdQpqNdKOgG+JxrqMHkVqt84lQNuXMYErT7jaL /vSaVL7amxOxvU90H7FHqZiMpqOb05l3M7obyRYR3t8Mvp1Pm9KHSYmXlibu0SmqkR82 5N2D7J5qruSc8pvx7vZvlDqRW8LFt4hmpz3mM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a2Gcyt2zwERLVsg6RPGuiJE6CP/cWE63hYsQKWCW1ao=; b=LTQM4X6NvhIyVI5GzP5Pigy1xP7TjKOWYXsdkV5hrrNO9Wm6ScmN9Je5OohKDAOC9J SO/XB8xREqjyHu/Tn2yidNhyxxyz9Q0b3Oi7Fxfhv62FvjiFFP0FKni7l3rRDUCTt62n vggQmgkA5S8PCadRB7myX5BRjq1v6NxvZcqxpAcPS4a65fLJ78weaHusOztfzwTJAWL1 4xVy9IbSPRd5y+bSI+jemY73oQsQO+JDnFy/Ovf9cXiz0ct6SZKXLK9DMJtdBAjtdZWG d5TZbomTh5DB2qFPvWUyrSLeKS6KTsuw2ALxnHgdlBVDr9+St9SuvxRdxhzxc+hT1bO2 RcQw== X-Gm-Message-State: AGi0Pubgik4YpPsq+V73QSp0R8d3LgKZ4MbF/LXjSDgnz3jtUxYbxFFS b3a+wYFgRTLWPmJQ+fx9fkXRdcGXXAw4/Tk27HgQoiTXyTS4sxidbJ5zLCkHNan/UTXVbw3/IDS qPp1/PELMdVnwEgNKUE/FrAESJtsB5Rckey1BDCn1P52yqtnW5kHPkVuT+xmZJKD31orakb0wkO ILOqTMi9J3m9/pqBZVuccj X-Google-Smtp-Source: APiQypIbw5tkFAwp9HaabXM/ZwhpwSHFdAJVF4XwiZ5WZI8UgF1UzzjNOi3hcgGrPBN0abxQOXZC+A== X-Received: by 2002:a65:4b8d:: with SMTP id t13mr7522927pgq.388.1586957148529; Wed, 15 Apr 2020 06:25:48 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id x186sm13715556pfb.151.2020.04.15.06.25.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2020 06:25:47 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu S Subject: [v1 3/5] mpt3sas: Separate out RDPQ allocation to new function. Date: Wed, 15 Apr 2020 09:25:23 -0400 Message-Id: <1586957125-19460-4-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S For readability separate out RDPQ allocations to new function base_alloc_rdpq_dma_pool(). Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 85 ++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 34 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 7f7b5af..27c829e 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -4944,6 +4944,55 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) } /** + * base_alloc_rdpq_dma_pool - Allocating DMA'able memory + * for reply queues. + * @ioc: per adapter object + * @sz: DMA Pool size + * Return: 0 for success, non-zero for failure. + */ +static int +base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) +{ + int i; + + ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? + (ioc->reply_queue_count):1, + sizeof(struct reply_post_struct), GFP_KERNEL); + + if (!ioc->reply_post) { + ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); + return -ENOMEM; + } + ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); + if (!ioc->reply_post_free_dma_pool) { + ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); + return -ENOMEM; + } + i = 0; + do { + ioc->reply_post[i].reply_post_free = + dma_pool_zalloc(ioc->reply_post_free_dma_pool, + GFP_KERNEL, + &ioc->reply_post[i].reply_post_free_dma); + if (!ioc->reply_post[i].reply_post_free) { + ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); + return -ENOMEM; + } + dinitprintk(ioc, + ioc_info(ioc, "reply post free pool (0x%p): depth(%d)," + "element_size(%d), pool_size(%d kB)\n", + ioc->reply_post[i].reply_post_free, + ioc->reply_post_queue_depth, 8, sz / 1024)); + dinitprintk(ioc, + ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", + (u64)ioc->reply_post[i].reply_post_free_dma)); + + } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + return 0; +} + +/** * _base_allocate_memory_pools - allocate start of day memory pools * @ioc: per adapter object * @@ -5118,41 +5167,9 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) sz = reply_post_free_sz; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) sz *= ioc->reply_queue_count; - - ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? - (ioc->reply_queue_count):1, - sizeof(struct reply_post_struct), GFP_KERNEL); - - if (!ioc->reply_post) { - ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); + if (base_alloc_rdpq_dma_pool(ioc, sz)) goto out; - } - ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); - if (!ioc->reply_post_free_dma_pool) { - ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); - goto out; - } - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, - GFP_KERNEL, - &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) { - ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); - goto out; - } - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, - 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); - total_sz += sz; - } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count); ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; From patchwork Wed Apr 15 13:25:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11491287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B1AC17EF for ; Wed, 15 Apr 2020 13:26:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 675E520737 for ; Wed, 15 Apr 2020 13:26:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="UaR8v0+k" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2636107AbgDON0D (ORCPT ); Wed, 15 Apr 2020 09:26:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2636101AbgDONZx (ORCPT ); Wed, 15 Apr 2020 09:25:53 -0400 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F231DC061A0E for ; Wed, 15 Apr 2020 06:25:52 -0700 (PDT) Received: by mail-pl1-x641.google.com with SMTP id t4so1229960plq.12 for ; Wed, 15 Apr 2020 06:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rf6x/KTTOIAwzoHwYKg3dCdH/l54Q/TaxTnrLHIz5bg=; b=UaR8v0+kDtirqidHg1iG0qd/aYFlktcnMX09huB4MQYTHNTOSWleFp4GE5tXttqjNS 3pcCWQrT2OxYb8FybfX4kIYlFL6tdvbVMvxSpW5JQ6PrJcCH0+i4fep0CEIBi08Jq64i gdulCbte7sVeDgsw3zf4+YbsPkXin0WU0fa3g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rf6x/KTTOIAwzoHwYKg3dCdH/l54Q/TaxTnrLHIz5bg=; b=blegYvc6Tf9802Oeg5R8KQiKkNE4ZNgxQMdmLDdPFd/Dx9t+cQINzxl8teKRR8+m9g K7oVjHRFMbPzA6aC0wPEWI3fGaqscBWLEMB6arynPGTF7X/+zF+Vny5LFbXDHvdqiOlr 48CU75JsOuHDIvOJMDZ0dl7REx8/zGqyaRsfauCgHbvAsVvIV+hxiADWH8lUOSD3KdLJ fjmTTdqGYUNCC9mPhhD5qm3IrhItW/F1HDVDEUgn2a5mWfgkcAPKk3HEk7O1tmpXlGfm RtRb+1Uc9arNg+rWotLDaJV9z08+l+FbpiVXkHPpG8JVpk6h1aaLir4d66OpTgtar69Y +H+Q== X-Gm-Message-State: AGi0PuYu4fL0EL2H5Gw4cZvV56EGuh4p85Zo+mFh2hM6Gb8gghkQL/Vn S+fej1dR6GbN6wD1IimU/rANmnlS2m1fhU/pNEr0XZYnqaNC7F+o+432ulJYlcrw1LHwGNRmocL 1PO64KBS/lw+SOkAgWiDItr/1sJHOlCxPVxcg42BZ4hrxKDVTZ/wULed2qOxNlw8DYWC4WQ1l2C vqnbpgUCfBA2IUCmaTxEmU X-Google-Smtp-Source: APiQypLD//c/6CQw4bi9V3aHP4CGdDyZIqfq5RuCfoT0hJe3W+2Lcp+N1fOAYbEubdvyW9feDK8M1A== X-Received: by 2002:a17:90a:3441:: with SMTP id o59mr5709106pjb.185.1586957151393; Wed, 15 Apr 2020 06:25:51 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id x186sm13715556pfb.151.2020.04.15.06.25.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2020 06:25:50 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu S Subject: [v1 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Date: Wed, 15 Apr 2020 09:25:24 -0400 Message-Id: <1586957125-19460-5-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..) and VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..) should be within 4 GB boundary. Driver uses limitation of VENTURA_SERIES to manage INVADER_SERIES as well. So here driver is allocating the DMA able memory for RDPQ's accordingly. 1) At driver load, set DMA Mask to 64 and allocate memory for RDPQ's. 2) Check if allocated resources for RDPQ are in the same 4GB range. 3) If #2 is true, continue with 64 bit DMA and go to #6 4) If #2 is false, then free all the resources from #1. 5) Set DMA mask to 32 and allocate RDPQ's. 6) Proceed with driver loading and other allocations Reviewed-by: Christoph Hellwig --- v1 Change log: 1) Use one dma pool for RDPQ's, thus removes the logic of using second dma pool with align. Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.c | 153 +++++++++++++++++++++++++----------- drivers/scsi/mpt3sas/mpt3sas_base.h | 1 + 2 files changed, 107 insertions(+), 47 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c index 27c829e..add23d7 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c @@ -3345,7 +3345,6 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc) pci_set_master(pdev); - if (_base_config_dma_addressing(ioc, pdev) != 0) { ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev)); r = -ENODEV; @@ -4812,8 +4811,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) { int i = 0; int j = 0; + int dma_alloc_count = 0; struct chain_tracker *ct; - struct reply_post_struct *rps; dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); @@ -4855,29 +4854,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc) } if (ioc->reply_post) { - do { - rps = &ioc->reply_post[i]; - if (rps->reply_post_free) { - dma_pool_free( - ioc->reply_post_free_dma_pool, - rps->reply_post_free, - rps->reply_post_free_dma); - dexitprintk(ioc, - ioc_info(ioc, "reply_post_free_pool(0x%p): free\n", - rps->reply_post_free)); - rps->reply_post_free = NULL; + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); + for (i = 0; i < ioc->reply_queue_count; i++) { + if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0 + && dma_alloc_count) { + if (ioc->reply_post[i].reply_post_free) { + dma_pool_free( + ioc->reply_post_free_dma_pool, + ioc->reply_post[i].reply_post_free, + ioc->reply_post[i].reply_post_free_dma); + dexitprintk(ioc, ioc_info(ioc, + "reply_post_free_pool(0x%p): free\n", + ioc->reply_post[i].reply_post_free)); + ioc->reply_post[i].reply_post_free = + NULL; + } + --dma_alloc_count; } - } while (ioc->rdpq_array_enable && - (++i < ioc->reply_queue_count)); + } + dma_pool_destroy(ioc->reply_post_free_dma_pool); if (ioc->reply_post_free_array && ioc->rdpq_array_enable) { dma_pool_free(ioc->reply_post_free_array_dma_pool, - ioc->reply_post_free_array, - ioc->reply_post_free_array_dma); + ioc->reply_post_free_array, + ioc->reply_post_free_array_dma); ioc->reply_post_free_array = NULL; } dma_pool_destroy(ioc->reply_post_free_array_dma_pool); - dma_pool_destroy(ioc->reply_post_free_dma_pool); kfree(ioc->reply_post); } @@ -4953,42 +4957,82 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz) static int base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz) { - int i; + int i = 0; + u32 dma_alloc_count = 0; + int reply_post_free_sz = ioc->reply_post_queue_depth * + sizeof(Mpi2DefaultReplyDescriptor_t); ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ? (ioc->reply_queue_count):1, sizeof(struct reply_post_struct), GFP_KERNEL); - if (!ioc->reply_post) { ioc_err(ioc, "reply_post_free pool: kcalloc failed\n"); return -ENOMEM; } - ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool", - &ioc->pdev->dev, sz, 16, 0); + /* + * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and + * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should + * be within 4GB boundary i.e reply queues in a set must have same + * upper 32-bits in their memory address. so here driver is allocating + * the DMA'able memory for reply queues according. + * Driver uses limitation of + * VENTURA_SERIES to manage INVADER_SERIES as well. + */ + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count, + RDPQ_MAX_INDEX_IN_ONE_CHUNK); + ioc->reply_post_free_dma_pool = + dma_pool_create("reply_post_free pool", + &ioc->pdev->dev, sz, 16, 0); if (!ioc->reply_post_free_dma_pool) { ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n"); return -ENOMEM; } - i = 0; - do { - ioc->reply_post[i].reply_post_free = - dma_pool_zalloc(ioc->reply_post_free_dma_pool, + for (i = 0; i < ioc->reply_queue_count; i++) { + if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) { + ioc->reply_post[i].reply_post_free = + dma_pool_alloc(ioc->reply_post_free_dma_pool, GFP_KERNEL, &ioc->reply_post[i].reply_post_free_dma); - if (!ioc->reply_post[i].reply_post_free) { - ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n"); - return -ENOMEM; - } - dinitprintk(ioc, - ioc_info(ioc, "reply post free pool (0x%p): depth(%d)," - "element_size(%d), pool_size(%d kB)\n", - ioc->reply_post[i].reply_post_free, - ioc->reply_post_queue_depth, 8, sz / 1024)); - dinitprintk(ioc, - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n", - (u64)ioc->reply_post[i].reply_post_free_dma)); + if (!ioc->reply_post[i].reply_post_free) { + ioc_err(ioc, "reply_post_free pool: " + "dma_pool_alloc failed\n"); + return -ENOMEM; + } + /* + * Each set of RDPQ pool must satisfy 4gb boundary + * restriction. + * 1) Check if allocated resources for RDPQ pool are in + * the same 4GB range. + * 2) If #1 is true, continue with 64 bit DMA. + * 3) If #1 is false, return 1. which means free all the + * resources and set DMA mask to 32 and allocate. + */ + if (!mpt3sas_check_same_4gb_region( + (long)ioc->reply_post[i].reply_post_free, sz)) { + dinitprintk(ioc, + ioc_err(ioc, "bad Replypost free pool(0x%p)" + "reply_post_free_dma = (0x%llx)\n", + ioc->reply_post[i].reply_post_free, + (unsigned long long) + ioc->reply_post[i].reply_post_free_dma)); + return -EAGAIN; + } + memset(ioc->reply_post[i].reply_post_free, 0, + RDPQ_MAX_INDEX_IN_ONE_CHUNK * + reply_post_free_sz); + dma_alloc_count--; - } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count)); + } else { + ioc->reply_post[i].reply_post_free = + (Mpi2ReplyDescriptorsUnion_t *) + ((long)ioc->reply_post[i-1].reply_post_free + + reply_post_free_sz); + ioc->reply_post[i].reply_post_free_dma = + (dma_addr_t) + (ioc->reply_post[i-1].reply_post_free_dma + + reply_post_free_sz); + } + } return 0; } @@ -5006,10 +5050,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) u16 chains_needed_per_io; u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz; u32 retry_sz; + u32 rdpq_sz = 0; u16 max_request_credit, nvme_blocks_needed; unsigned short sg_tablesize; u16 sge_size; int i, j; + int ret = 0; struct chain_tracker *ct; dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__)); @@ -5163,14 +5209,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) /* reply post queue, 16 byte align */ reply_post_free_sz = ioc->reply_post_queue_depth * sizeof(Mpi2DefaultReplyDescriptor_t); - - sz = reply_post_free_sz; + rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK; if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable) - sz *= ioc->reply_queue_count; - if (base_alloc_rdpq_dma_pool(ioc, sz)) - goto out; - total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count); - + rdpq_sz = reply_post_free_sz * ioc->reply_queue_count; + ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz); + if (ret == -EAGAIN) { + /* + * Free allocated bad RDPQ memory pools. + * Change dma coherent mask to 32 bit and reallocate RDPQ + */ + _base_release_memory_pools(ioc); + ioc->is_dma_32bit = 1; + if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) { + ioc_err(ioc, + "32 DMA mask failed %s\n", pci_name(ioc->pdev)); + return -ENODEV; + } + if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz)) + return -ENOMEM; + } else if (ret == -ENOMEM) + return -ENOMEM; + total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 : + DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK)); ioc->scsiio_depth = ioc->hba_queue_depth - ioc->hi_priority_depth - ioc->internal_depth; @@ -5182,7 +5242,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc) ioc_info(ioc, "scsi host: can_queue depth (%d)\n", ioc->shost->can_queue)); - /* contiguous pool for request and chains, 16 byte align, one extra " * "frame for smid=0 */ diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 396ac96..99724a7 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd { #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8 #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16 #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128 +#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16 /* OEM Specific Flags will come from OEM specific header files */ struct Mpi2ManufacturingPage10_t { From patchwork Wed Apr 15 13:25:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suganath Prabu S X-Patchwork-Id: 11491289 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B294714B4 for ; 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Wed, 15 Apr 2020 06:25:54 -0700 (PDT) Received: from dhcp-10-123-20-36.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id x186sm13715556pfb.151.2020.04.15.06.25.51 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 15 Apr 2020 06:25:53 -0700 (PDT) From: Suganath Prabu To: linux-scsi@vger.kernel.org Cc: hch@infradead.org, Sathya.Prakash@broadcom.com, sreekanth.reddy@broadcom.com, Suganath Prabu S Subject: [v1 5/5] mpt3sas: Update mpt3sas version to 33.101.00.00 Date: Wed, 15 Apr 2020 09:25:25 -0400 Message-Id: <1586957125-19460-6-git-send-email-suganath-prabu.subramani@broadcom.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> References: <1586957125-19460-1-git-send-email-suganath-prabu.subramani@broadcom.com> Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Suganath Prabu S Update mpt3sas driver version from 33.100.00.00 to 33.101.00.00 Signed-off-by: Suganath Prabu S --- drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 99724a7..c136157 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -76,9 +76,9 @@ #define MPT3SAS_DRIVER_NAME "mpt3sas" #define MPT3SAS_AUTHOR "Avago Technologies " #define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver" -#define MPT3SAS_DRIVER_VERSION "33.100.00.00" +#define MPT3SAS_DRIVER_VERSION "33.101.00.00" #define MPT3SAS_MAJOR_VERSION 33 -#define MPT3SAS_MINOR_VERSION 100 +#define MPT3SAS_MINOR_VERSION 101 #define MPT3SAS_BUILD_VERSION 0 #define MPT3SAS_RELEASE_VERSION 00