From patchwork Thu Apr 16 07:34:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11492427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E3F1692C for ; Thu, 16 Apr 2020 07:34:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC39B21556 for ; Thu, 16 Apr 2020 07:34:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="iZq8Kd3A" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439363AbgDPHet (ORCPT ); Thu, 16 Apr 2020 03:34:49 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:6238 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438944AbgDPHer (ORCPT ); Thu, 16 Apr 2020 03:34:47 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 16 Apr 2020 00:34:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 16 Apr 2020 00:34:47 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 16 Apr 2020 00:34:47 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Apr 2020 07:34:47 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 16 Apr 2020 07:34:47 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 16 Apr 2020 00:34:46 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V1 1/4] dt-bindings: usb: tegra-xudc: Add Tegra194 XUSB controller support Date: Thu, 16 Apr 2020 13:04:17 +0530 Message-ID: <1587022460-31988-2-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> References: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587022474; bh=xXeyeOzrJxjRg6qxD+Id9IV03wPtXpCgjlMCvQwVdc8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iZq8Kd3AWSN5BGra4tM++nPBdjCJj9BrumkIeBnNqmVBmxW5v/++eYk2PNuC00HKF paufb7qiGTd/sTGaotqfV/prsELoNRXbF2i0xdsLUkGGdlVoevmJ/ZkRReHoeH4pjn j0EOuxN6cNqq9tUm1flk1SDJ0N7vFHzF/8BCsmABxnBxbFRnBZq9hK9zvjW4TWGjmU kKHsYHhE15BlQLcBZCIO1nHgiFRcualtMclCs3u00XHaiCXmB7AsqaT0agkSvo0ZJG zaW7Sap1VGHev3im4zE12f79mIE88YaYEAJI/yn78LbDnWWd4HHmmqTOxEGKyQ6OPp OL8cJwX9sFMfw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Extend the Tegra XUSB controller device tree binding with Tegra194 support. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding Acked-by: Rob Herring --- Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index b84ed8e..75ea946 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -21,6 +21,7 @@ properties: - enum: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 + - nvidia,tegra194-xudc # For Tegra194 reg: minItems: 2 @@ -144,6 +145,7 @@ allOf: contains: enum: - nvidia,tegra186-xudc + - nvidia,tegra194-xudc then: properties: reg: From patchwork Thu Apr 16 07:34:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11492429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B032112C for ; Thu, 16 Apr 2020 07:34:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7549A21655 for ; Thu, 16 Apr 2020 07:34:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="WxZKqVtj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439388AbgDPHew (ORCPT ); Thu, 16 Apr 2020 03:34:52 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9951 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438944AbgDPHev (ORCPT ); Thu, 16 Apr 2020 03:34:51 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 16 Apr 2020 00:33:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 16 Apr 2020 00:34:50 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 16 Apr 2020 00:34:50 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Apr 2020 07:34:50 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 16 Apr 2020 07:34:50 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 16 Apr 2020 00:34:49 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V1 2/4] arm64: tegra: Add xudc node for Tegra194 Date: Thu, 16 Apr 2020 13:04:18 +0530 Message-ID: <1587022460-31988-3-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> References: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587022380; bh=qQMgfjYiYx+v2twyl6oIwGAWHyf/az0MjNbZ1f4jWms=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WxZKqVtjDUSee+hTgt3NV7XjgpkDb2wpY4Tmlo1q68czpHYEQnJpIyhWCXXGGuJAp RiTESSAb5CZRdQVQcAVDhnTFfWCBA2niIxRtbKvkbANDU1lW0G6/onM/aIYer8dCsM tNHLw8cxCayn90c3ZiP9ViARKDIY/fZIfjRDvwumRO9KPyo+wJ5yLxrbuvH84a/bwy Cqp6hLJyxqhcV9jDA3e8+2YEGOeD27JfMvytAAWMDxsExJqKtJbA7vom9DxZKNjxO0 fyYtO/BOEm/obMYtncm9JD4X1omxx6OF+6/omFySF/sZjyp7PZgaOOZe3qxcNncnFc yI0mUTfEv5RIw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Tegra194 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller Signed-off-by: Nagarjuna Kristam --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f4ede86..e1ae01c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -644,6 +644,24 @@ }; }; + usb@3550000 { + compatible = "nvidia,tegra194-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + usb@3610000 { compatible = "nvidia,tegra194-xusb"; reg = <0x03610000 0x40000>, From patchwork Thu Apr 16 07:34:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11492431 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F461112C for ; Thu, 16 Apr 2020 07:34:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 177DC214D8 for ; Thu, 16 Apr 2020 07:34:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="fAbQt8ec" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439399AbgDPHez (ORCPT ); Thu, 16 Apr 2020 03:34:55 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:6243 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438944AbgDPHex (ORCPT ); Thu, 16 Apr 2020 03:34:53 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 16 Apr 2020 00:34:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 16 Apr 2020 00:34:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 16 Apr 2020 00:34:53 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Apr 2020 07:34:53 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 16 Apr 2020 07:34:53 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 16 Apr 2020 00:34:52 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V1 3/4] usb: gadget: tegra-xudc: Add Tegra194 support Date: Thu, 16 Apr 2020 13:04:19 +0530 Message-ID: <1587022460-31988-4-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> References: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587022480; bh=0rPpKqpqRbtyPXXtz80/VGnqoHPuk5t0Vx4KqrlFy8s=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=fAbQt8ecdW2IERu56PRjLOTuSxlM8Wl3/NFUmYofdqMjkcEj2pMmd0TUM22eZQV+b DtE/cyKyJJoFcZYPUME0SkZmqC3xEYe6S2rYl+i1hLJhBrgQcaDIO2/Ce8xZ6dYFPT cgx4OygOWrK6/7PSG6chvxVz8UIaxbVw0AjyUhKqDb7ulHHDjMkgth2wdYQ2EtfhZZ JjC1n9aWYhNxZajjoBHgKqOf5KaICXXhUuioFYOACSl055cxDSOOB12XoMOmJVEaW6 cBHh3pSwRqCIUaCzJl2K6K8lWZfHQ/8cUJQe3A6Iwvd0DBFx4RRSHUnmkMyrtl+qHm cegzaLZ9NPQfw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This commit adds support for XUSB device mode controller support on Tegra194 SoC. This is very similar to the existing Tegra186 XUDC, with lpm support added in addition. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- drivers/usb/gadget/udc/tegra-xudc.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 52a6add..fb01117 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3494,6 +3494,13 @@ static const char * const tegra186_xudc_clock_names[] = { "fs_src", }; +static const char * const tegra194_xudc_clock_names[] = { + "dev", + "ss", + "ss_src", + "fs_src", +}; + static struct tegra_xudc_soc tegra210_xudc_soc_data = { .supply_names = tegra210_xudc_supply_names, .num_supplies = ARRAY_SIZE(tegra210_xudc_supply_names), @@ -3522,6 +3529,19 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra194_xudc_soc_data = { + .clock_names = tegra194_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra194_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3531,6 +3551,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra186-xudc", .data = &tegra186_xudc_soc_data }, + { + .compatible = "nvidia,tegra194-xudc", + .data = &tegra194_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match); From patchwork Thu Apr 16 07:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11492433 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B55FD112C for ; Thu, 16 Apr 2020 07:34:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 98787214D8 for ; Thu, 16 Apr 2020 07:34:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="opxz6HfZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439411AbgDPHe6 (ORCPT ); Thu, 16 Apr 2020 03:34:58 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:9968 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2438944AbgDPHe4 (ORCPT ); Thu, 16 Apr 2020 03:34:56 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 16 Apr 2020 00:33:06 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 16 Apr 2020 00:34:56 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 16 Apr 2020 00:34:56 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 16 Apr 2020 07:34:56 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 16 Apr 2020 07:34:55 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 16 Apr 2020 00:34:55 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V1 4/4] usb: gadget: tegra-xudc: add port_speed_quirk Date: Thu, 16 Apr 2020 13:04:20 +0530 Message-ID: <1587022460-31988-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> References: <1587022460-31988-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1587022386; bh=naqEuQE4k8cFdiWBVAPEQm5vMjpwh+WbGHA3Ol+AaAk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=opxz6HfZIJWYEIzeiI+X7Lf9binF1dK6DgrdR6jS/Sz7lBx8q+i/xCtnL1tBqy/Ap GMB/TsL77Nk12pl2qFZ9mWQu1jLSemwa6h/yf3UVgO1yR7z/cubFoJFUAn2h9mze1U r2QQUb6OaNFSH/mqE2Bo6cwyHS+K3yzuRbAU7PmHcbkGRuOS2IRzyeDlAVC6hU3KlE 6ARbenruqp8FkcrrmeHV0n2kn8cNGaaTYILhsiINxEWLxiOqVFCl4ZqyOp6RKM1h+T Pe6tkFu5GjEBNZ4wMiUBHBEtOiZgfOdFeSs4yO7+k+iwhsAUASULu3vFgRJSllfo99 weKekPQt/qXeQ== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add port_speed_quirk that modify below registers to limit/restore OTG port speed to GEN1/GEN2. SSPX_CORE_CNT56 SSPX_CORE_CNT57 SSPX_CORE_CNT65 SSPX_CORE_CNT66 SSPX_CORE_CNT67 SSPX_CORE_CNT72 The basic idea is to make SCD intentionally fail, reduce SCD timeout and force device transit to TSEQ. Enable this flag to only Tegra194. Based on work by WayneChang Signed-off-by: Nagarjuna Kristam --- drivers/usb/gadget/udc/tegra-xudc.c | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index fb01117..63484f98 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -158,6 +158,30 @@ #define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0) #define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \ SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK) +#define SSPX_CORE_CNT56 0x6fc +#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \ + SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK) +#define SSPX_CORE_CNT57 0x700 +#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \ + SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK) +#define SSPX_CORE_CNT65 0x720 +#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK) +#define SSPX_CORE_CNT66 0x724 +#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK) +#define SSPX_CORE_CNT67 0x728 +#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK) +#define SSPX_CORE_CNT72 0x73c +#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \ + SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK) #define SSPX_CORE_PADCTL4 0x750 #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0) #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \ @@ -530,6 +554,7 @@ struct tegra_xudc_soc { bool invalid_seq_num; bool pls_quirk; bool port_reset_quirk; + bool port_speed_quirk; bool has_ipfs; }; @@ -599,6 +624,78 @@ static inline void dump_trb(struct tegra_xudc *xudc, const char *type, trb->control); } +static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc) +{ + u32 val; + + /* limit port speed to gen 1 */ + val = xudc_readl(xudc, SSPX_CORE_CNT56); + val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260); + xudc_writel(xudc, val, SSPX_CORE_CNT56); + + val = xudc_readl(xudc, SSPX_CORE_CNT57); + val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK ); + val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6); + xudc_writel(xudc, val, SSPX_CORE_CNT57); + + val = xudc_readl(xudc, SSPX_CORE_CNT65); + val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); + val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT66); + val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); + val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT67); + val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); + val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT67); + + val = xudc_readl(xudc, SSPX_CORE_CNT72); + val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); + val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10); + xudc_writel(xudc, val, SSPX_CORE_CNT72); +} + +static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc) +{ + u32 val; + + /* restore port speed to gen2 */ + val = xudc_readl(xudc, SSPX_CORE_CNT56); + val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438); + xudc_writel(xudc, val, SSPX_CORE_CNT56); + + val = xudc_readl(xudc, SSPX_CORE_CNT57); + val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK ); + val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528); + xudc_writel(xudc, val, SSPX_CORE_CNT57); + + val = xudc_readl(xudc, SSPX_CORE_CNT65); + val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); + val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT66); + val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); + val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT67); + val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); + val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0); + xudc_writel(xudc, val, SSPX_CORE_CNT67); + + val = xudc_readl(xudc, SSPX_CORE_CNT72); + val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); + val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21); + xudc_writel(xudc, val, SSPX_CORE_CNT72); +} + static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) { int err; @@ -631,6 +728,9 @@ static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) reinit_completion(&xudc->disconnect_complete); + if (xudc->soc->port_speed_quirk) + tegra_xudc_restore_port_speed(xudc); + phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> @@ -3274,6 +3374,9 @@ static void tegra_xudc_device_params_init(struct tegra_xudc *xudc) xudc_writel(xudc, val, BLCG); } + if (xudc->soc->port_speed_quirk) + tegra_xudc_limit_port_speed(xudc); + /* Set a reasonable U3 exit timer value. */ val = xudc_readl(xudc, SSPX_CORE_PADCTL4); val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK); @@ -3513,6 +3616,7 @@ static struct tegra_xudc_soc tegra210_xudc_soc_data = { .invalid_seq_num = true, .pls_quirk = true, .port_reset_quirk = true, + .port_speed_quirk = false, .has_ipfs = true, }; @@ -3526,6 +3630,7 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .invalid_seq_num = false, .pls_quirk = false, .port_reset_quirk = false, + .port_speed_quirk = false, .has_ipfs = false, }; @@ -3539,6 +3644,7 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .invalid_seq_num = false, .pls_quirk = false, .port_reset_quirk = false, + .port_speed_quirk = true, .has_ipfs = false, };