From patchwork Thu Apr 16 17:43:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493573 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 778FE92C for ; Thu, 16 Apr 2020 17:43:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 555292223F for ; Thu, 16 Apr 2020 17:43:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pns9fgLX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729474AbgDPRnV (ORCPT ); Thu, 16 Apr 2020 13:43:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725906AbgDPRnU (ORCPT ); Thu, 16 Apr 2020 13:43:20 -0400 Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF95C061A0C; Thu, 16 Apr 2020 10:43:20 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id i10so5821939wrv.10; Thu, 16 Apr 2020 10:43:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=NrrUfW6vk8LgplT9nLEcV4V1JQYGDjA/MPqzeQmBnq8=; b=pns9fgLXDrLLhNt5os5ASORlyC0koVOzvPif+M5x6S/CCgOKjO3IyFkQNdQoP3Z4UK Tvm9T7/an5kT7IXWAtMWuoQN3Vy9ZfMa611ZA5SKsUb/YuNTorbImGAEkw5cq1ztrfoX 4G1rdsg4LZdti7+0vAU0O6q2Lka5A65gTEUKQUTcKrtvcFzlSgNcvgqPmC6f/fg913Z2 x/rYzoTUDjHhU/gVOMWsHnwbfOssQg9luk4Xte9TyK9j8IyIdlCvR5gqKHPKY7+t8M/M Jpy00ecl3IC3k0B5viNA7ImKIYwSGzF+tMUghlZZEVxpNmrPKQ2qs7/18StwPQWZUrWM vuqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=NrrUfW6vk8LgplT9nLEcV4V1JQYGDjA/MPqzeQmBnq8=; b=rAKn0liKVkckGwh1hkjlGoFk7puEo2tGIbovLgA96/TQj5g+D3fCYrLOY9cSSYDqAv 2A66KjGWp4mJ8uCAi/R/8LNNuNwcWZqRwz0eg3ClK3b/4Ps9/pxOnrHfPF/tvvCv57v4 iof1W2Yry8LxjjnPlkespcLSxHxnXdcGY5UNz/5/I7gsmh9Btweh8BZyyHArAkZAEyKK ezvSpwv7GfOw5DfNhML2tL1jC0Gjey32PPz1T8qxfsYlLQ/cdOUIFm5+G1K91C20JFfA er8TMkqEEe2QCiKWLBImVgGL20esfku319MKHTTFIl9V2PrjIq8X9osPfuG5UX9qQ+6j ztcg== X-Gm-Message-State: AGi0PuZYbas58h1DlHXUnQBZ3aaqXCMsnewLShS64ghv+kEtelnJ7Frb y9NOf6N1mJM0ovYbZn2p0rybgnhoxwk= X-Google-Smtp-Source: APiQypKFjOmDUmtTBtpZe21AkDnu+8Yk+AWo5X3eZCnDcLMBTElU/6Y2/S8IBVEwUYWgP8g00DuvTQ== X-Received: by 2002:adf:fa41:: with SMTP id y1mr34531615wrr.131.1587058999291; Thu, 16 Apr 2020 10:43:19 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:18 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Florian Fainelli , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 1/9] spi: bcm-qspi: Handle clock probe deferral Date: Thu, 16 Apr 2020 13:43:01 -0400 Message-Id: <20200416174309.34044-1-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional(). Signed-off-by: Florian Fainelli Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 23d295f36c80..74f4579c3f6a 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1222,6 +1222,11 @@ int bcm_qspi_probe(struct platform_device *pdev, } qspi = spi_master_get_devdata(master); + + qspi->clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(qspi->clk)) + return PTR_ERR(qspi->clk); + qspi->pdev = pdev; qspi->trans_pos.trans = NULL; qspi->trans_pos.byte = 0; @@ -1335,13 +1340,6 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->soc_intc = NULL; } - qspi->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(qspi->clk)) { - dev_warn(dev, "unable to get clock\n"); - ret = PTR_ERR(qspi->clk); - goto qspi_probe_err; - } - ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "failed to prepare clock\n"); From patchwork Thu Apr 16 17:43:02 2020 Content-Type: text/plain; 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Thu, 16 Apr 2020 10:43:28 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:27 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Date: Thu, 16 Apr 2020 13:43:02 -0400 Message-Id: <20200416174309.34044-2-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Added documentation for compatibility for brcmstb SoCs : 7425, 7429, 7435, 7216, 7278 Signed-off-by: Kamal Dasu --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt index ad7ac80a3841..f5e518d099f2 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -26,6 +26,16 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs From patchwork Thu Apr 16 17:43:03 2020 Content-Type: text/plain; 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Thu, 16 Apr 2020 10:43:31 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:30 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Florian Fainelli , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Date: Thu, 16 Apr 2020 13:43:03 -0400 Message-Id: <20200416174309.34044-3-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Older MIPS chips have a QSPI/MSPI controller that does not have the MSPI_REV offset, reading from that offset will cause a bus error. Match their compatible string and do not perform a read from that register in that case. Signed-off-by: Florian Fainelli Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 50 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 74f4579c3f6a..d901dcb10d06 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -91,6 +91,7 @@ #define MSPI_MSPI_STATUS 0x020 #define MSPI_CPTQP 0x024 #define MSPI_SPCR3 0x028 +#define MSPI_REV 0x02c #define MSPI_TXRAM 0x040 #define MSPI_RXRAM 0x0c0 #define MSPI_CDRAM 0x140 @@ -217,6 +218,8 @@ struct bcm_qspi { struct bcm_qspi_dev_id *dev_ids; struct completion mspi_done; struct completion bspi_done; + u8 mspi_maj_rev; + u8 mspi_min_rev; }; static inline bool has_bspi(struct bcm_qspi *qspi) @@ -1190,8 +1193,35 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { .exec_op = bcm_qspi_exec_mem_op, }; +struct bcm_qspi_data { + bool has_mspi_rev; +}; + +static const struct bcm_qspi_data bcm_qspi_no_rev_data = { + .has_mspi_rev = false, +}; + +static const struct bcm_qspi_data bcm_qspi_rev_data = { + .has_mspi_rev = true, +}; + static const struct of_device_id bcm_qspi_of_match[] = { - { .compatible = "brcm,spi-bcm-qspi" }, + { + .compatible = "brcm,spi-bcm7425-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm7429-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm7435-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm-qspi", + .data = &bcm_qspi_rev_data, + }, {}, }; MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); @@ -1199,12 +1229,15 @@ MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); int bcm_qspi_probe(struct platform_device *pdev, struct bcm_qspi_soc_intc *soc_intc) { + const struct of_device_id *of_id = NULL; + const struct bcm_qspi_data *data; struct device *dev = &pdev->dev; struct bcm_qspi *qspi; struct spi_master *master; struct resource *res; int irq, ret = 0, num_ints = 0; u32 val; + u32 rev = 0; const char *name = NULL; int num_irqs = ARRAY_SIZE(qspi_irq_tab); @@ -1212,9 +1245,12 @@ int bcm_qspi_probe(struct platform_device *pdev, if (!dev->of_node) return -ENODEV; - if (!of_match_node(bcm_qspi_of_match, dev->of_node)) + of_id = of_match_node(bcm_qspi_of_match, dev->of_node); + if (!of_id) return -ENODEV; + data = of_id->data; + master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); if (!master) { dev_err(dev, "error allocating spi_master\n"); @@ -1349,6 +1385,16 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->base_clk = clk_get_rate(qspi->clk); qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); + if (data->has_mspi_rev) { + rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); + /* some older revs do not have a MSPI_REV register */ + if ((rev & 0xff) == 0xff) + rev = 0; + } + + qspi->mspi_maj_rev = (rev >> 4) & 0xf; + qspi->mspi_min_rev = rev & 0xf; + bcm_qspi_hw_init(qspi); init_completion(&qspi->mspi_done); init_completion(&qspi->bspi_done); From patchwork Thu Apr 16 17:43:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493579 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33E6392C for ; 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Thu, 16 Apr 2020 10:43:34 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:34 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Date: Thu, 16 Apr 2020 13:43:04 -0400 Message-Id: <20200416174309.34044-4-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As per the spi core implementation for MSPI devices when the transfer is the last one in the message, the chip may stay selected until the next transfer. On multi-device SPI busses with nothing blocking messages going to other devices, this is just a performance hint; starting a message to another device deselects this one. But in other cases, this can be used to ensure correctness. Some devices need protocol transactions to be built from a series of spi_message submissions, where the content of one message is determined by the results of previous messages and where the whole transaction ends when the chipselect goes intactive. On CS change after completing the last serial transfer, the MSPI driver drives SSb pin CDRAM register correctly according comments in core spi.h as shown below: case 1) EOM =1, cs_change =0: SSb inactive case 2) EOM =1, cs_change =1: SSb active case 3) EOM =0, cs_change =0: SSb active case 4) EOM =0, cs_change =1: SSb inactive Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index d901dcb10d06..c48c399dce53 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -615,19 +615,15 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, if (qt->trans->cs_change && (flags & TRANS_STATUS_BREAK_CS_CHANGE)) ret |= TRANS_STATUS_BREAK_CS_CHANGE; - if (ret) - goto done; - dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); if (bcm_qspi_mspi_transfer_is_last(qspi, qt)) - ret = TRANS_STATUS_BREAK_EOM; + ret |= TRANS_STATUS_BREAK_EOM; else - ret = TRANS_STATUS_BREAK_NO_BYTES; + ret |= TRANS_STATUS_BREAK_NO_BYTES; qt->trans = NULL; } -done: dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); return ret; @@ -774,7 +770,16 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); - if (tstatus & TRANS_STATUS_BREAK_DESELECT) { + /* + * case 1) EOM =1, cs_change =0: SSb inactive + * case 2) EOM =1, cs_change =1: SSb stay active + * case 3) EOM =0, cs_change =0: SSb stay active + * case 4) EOM =0, cs_change =1: SSb inactive + */ + if (((tstatus & TRANS_STATUS_BREAK_DESELECT) + == TRANS_STATUS_BREAK_CS_CHANGE) || + ((tstatus & TRANS_STATUS_BREAK_DESELECT) + == TRANS_STATUS_BREAK_EOM)) { mspi_cdram = read_cdram_slot(qspi, slot - 1) & ~MSPI_CDRAM_CONT_BIT; write_cdram_slot(qspi, slot - 1, mspi_cdram); From patchwork Thu Apr 16 17:43:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493581 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8478381 for ; Thu, 16 Apr 2020 17:43:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A1D92064A for ; Thu, 16 Apr 2020 17:43:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fOgmbt24" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732294AbgDPRnn (ORCPT ); Thu, 16 Apr 2020 13:43:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1732560AbgDPRnj (ORCPT ); Thu, 16 Apr 2020 13:43:39 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60C50C061A0C; Thu, 16 Apr 2020 10:43:39 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id a81so5841522wmf.5; Thu, 16 Apr 2020 10:43:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VT7oTdX/J4WibqlSitG5Ze8BtxKf5ofSQPDu5bFcIAY=; b=fOgmbt24Fa/xv7ATQ9dhmpOd0y0QXDQQh0W/4CQEzpA6Pe01uxOJS1/7KvrkB9pkEa DzgqgT5+FzmdjalJIo8lJ1zyMBHp57w2ncsVIcBWDzgAulgIzDCKx8cr2ux1KpIx8xSD j7QujYdFFWMkrcYIxbLD2LOZIdw49nNw/L7FPGUDF8H2Cwyb6ANASGA3Har1oNw6T988 hK1fh6IQKIb7KFKLPE8Rkf7uz/iSfMrX3VFIK3WiJfPNjPBBfg7ZBA6BmG5xCp5YW83C XkPlyjXd/dixiGWdo/5BgTjRPTSkBtFWQ84wTpGbuD9wCwIoBEB/siOPcMz7yrkxBXg6 r50g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VT7oTdX/J4WibqlSitG5Ze8BtxKf5ofSQPDu5bFcIAY=; b=PpJEJN/5wVUGIkL8972EPD5f+TMr4e/kwUChk4qqCv6yI+lR8xA4NWOpAiPXc8xEcS VQ8XeeU/W7/1CZ2fbPJc122xSg3u7Pe6+FDEAC+ue8jw47ckHTSNkTkearscskw0NKcy Tv2SfeYYSt6+9Xkd0G1QMZ2+KvuBjOc4FdLLDb4tsr4N6Ea1I9+j5kkvTsx74k/rf1WP Dt3QIcb0srkr8z41TM/iWzgPxqMSws9hHetWJJQS7EfoJs9WR82aDnBiPfWpq1EJCgjW lG0//b3viDWhdVm5TLd4I53Nzkx5efIFV+GY9JIK0t67Lf6+uErlP4tsD4vBFhlkfl98 LCfA== X-Gm-Message-State: AGi0PuZbVma6XxksOAOmWplwp9g6haTUrU+BkfE+KoilVeNk+IBH8RlH 7/2cVH+QhgMeDB7lyZfWUzo= X-Google-Smtp-Source: APiQypLo4NDGXDAu77RQZ+RaXOO40hdqk4TsG4dKky3/yxjnH0amcSxZ1bCC89R+4pQq1Iprl7f+7g== X-Received: by 2002:a7b:c1da:: with SMTP id a26mr5651209wmj.125.1587059018163; Thu, 16 Apr 2020 10:43:38 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:37 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Justin Chen , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Date: Thu, 16 Apr 2020 13:43:05 -0400 Message-Id: <20200416174309.34044-5-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Currently we set the tx/rx buffer to 0xff when NULL. This causes problems with some spi slaves where 0xff is a valid command. Looking at other drivers, the tx/rx buffer is usually set to 0x00 when NULL. Following this convention solves the issue. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Justin Chen Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index c48c399dce53..e00208801c8b 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -669,7 +669,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots) if (buf) buf[tp.byte] = read_rxram_slot_u8(qspi, slot); dev_dbg(&qspi->pdev->dev, "RD %02x\n", - buf ? buf[tp.byte] : 0xff); + buf ? buf[tp.byte] : 0x0); } else { u16 *buf = tp.trans->rx_buf; @@ -677,7 +677,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots) buf[tp.byte / 2] = read_rxram_slot_u16(qspi, slot); dev_dbg(&qspi->pdev->dev, "RD %04x\n", - buf ? buf[tp.byte] : 0xffff); + buf ? buf[tp.byte / 2] : 0x0); } update_qspi_trans_byte_count(qspi, &tp, @@ -732,13 +732,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) while (!tstatus && slot < MSPI_NUM_CDRAM) { if (tp.trans->bits_per_word <= 8) { const u8 *buf = tp.trans->tx_buf; - u8 val = buf ? buf[tp.byte] : 0xff; + u8 val = buf ? buf[tp.byte] : 0x00; write_txram_slot_u8(qspi, slot, val); dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); } else { const u16 *buf = tp.trans->tx_buf; - u16 val = buf ? buf[tp.byte / 2] : 0xffff; + u16 val = buf ? buf[tp.byte / 2] : 0x0000; write_txram_slot_u16(qspi, slot, val); dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); From patchwork Thu Apr 16 17:43:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493583 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3582892C for ; Thu, 16 Apr 2020 17:43:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 194152064A for ; Thu, 16 Apr 2020 17:43:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZJja63Vq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733292AbgDPRnr (ORCPT ); Thu, 16 Apr 2020 13:43:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1732896AbgDPRnn (ORCPT ); Thu, 16 Apr 2020 13:43:43 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C321C061A0C; Thu, 16 Apr 2020 10:43:42 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id x4so5534671wmj.1; Thu, 16 Apr 2020 10:43:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jF5s6mIDV3imWHwN3gxECUXiGCch+faubGbjA6qiFuo=; b=ZJja63VqjxQSor/OTOHUgcBFFUlAlwS2Sz6byrUNrboZexWwV0EQ+QV3R+z0m5Olrf g+c2KjEO6xdMrFrxwe1kYvdTfCGDdsqa2198ujvDJPBZuEIWn0d5nkXTvd61DgbAWHal p/yoD6XV7ZdWxoRAkLNYPtQ+gApo3U9rYgY72FB33U5O2JLPVYpnXygbwzwR5e/4OTY9 WzkB1jh8/GByzE5mVRiq5h+zGY2SR2x9BAlzwvMggjrwHmVMGQs5yiovVa9bpflUIds9 /2cFr/LMxGqk8/FSoZQYLYOK2Lvq5/OCH0v24WA2oKTDF0YKW9byQKlpvaEk417MjzBZ Asaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jF5s6mIDV3imWHwN3gxECUXiGCch+faubGbjA6qiFuo=; b=ZIl2upFO0YeDWnBhP920Iv1U2V53JdW7mGlDg5+OEh5QLKl9ZIYjJLgfefK8M0MXd1 f3esux4oTeWcRMhLrb/hQj4sVKYPG9M2RjKF69FEpVYsFgjM+w9kn5M0ihhDp2dy8or1 vgpxaDYGcJ8ULc3s5MU4IXnVdxp8XN6bfig8TRjshANFEx2FE3Bwmlum2XLI+KnUD+KF OAnXK0PPlaZiIJ57+IXfpMv86DNfyq38KLaANLxunxP5f5giJJxtsxwKct2bZZ+kxi5U NPkOWbQtqVMbnj1i2BZnJH8TUfmBaIk38iaPyEPET2uyhELVoq9jr3N+lJTUETVSkrTM veGA== X-Gm-Message-State: AGi0PuaqJvMLR6K8b7yktfqwKSQmz4Y3DOEHFwZfdSL/JLfF8T6V0GGl Up5bb4rJ6m5gmxDpifScglY= X-Google-Smtp-Source: APiQypKABfDL3aBsjY878f0gyJuW4CTyhdV1K0/71xLp4SDNdTH/MRJGPB/DmsdCVy0QtbA9U9e4kw== X-Received: by 2002:a05:600c:2941:: with SMTP id n1mr6082191wmd.25.1587059021446; Thu, 16 Apr 2020 10:43:41 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:41 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Date: Thu, 16 Apr 2020 13:43:06 -0400 Message-Id: <20200416174309.34044-6-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SCMI only passes clk_prepare_enable() and clk_disable_unprepare(), made changes to suspend/resume ops to use the appropriate calls so that PM works for ARM and ARM64 platforms. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index e00208801c8b..a3936ae5a860 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1455,7 +1455,7 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev) bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); spi_master_suspend(qspi->master); - clk_disable(qspi->clk); + clk_disable_unprepare(qspi->clk); bcm_qspi_hw_uninit(qspi); return 0; @@ -1473,7 +1473,7 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev) qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, true); - ret = clk_enable(qspi->clk); + ret = clk_prepare_enable(qspi->clk); if (!ret) spi_master_resume(qspi->master); From patchwork Thu Apr 16 17:43:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBBBC81 for ; Thu, 16 Apr 2020 17:43:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A33982223F for ; Thu, 16 Apr 2020 17:43:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pkR7bMbd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731573AbgDPRn5 (ORCPT ); Thu, 16 Apr 2020 13:43:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729252AbgDPRnx (ORCPT ); Thu, 16 Apr 2020 13:43:53 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4298BC061A0C; Thu, 16 Apr 2020 10:43:52 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id a81so5842279wmf.5; Thu, 16 Apr 2020 10:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OZ96LAcwn+BELPZteh+FF1ZZG0PwSRcuJ8BBRDIlsU=; b=pkR7bMbd/nbASMOpMKJ+a4qCQ6/poc7lIW7LbNVFTW+mf0T3IW3Ct+a/43TpHO4EnT hueTAnQsLxbZbeNCgOOileSs36x79BNaOpkFQZFt1ehtysy2kg3odHYJv7ppYPKnpGC4 wt6KD3wOZxakmA/qP1OnxqfyAbACL++EWURo1Tpcb2GODGRlWPze+i4KppI54rCU/Sgc F7bWTRxi2OTEgMux4XnX5MC8FGy0HGqJ7v3L06UyAd3qgGpX00yS4Zr8T4hR/uJQmtQN y2pASjPqye+VWN9A14dA2YNkKHr7erYdjSeFlU2EzyT2T/sm+xue0fHGO9q9bZ4VVS0M z9bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OZ96LAcwn+BELPZteh+FF1ZZG0PwSRcuJ8BBRDIlsU=; b=lRv+XqXV6n2hsZ5tUwFpnOozO+F3NbhwLaiuCg1W6zjFHMoCk7MbIjvmmHPuRsYmnj LyKAIGl5/NdegshJMyUvDno8osNhkqaYS4OdDlgsFiOFQj0i/Mi3MGr4tNn6cUcYI81j qUZfXR3Cej7t0XTUEJmqUkUCFDAfY7Rwa8epBBW7wxqvD0JKR53OLwbwsgAvr+SSm83g noNcXzzCyjve3r3NTrLaqiV1YFGrBCiBIz1Fn31rUm2GquwWX7mcgJQno3xR7DVSZx+1 GICK+OwG2Sj3J0eYSLmm0cQ6PNuwyDiamup0hTMTHyt0ANJcfOxSwYsFO+/O7Z46jBhx yZkQ== X-Gm-Message-State: AGi0PuZCovQ5HYTBasELpcwzKOA3/NP0me404tCnDWBjXxZQE/4kmLrr geMFnOeAEyX0YN+Xod0oDNE= X-Google-Smtp-Source: APiQypKYNwLnBbdY/fFSnFE9nzSzFaHjKQi4OXnXowBqj4DelxYMkCtj9koNkJoDO7SouXLQpZ8tAg== X-Received: by 2002:a1c:23d6:: with SMTP id j205mr5844291wmj.22.1587059030074; Thu, 16 Apr 2020 10:43:50 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:49 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Date: Thu, 16 Apr 2020 13:43:07 -0400 Message-Id: <20200416174309.34044-7-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of 1-7, while the default value prohibits these values and requires a minimum clock divider value of 8. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index a3936ae5a860..edc601dbf221 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -107,13 +107,15 @@ #define MSPI_SPCR2_SPE BIT(6) #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) +#define MSPI_SPCR3_FASTBR BIT(0) +#define MSPI_SPCR3_FASTDT BIT(1) + #define MSPI_MSPI_STATUS_SPIF BIT(0) #define INTR_BASE_BIT_SHIFT 0x02 #define INTR_COUNT 0x07 #define NUM_CHIPSELECT 4 -#define QSPI_SPBR_MIN 8U #define QSPI_SPBR_MAX 255U #define OPCODE_DIOR 0xBB @@ -227,6 +229,25 @@ static inline bool has_bspi(struct bcm_qspi *qspi) return qspi->bspi_mode; } +/* hardware supports spcr3 and fast baud-rate */ +static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) +{ + if (!has_bspi(qspi) && + ((qspi->mspi_maj_rev >= 1) && + (qspi->mspi_min_rev >= 5))) + return true; + + return false; +} + +static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) +{ + if (bcm_qspi_has_fastbr(qspi)) + return 1; + else + return 8; +} + /* Read qspi controller register*/ static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, unsigned int offset) @@ -534,7 +555,7 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, if (xp->speed_hz) spbr = qspi->base_clk / (2 * xp->speed_hz); - spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX); + spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX); bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); spcr = MSPI_MASTER_BIT; @@ -544,6 +565,14 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, spcr |= xp->mode & 3; bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); + if (bcm_qspi_has_fastbr(qspi)) { + spcr = 0; + + /* enable fastbr */ + spcr |= MSPI_SPCR3_FASTBR; + bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); + } + qspi->last_parms = *xp; } @@ -1388,7 +1417,6 @@ int bcm_qspi_probe(struct platform_device *pdev, } qspi->base_clk = clk_get_rate(qspi->clk); - qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); if (data->has_mspi_rev) { rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); @@ -1400,6 +1428,8 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->mspi_maj_rev = (rev >> 4) & 0xf; qspi->mspi_min_rev = rev & 0xf; + qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); + bcm_qspi_hw_init(qspi); init_completion(&qspi->mspi_done); init_completion(&qspi->bspi_done); From patchwork Thu Apr 16 17:43:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493587 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19B7114DD for ; Thu, 16 Apr 2020 17:43:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F3FD92223F for ; Thu, 16 Apr 2020 17:43:57 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 16 Apr 2020 10:43:53 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Date: Thu, 16 Apr 2020 13:43:08 -0400 Message-Id: <20200416174309.34044-8-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Adding support for MSPI sys clk 108Mhz available on 7216 and 7278 BRCMSTB SoCs. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index edc601dbf221..99f2cfcbb50c 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -109,6 +109,11 @@ #define MSPI_SPCR3_FASTBR BIT(0) #define MSPI_SPCR3_FASTDT BIT(1) +#define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10) +#define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \ + ~(BIT(10) | BIT(11))) +#define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \ + BIT(11)) #define MSPI_MSPI_STATUS_SPIF BIT(0) @@ -117,6 +122,7 @@ #define NUM_CHIPSELECT 4 #define QSPI_SPBR_MAX 255U +#define MSPI_BASE_FREQ 27000000UL #define OPCODE_DIOR 0xBB #define OPCODE_QIOR 0xEB @@ -222,6 +228,7 @@ struct bcm_qspi { struct completion bspi_done; u8 mspi_maj_rev; u8 mspi_min_rev; + bool mspi_spcr3_sysclk; }; static inline bool has_bspi(struct bcm_qspi *qspi) @@ -240,6 +247,17 @@ static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) return false; } +/* hardware supports sys clk 108Mhz */ +static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) +{ + if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || + ((qspi->mspi_maj_rev >= 1) && + (qspi->mspi_min_rev >= 6)))) + return true; + + return false; +} + static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) { if (bcm_qspi_has_fastbr(qspi)) @@ -570,6 +588,15 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, /* enable fastbr */ spcr |= MSPI_SPCR3_FASTBR; + + if (bcm_qspi_has_sysclk_108(qspi)) { + /* SYSCLK_108 */ + spcr |= MSPI_SPCR3_SYSCLKSEL_108; + qspi->base_clk = MSPI_BASE_FREQ * 4; + /* Change spbr as we changed sysclk */ + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4); + } + bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); } @@ -1229,14 +1256,22 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { struct bcm_qspi_data { bool has_mspi_rev; + bool has_spcr3_sysclk; }; static const struct bcm_qspi_data bcm_qspi_no_rev_data = { .has_mspi_rev = false, + .has_spcr3_sysclk = false, }; static const struct bcm_qspi_data bcm_qspi_rev_data = { .has_mspi_rev = true, + .has_spcr3_sysclk = false, +}; + +static const struct bcm_qspi_data bcm_qspi_spcr3_data = { + .has_mspi_rev = true, + .has_spcr3_sysclk = true, }; static const struct of_device_id bcm_qspi_of_match[] = { @@ -1256,6 +1291,14 @@ static const struct of_device_id bcm_qspi_of_match[] = { .compatible = "brcm,spi-bcm-qspi", .data = &bcm_qspi_rev_data, }, + { + .compatible = "brcm,spi-bcm7216-qspi", + .data = &bcm_qspi_spcr3_data, + }, + { + .compatible = "brcm,spi-bcm7278-qspi", + .data = &bcm_qspi_spcr3_data, + }, {}, }; MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); @@ -1427,6 +1470,7 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->mspi_maj_rev = (rev >> 4) & 0xf; qspi->mspi_min_rev = rev & 0xf; + qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk; qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); From patchwork Thu Apr 16 17:43:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11493589 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8452181 for ; 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Thu, 16 Apr 2020 10:43:57 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id p7sm28736296wrf.31.2020.04.16.10.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2020 10:43:56 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Date: Thu, 16 Apr 2020 13:43:09 -0400 Message-Id: <20200416174309.34044-9-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200416174309.34044-1-kdasu.kdev@gmail.com> References: <20200416174309.34044-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers. refs #SWLINUX-5186 Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 99f2cfcbb50c..681d09085175 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -576,11 +576,17 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX); bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); - spcr = MSPI_MASTER_BIT; + if (!qspi->mspi_maj_rev) + /* legacy controller */ + spcr = MSPI_MASTER_BIT; + else + spcr = 0; + /* for 16 bit the data should be zero */ if (xp->bits_per_word != 16) spcr |= xp->bits_per_word << 2; spcr |= xp->mode & 3; + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); if (bcm_qspi_has_fastbr(qspi)) {