From patchwork Fri Apr 17 14:44:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 11495331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6A6792C for ; Fri, 17 Apr 2020 14:45:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF83E2076A for ; Fri, 17 Apr 2020 14:45:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF83E2076A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 78B856EC24; Fri, 17 Apr 2020 14:45:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id AFBAC6EC24 for ; Fri, 17 Apr 2020 14:44:59 +0000 (UTC) IronPort-SDR: 4d5l28PDfM+Lh6e5639UkqVr8PZ3ZyqQFocLP0TRhzvrv+sjTSt++nt+UX1o53NNerLCXJVttR g47sqFpm1cJg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2020 07:44:59 -0700 IronPort-SDR: gjnTF4TJ6E1rouJs3xzeoG6Wt34rTEK5Em/xdmOSscUdKQeRpvkSIXY5VAEPWUyAH5vKIuDwzl W4pymUbjTrTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,395,1580803200"; d="scan'208";a="257599072" Received: from rosetta.fi.intel.com ([10.237.72.194]) by orsmga006.jf.intel.com with ESMTP; 17 Apr 2020 07:44:58 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id AFD23843785; Fri, 17 Apr 2020 17:44:32 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Apr 2020 17:44:27 +0300 Message-Id: <20200417144429.20575-1-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Add per ctx batchbuffer wa for timestamp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chris Wilson MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Restoration of a previous timestamp can collide with updating the timestamp, causing a value corruption. Combat this issue by using indirect ctx bb to modify the context image during restoring process. For render engine, we can preload value into scratch register. From which we then do the actual write with LRR. LRR is faster and thus less error prone. For other engines, no scratch is available so we must do a more complex sequence of sync and async LRMs. As the LRM is slower, the probablity of racy write raises and thus we still see corruption sometimes. References: HSDES#16010904313 Testcase: igt/i915_selftest/gt_lrc Suggested-by: Joseph Koston Cc: Chris Wilson Signed-off-by: Mika Kuoppala bug on fix --- drivers/gpu/drm/i915/gt/intel_context_types.h | 3 + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 3 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 196 ++++++++++++++---- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 + 4 files changed, 165 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h index 07cb83a0d017..c7573d565f58 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_types.h +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h @@ -70,6 +70,9 @@ struct intel_context { u32 *lrc_reg_state; u64 lrc_desc; + + u32 ctx_bb_offset; + u32 tag; /* cookie passed to HW to track this context on submission */ /* Time on GPU as tracked by the hw. */ diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index f04214a54f75..0c2adb4078a7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -138,7 +138,7 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) /* Gen11+. addr = base + (ctx_restore ? offset & GENMASK(12,2) : offset) */ -#define MI_LRI_CS_MMIO (1<<19) +#define MI_LRI_LRM_CS_MMIO (1<<19) #define MI_LRI_FORCE_POSTED (1<<12) #define MI_LOAD_REGISTER_IMM_MAX_REGS (126) #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) @@ -155,6 +155,7 @@ #define MI_FLUSH_DW_USE_PPGTT (0<<2) #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) +#define MI_LRM_ASYNC (1<<21) #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 6fbad5e2343f..531884b9050c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -234,7 +234,7 @@ static void execlists_init_reg_state(u32 *reg_state, const struct intel_ring *ring, bool close); static void -__execlists_update_reg_state(const struct intel_context *ce, +__execlists_update_reg_state(struct intel_context *ce, const struct intel_engine_cs *engine, u32 head); @@ -537,7 +537,7 @@ static void set_offsets(u32 *regs, if (flags & POSTED) *regs |= MI_LRI_FORCE_POSTED; if (INTEL_GEN(engine->i915) >= 11) - *regs |= MI_LRI_CS_MMIO; + *regs |= MI_LRI_LRM_CS_MMIO; regs++; GEM_BUG_ON(!count); @@ -3142,8 +3142,152 @@ static void execlists_context_unpin(struct intel_context *ce) i915_gem_object_unpin_map(ce->state->obj); } +static u32 intel_lr_indirect_ctx_offset(const struct intel_engine_cs *engine) +{ + u32 indirect_ctx_offset; + + switch (INTEL_GEN(engine->i915)) { + default: + MISSING_CASE(INTEL_GEN(engine->i915)); + fallthrough; + case 12: + indirect_ctx_offset = + GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 11: + indirect_ctx_offset = + GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 10: + indirect_ctx_offset = + GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 9: + indirect_ctx_offset = + GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 8: + indirect_ctx_offset = + GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + } + + return indirect_ctx_offset; +} + +static u32 * +gen12_emit_timestamp_wa_lrm(struct intel_context *ce, u32 *cs) +{ + const u32 lrc_offset = i915_ggtt_offset(ce->state) + + LRC_STATE_PN * PAGE_SIZE; + const u32 lrm = MI_LOAD_REGISTER_MEM_GEN8 | + MI_SRM_LRM_GLOBAL_GTT | MI_LRI_LRM_CS_MMIO; + + *cs++ = lrm; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + *cs++ = lrc_offset + CTX_TIMESTAMP * sizeof(u32); + *cs++ = 0; + + *cs++ = lrm | MI_LRM_ASYNC; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + *cs++ = lrc_offset + CTX_TIMESTAMP * sizeof(u32); + *cs++ = 0; + + *cs++ = lrm | MI_LRM_ASYNC; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + *cs++ = lrc_offset + CTX_TIMESTAMP * sizeof(u32); + *cs++ = 0; + + *cs++ = lrm; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + *cs++ = lrc_offset + CTX_TIMESTAMP * sizeof(u32); + *cs++ = 0; + + return cs; +} + +static u32 * +gen12_emit_timestamp_wa_lrr(struct intel_context *ce, u32 *cs) +{ + const u32 lrc_offset = i915_ggtt_offset(ce->state) + + LRC_STATE_PN * PAGE_SIZE; + const u32 lrm = MI_LOAD_REGISTER_MEM_GEN8 | + MI_SRM_LRM_GLOBAL_GTT | MI_LRI_LRM_CS_MMIO; + const u32 scratch_reg = 0x2198; + + *cs++ = lrm; + *cs++ = scratch_reg; + *cs++ = lrc_offset + CTX_TIMESTAMP * sizeof(u32); + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_REG | MI_LRI_LRM_CS_MMIO; + *cs++ = scratch_reg; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + + *cs++ = MI_LOAD_REGISTER_REG | MI_LRI_LRM_CS_MMIO; + *cs++ = scratch_reg; + *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + + return cs; +} + +static u32 * +execlists_emit_ctx_bb(struct intel_context *ce, + u32 *(*emit)(struct intel_context *, u32 *)) +{ + u32 *cs = (void *)(ce->lrc_reg_state) - + LRC_STATE_PN * PAGE_SIZE + ce->ctx_bb_offset; + const u32 * const batch_start = cs; + + GEM_DEBUG_BUG_ON(!ce->ctx_bb_offset); + + cs = emit(ce, cs); + + GEM_DEBUG_BUG_ON(cs - batch_start > + (I915_GTT_PAGE_SIZE - 4)/sizeof(*cs)); + + return cs; +} + +static void +execlists_setup_indirect_ctx_bb(struct intel_context *ce, + u32 *(*emit)(struct intel_context *, u32 *)) +{ + const u32 indirect_ptr_offset = + INTEL_GEN(ce->engine->i915) >= 12 ? + GEN12_CTX_BB_PER_CTX_PTR + 2 : + CTX_BB_PER_CTX_PTR + 2; + const u32 * const start = (void *)(ce->lrc_reg_state) - + LRC_STATE_PN * PAGE_SIZE + ce->ctx_bb_offset; + u32 *cs; + + cs = execlists_emit_ctx_bb(ce, emit); + + while ((unsigned long)cs % CACHELINE_BYTES) + *cs++ = MI_NOOP; + + ce->lrc_reg_state[indirect_ptr_offset] = + (i915_ggtt_offset(ce->state) + ce->ctx_bb_offset) | + (cs - start) * sizeof(*cs) / + CACHELINE_BYTES; + + ce->lrc_reg_state[indirect_ptr_offset + 2] = + intel_lr_indirect_ctx_offset(ce->engine) << 6; +} + static void -__execlists_update_reg_state(const struct intel_context *ce, +gen12_setup_timestamp_ctx_wa(struct intel_context *ce) +{ + if (ce->engine->class == RENDER_CLASS) + execlists_setup_indirect_ctx_bb(ce, + gen12_emit_timestamp_wa_lrr); + else + execlists_setup_indirect_ctx_bb(ce, + gen12_emit_timestamp_wa_lrm); +} + +static void +__execlists_update_reg_state(struct intel_context *ce, const struct intel_engine_cs *engine, u32 head) { @@ -3164,6 +3308,13 @@ __execlists_update_reg_state(const struct intel_context *ce, intel_sseu_make_rpcs(engine->i915, &ce->sseu); i915_oa_init_reg_state(ce, engine); + + } + + if (ce->ctx_bb_offset) { + /* Mutually exclusive wrt to global indirect bb */ + GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size); + gen12_setup_timestamp_ctx_wa(ce); } } @@ -4667,40 +4818,6 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) return 0; } -static u32 intel_lr_indirect_ctx_offset(const struct intel_engine_cs *engine) -{ - u32 indirect_ctx_offset; - - switch (INTEL_GEN(engine->i915)) { - default: - MISSING_CASE(INTEL_GEN(engine->i915)); - /* fall through */ - case 12: - indirect_ctx_offset = - GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - break; - case 11: - indirect_ctx_offset = - GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - break; - case 10: - indirect_ctx_offset = - GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - break; - case 9: - indirect_ctx_offset = - GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - break; - case 8: - indirect_ctx_offset = - GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; - break; - } - - return indirect_ctx_offset; -} - - static void init_common_reg_state(u32 * const regs, const struct intel_engine_cs *engine, const struct intel_ring *ring, @@ -4867,6 +4984,11 @@ static int __execlists_context_alloc(struct intel_context *ce, if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) context_size += I915_GTT_PAGE_SIZE; /* for redzone */ + if (INTEL_GEN(engine->i915) == 12) { + ce->ctx_bb_offset = context_size; + context_size += PAGE_SIZE; + } + ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size); if (IS_ERR(ctx_obj)) return PTR_ERR(ctx_obj); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index d39b72590e40..bb444614f33b 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -32,6 +32,7 @@ /* GEN12+ Reg State Context */ #define GEN12_CTX_BB_PER_CTX_PTR (0x12 + 1) +#define CTX_BB_PER_CTX_PTR_VALID BIT(0) #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ u32 *reg_state__ = (reg_state); \ From patchwork Fri Apr 17 14:44:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 11495333 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3B97713B2 for ; Fri, 17 Apr 2020 14:45:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2497D2076A for ; Fri, 17 Apr 2020 14:45:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2497D2076A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 200B96EC27; Fri, 17 Apr 2020 14:45:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 942836EC06 for ; Fri, 17 Apr 2020 14:44:59 +0000 (UTC) IronPort-SDR: kHSaTC6o5dZOfweudycw6EdTvXmmfm6b72mRCzHBJAv30Xk8zsaGuIHQrjqRejr7pLmkOLQem0 wC+77lrgTn/A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2020 07:44:59 -0700 IronPort-SDR: Cx5+WGN8M15GtXVb1aMN0vBVgOOqLUCDZWztVKTOq1vUVxJypF9WUCIGtpkkuNqqD3cp1dK2Bp ohP2xV8BH3UA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,395,1580803200"; d="scan'208";a="257599071" Received: from rosetta.fi.intel.com ([10.237.72.194]) by orsmga006.jf.intel.com with ESMTP; 17 Apr 2020 07:44:58 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id B50378400F9; Fri, 17 Apr 2020 17:44:32 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Apr 2020 17:44:28 +0300 Message-Id: <20200417144429.20575-2-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417144429.20575-1-mika.kuoppala@linux.intel.com> References: <20200417144429.20575-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Add live selftests for indirect ctx batchbuffers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add live selftest for indirect ctx context batchbuffers Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/selftest_lrc.c | 152 ++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c index 6f5e35afe1b2..cd7543e10813 100644 --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c @@ -5363,6 +5363,155 @@ static int live_lrc_isolation(void *arg) return err; } +static int ctx_bb_submit_req(struct intel_context *ce) +{ + struct i915_request *rq; + int err; + + rq = intel_context_create_request(ce); + if (IS_ERR(rq)) + return PTR_ERR(rq); + + i915_request_get(rq); + i915_request_add(rq); + + err = i915_request_wait(rq, 0, HZ / 5); + if (err < 0) + pr_err("%s: request not completed!\n", rq->engine->name); + + i915_request_put(rq); + + return 0; +} + +#define CTX_BB_CANARY_OFFSET (3*1024) +#define CTX_BB_CANARY_INDEX (CTX_BB_CANARY_OFFSET/sizeof(u32)) + +static u32 * +emit_ctx_bb_canary(struct intel_context *ce, u32 *cs) +{ + const u32 ring_start_reg = i915_mmio_reg_offset(RING_START(0)); + const u32 srm = MI_STORE_REGISTER_MEM_GEN8 | + MI_SRM_LRM_GLOBAL_GTT | MI_LRI_LRM_CS_MMIO; + + *cs++ = srm; + *cs++ = ring_start_reg; + *cs++ = i915_ggtt_offset(ce->state) + + ce->ctx_bb_offset + CTX_BB_CANARY_OFFSET; + *cs++ = 0; + + return cs; +} + +static void +ctx_bb_setup(struct intel_context *ce) +{ + u32 *cs = (void *)(ce->lrc_reg_state) - + LRC_STATE_PN * PAGE_SIZE + ce->ctx_bb_offset; + + cs[CTX_BB_CANARY_INDEX] = 0xdeadf00d; + + execlists_setup_indirect_ctx_bb(ce, emit_ctx_bb_canary); +} + +static bool check_ring_start(struct intel_context *ce) +{ + const u32 * const ctx_bb = (void *)(ce->lrc_reg_state) - + LRC_STATE_PN * PAGE_SIZE + ce->ctx_bb_offset; + + if (ctx_bb[CTX_BB_CANARY_INDEX] == ce->lrc_reg_state[CTX_RING_START]) + return true; + + pr_err("ring start mismatch canary 0x%08x vs state 0x%08x\n", + ctx_bb[CTX_BB_CANARY_INDEX], + ce->lrc_reg_state[CTX_RING_START]); + + return false; +} + +static int ctx_bb_check(struct intel_context *ce) +{ + int err; + + err = ctx_bb_submit_req(ce); + if (err) + return err; + + if (!check_ring_start(ce)) + return -EINVAL; + + return 0; +} + +static int __per_ctx_bb(struct intel_engine_cs *engine) +{ + struct intel_context *ce1, *ce2; + int err = 0; + + ce1 = intel_context_create(engine); + ce2 = intel_context_create(engine); + + err = intel_context_pin(ce1); + if (err) + return err; + + err = intel_context_pin(ce2); + if (err) { + intel_context_put(ce1); + return err; + } + + if (!ce1->ctx_bb_offset) { + GEM_BUG_ON(ce2->ctx_bb_offset); + /* must have */ + GEM_BUG_ON(INTEL_GEN(engine->i915) == 12); + goto out; + } + + /* make the batch to grab ring start and write it to canary spot */ + ctx_bb_setup(ce1); + ctx_bb_setup(ce2); + + err = ctx_bb_check(ce1); + if (err) + goto out; + + err = ctx_bb_check(ce2); +out: + intel_context_unpin(ce2); + intel_context_put(ce2); + + intel_context_unpin(ce1); + intel_context_put(ce1); + + return err; +} + +static int live_lrc_indirect_ctx_bb(void *arg) +{ + struct intel_gt *gt = arg; + struct intel_engine_cs *engine; + enum intel_engine_id id; + int err = 0; + + for_each_engine(engine, gt, id) { + + intel_engine_pm_get(engine); + err = __per_ctx_bb(engine); + intel_engine_pm_put(engine); + + if (err) + break; + + if (igt_flush_test(gt->i915)) { + err = -EIO; + break; + } + } + + return err; +} + static void garbage_reset(struct intel_engine_cs *engine, struct i915_request *rq) { @@ -5594,10 +5743,11 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915) SUBTEST(live_lrc_fixed), SUBTEST(live_lrc_state), SUBTEST(live_lrc_gpr), - SUBTEST(live_lrc_isolation), + SUBTEST(live_lrc_indirect_ctx_bb), SUBTEST(live_lrc_timestamp), SUBTEST(live_lrc_garbage), SUBTEST(live_pphwsp_runtime), + SUBTEST(live_lrc_isolation), }; if (!HAS_LOGICAL_RING_CONTEXTS(i915)) From patchwork Fri Apr 17 14:44:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 11495329 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C69F613B2 for ; Fri, 17 Apr 2020 14:45:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ADAC22076A for ; Fri, 17 Apr 2020 14:45:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADAC22076A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 189776EC06; Fri, 17 Apr 2020 14:45:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id AD2E26EC23 for ; Fri, 17 Apr 2020 14:44:59 +0000 (UTC) IronPort-SDR: zuKRoxD3Wg9s4hFbIPBoKsGyqNHyi0xnCdG8qDzZxu4efI3xwjonSkJsFFQVuNPGpN6yuht+DK OEOTfiPbwdpQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2020 07:44:59 -0700 IronPort-SDR: M5r+QQeFOo7zbcitCwFXFsJf2Qc5KerUVhIUNFw2/i82OB7BKdDCsUYCRbdqiISn5r3xXn6dU2 9ZvfdDHB37IQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,395,1580803200"; d="scan'208";a="454749611" Received: from rosetta.fi.intel.com ([10.237.72.194]) by fmsmga005.fm.intel.com with ESMTP; 17 Apr 2020 07:44:57 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id BA5D68442BB; Fri, 17 Apr 2020 17:44:32 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Apr 2020 17:44:29 +0300 Message-Id: <20200417144429.20575-3-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200417144429.20575-1-mika.kuoppala@linux.intel.com> References: <20200417144429.20575-1-mika.kuoppala@linux.intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Use indirect ctx bb to mend CMD_BUF_CCTL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Use indirect ctx bb to load cmd buffer control value from context image to avoid corruption. Testcase: igt/i915_selftest/gt_lrc Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 13 +++++++++++-- drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 531884b9050c..45e07209ddf3 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3207,7 +3207,7 @@ gen12_emit_timestamp_wa_lrm(struct intel_context *ce, u32 *cs) } static u32 * -gen12_emit_timestamp_wa_lrr(struct intel_context *ce, u32 *cs) +gen12_emit_render_ctx_wa(struct intel_context *ce, u32 *cs) { const u32 lrc_offset = i915_ggtt_offset(ce->state) + LRC_STATE_PN * PAGE_SIZE; @@ -3228,6 +3228,15 @@ gen12_emit_timestamp_wa_lrr(struct intel_context *ce, u32 *cs) *cs++ = scratch_reg; *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); + *cs++ = lrm; + *cs++ = scratch_reg; + *cs++ = lrc_offset + CTX_CMD_BUF_CCTL * sizeof(u32); + *cs++ = 0; + + *cs++ = MI_LOAD_REGISTER_REG | MI_LRI_LRM_CS_MMIO; + *cs++ = scratch_reg; + *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); + return cs; } @@ -3280,7 +3289,7 @@ gen12_setup_timestamp_ctx_wa(struct intel_context *ce) { if (ce->engine->class == RENDER_CLASS) execlists_setup_indirect_ctx_bb(ce, - gen12_emit_timestamp_wa_lrr); + gen12_emit_render_ctx_wa); else execlists_setup_indirect_ctx_bb(ce, gen12_emit_timestamp_wa_lrm); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h index bb444614f33b..6c81a3a815ac 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h +++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h @@ -27,6 +27,7 @@ #define CTX_PDP0_UDW (0x30 + 1) #define CTX_PDP0_LDW (0x32 + 1) #define CTX_R_PWR_CLK_STATE (0x42 + 1) +#define CTX_CMD_BUF_CCTL (0xB6 + 1) #define GEN9_CTX_RING_MI_MODE 0x54 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a24e23e9b3d0..b31ca8e4399f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2657,6 +2657,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RING_DMA_FADD_UDW(base) _MMIO((base) + 0x60) /* gen8+ */ #define RING_INSTPM(base) _MMIO((base) + 0xc0) #define RING_MI_MODE(base) _MMIO((base) + 0x9c) +#define RING_CMD_BUF_CCTL(base) _MMIO((base) + 0x84) #define INSTPS _MMIO(0x2070) /* 965+ only */ #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ #define ACTHD_I965 _MMIO(0x2074)