From patchwork Fri Apr 17 18:41:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11495945 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8FC22174A for ; Fri, 17 Apr 2020 18:41:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7915020780 for ; Fri, 17 Apr 2020 18:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="tR8/oPjB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728862AbgDQSln (ORCPT ); Fri, 17 Apr 2020 14:41:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727969AbgDQSll (ORCPT ); Fri, 17 Apr 2020 14:41:41 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ADF0C061A0C; Fri, 17 Apr 2020 11:41:41 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id x25so3929856wmc.0; Fri, 17 Apr 2020 11:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pDfj/QraDSKRnuL+EP//h6wcVnH2S8rr57iQRcR8OO4=; b=tR8/oPjB9/ARC6Hww1D9hRyK/54LWHuBJ+pEdpKCepWwuReRyO2Nuab4w0rvaaHqK4 u8layFvzbJh1hpiDg2tCv5gBb6ylIeBOmfJM5ixjUs+Jro8434qaruah3qBH8byFQcva Z8U2c/Fx3YrJu7x5fA58+yphQvt4/frOW6854zyDxZvbSvcu0aqEFeoUQMTTvSJT3jOm l+zq2hQBC94+pkeNQrCTKmRE4lPv1e3iTsWVlXmy4FwnDdPY65zHBIEQt12kJRRiCN7F 0JAW3rLLWtskqYGDRpKtnZdseu5z5rLUSFUXpmvaxYbIc/w1yLBPrFcWTbeDsTCRw30i Ui4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pDfj/QraDSKRnuL+EP//h6wcVnH2S8rr57iQRcR8OO4=; b=IRG3HpUHp4weXP2o9E64B6Im45yCx0JKRA2a5PHLjaq+3m547IkcxbvFPQ/mhFF1iz jUHFwjxmvL7qjnhfKw97+WRBv2FNcxgzQYW4ftbvWpBjqf8f2yRsr12KeVdKrUs1a5Hg g+zDIdjf0T4H6MQnvpkAJYL1ulzY70ArpRTUBX/IboTe3ktSgj56fGYNtaKVMtf2C9fV Mjm9dlEaCFSKNkZ8CsSXaArZxhqihT/TzpssaguMMuiUK+rKDbldnggQ5oXytkK+D1GS E9GupujN8AbeDxd6/szmQBev6+8P1UwwYZzUU0hK9+/J17w5MJoprgivnXesDCoJwSLo 0BVQ== X-Gm-Message-State: AGi0Puax3WTAwyiBXjmOd4JrthyMSURQ3nRYjJd/bcKHunSOytI0u5kl ilF07qi2pRY870NI7PVCYr4= X-Google-Smtp-Source: APiQypK5zOAKZQ5Jv4qR6V0MqyvU1fbrwrOUGQZj8hr390Y8FhwQ0Ia7fSUa6KYL6mXnV95wrrnNkQ== X-Received: by 2002:a7b:c20f:: with SMTP id x15mr4506759wmi.2.1587148900114; Fri, 17 Apr 2020 11:41:40 -0700 (PDT) Received: from localhost.localdomain (p200300F137142E00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3714:2e00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c17sm33237391wrp.28.2020.04.17.11.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2020 11:41:39 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 1/4] clk: meson: meson8b: Fix the first parent of vid_pll_in_sel Date: Fri, 17 Apr 2020 20:41:24 +0200 Message-Id: <20200417184127.1319871-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> References: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 7c55c695cbae..90d284ffc780 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { * Meson8m2: vid2_pll */ .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw + &meson8b_hdmi_pll_lvds_out.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Fri Apr 17 18:41:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11495947 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B23B912 for ; Fri, 17 Apr 2020 18:41:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EC8322202 for ; Fri, 17 Apr 2020 18:41:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="mRTd94CV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729405AbgDQSlz (ORCPT ); Fri, 17 Apr 2020 14:41:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728801AbgDQSlm (ORCPT ); Fri, 17 Apr 2020 14:41:42 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ECDAC061A0C; Fri, 17 Apr 2020 11:41:42 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id x25so3929893wmc.0; Fri, 17 Apr 2020 11:41:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HhRrcSbzdrYOhGIkbng34xs3uvw4GEDIaENc9GUahfI=; b=mRTd94CVe3OP71yIcqIkEo4fR/JzFwnwJ3xI98No421tTKrDWiDH0OxlBm6fIC3mHL tAp/JQFabJ0VMJe63sveMQciuu/CsEggJklaxNqt1nTCUVGI8G1VyvgSr6QBvsw+vp1j yDf+t8L1PCX0bfUj8RO3cv5cBDcyts76f1AoR/DC7QYD4QOHpf/DuW47NpP4YW2YzVla fLyb22Fm8XK/S0xfMrx2axzSWg84dDPk8HSiCWFDkYAHsQtqEoI5Ao8W2ntnssxoEi7o f4YMyUh+60Us+P15RDrtgs2fyA3jBvMmlKqKRsK9C3/MQbGRupQuKGRe22fYZ1f3wC0i CQSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HhRrcSbzdrYOhGIkbng34xs3uvw4GEDIaENc9GUahfI=; b=V5WsJ+DQHvHjRGNX+4aALnGVMPiUS1JgEKOm6b5uAJR27wxR9v5M7TO4rki+4arjl9 htJ3l5742k3SCRqxQoMpAnjIuI1J2PAgUPUI+mhCfpYGCrIdxBXSiY7178Ox7w0rQ39l HjwPTBYJ1KCg8GdQ5Sq3Av/oocg94GL826HoE/ig5WZEZE6PuI1UoHZB1g1/wfvaTAg6 27uVoS6eTIUk8a3MQVrIp3WinSlYv1IsLCNlEaIqKPsos9MweyOtrrMqsu3DGz+7uzoQ ADB62FIn8BUqym3dPcQZXEVjk+tA5olYW0/LyO+fu8XsAqqpMuAk2QPrMEFIV57Vwmte 0Bxg== X-Gm-Message-State: AGi0Puayc8cVpVsLjWqYXOWgs6j2RF6O09xjaFFlvrYPZBtjodAPxOhU e75tc/1AVH+CdypymDLMAiY= X-Google-Smtp-Source: APiQypLZVwsv1sUcu/VFJzhsLAmrPBJK+b+iI07XhRYdWUMc5S2KJK4PgA7rOE687BGjZMq4vKXOUw== X-Received: by 2002:a1c:b684:: with SMTP id g126mr4491736wmf.163.1587148901133; Fri, 17 Apr 2020 11:41:41 -0700 (PDT) Received: from localhost.localdomain (p200300F137142E00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3714:2e00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c17sm33237391wrp.28.2020.04.17.11.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2020 11:41:40 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 2/4] clk: meson: meson8b: Fix the polarity of the RESET_N lines Date: Fri, 17 Apr 2020 20:41:25 +0200 Message-Id: <20200417184127.1319871-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> References: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means: - asserting them requires setting the register value to 0 - de-asserting them requires setting the register value to 1 Set the register value accordingly for these two reset lines by setting the inverted the register value compared to all other reset lines. Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller") Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 79 ++++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 23 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 90d284ffc780..1dec8d5404a1 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -3506,54 +3506,87 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { static const struct meson8b_clk_reset_line { u32 reg; u8 bit_idx; + bool active_low; } meson8b_clk_reset_bits[] = { [CLKC_RESET_L2_CACHE_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 30, + .active_low = false, }, [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 29, + .active_low = false, }, [CLKC_RESET_SCU_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 28, + .active_low = false, }, [CLKC_RESET_CPU3_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 27, + .active_low = false, }, [CLKC_RESET_CPU2_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 26, + .active_low = false, }, [CLKC_RESET_CPU1_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 25, + .active_low = false, }, [CLKC_RESET_CPU0_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 24, + .active_low = false, }, [CLKC_RESET_A5_GLOBAL_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 18, + .active_low = false, }, [CLKC_RESET_A5_AXI_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 17, + .active_low = false, }, [CLKC_RESET_A5_ABP_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16 + .reg = HHI_SYS_CPU_CLK_CNTL0, + .bit_idx = 16, + .active_low = false, }, [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = { - .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30 + .reg = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 30, + .active_low = false, }, [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = { - .reg = HHI_VID_CLK_CNTL, .bit_idx = 15 + .reg = HHI_VID_CLK_CNTL, + .bit_idx = 15, + .active_low = false, }, [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = { - .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7 + .reg = HHI_VID_DIVIDER_CNTL, + .bit_idx = 7, + .active_low = false, }, [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = { - .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3 + .reg = HHI_VID_DIVIDER_CNTL, + .bit_idx = 3, + .active_low = false, }, [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = { - .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1 + .reg = HHI_VID_DIVIDER_CNTL, + .bit_idx = 1, + .active_low = true, }, [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = { - .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0 + .reg = HHI_VID_DIVIDER_CNTL, + .bit_idx = 0, + .active_low = true, }, }; @@ -3562,22 +3595,22 @@ static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev, { struct meson8b_clk_reset *meson8b_clk_reset = container_of(rcdev, struct meson8b_clk_reset, reset); - unsigned long flags; const struct meson8b_clk_reset_line *reset; + unsigned int value = 0; + unsigned long flags; if (id >= ARRAY_SIZE(meson8b_clk_reset_bits)) return -EINVAL; reset = &meson8b_clk_reset_bits[id]; + if (assert != reset->active_low) + value = BIT(reset->bit_idx); + spin_lock_irqsave(&meson_clk_lock, flags); - if (assert) - regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, - BIT(reset->bit_idx), BIT(reset->bit_idx)); - else - regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, - BIT(reset->bit_idx), 0); + regmap_update_bits(meson8b_clk_reset->regmap, reset->reg, + BIT(reset->bit_idx), value); spin_unlock_irqrestore(&meson_clk_lock, flags); From patchwork Fri Apr 17 18:41:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11495943 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CAAE8174A for ; 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[2003:f1:3714:2e00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c17sm33237391wrp.28.2020.04.17.11.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2020 11:41:41 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 3/4] clk: meson: meson8b: Fix the vclk_div{1,2,4,6,12}_en gate bits Date: Fri, 17 Apr 2020 20:41:26 +0200 Message-Id: <20200417184127.1319871-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> References: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL register: - HHI_VID_CLK_CNTL[0] = DIV1_EN - HHI_VID_CLK_CNTL[1] = DIV2_EN - HHI_VID_CLK_CNTL[2] = DIV4_EN - HHI_VID_CLK_CNTL[3] = DIV6_EN - HHI_VID_CLK_CNTL[4] = DIV12_EN Update the bits accordingly so we will enable the bits in the correct register once we switch these clocks to be mutable. Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees") Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 1dec8d5404a1..6d1727e62b55 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1213,7 +1213,7 @@ static struct clk_regmap meson8b_vclk_in_en = { static struct clk_regmap meson8b_vclk_div1_gate = { .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_CLK_DIV, + .offset = HHI_VID_CLK_CNTL, .bit_idx = 0, }, .hw.init = &(struct clk_init_data){ @@ -1243,7 +1243,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = { static struct clk_regmap meson8b_vclk_div2_div_gate = { .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_CLK_DIV, + .offset = HHI_VID_CLK_CNTL, .bit_idx = 1, }, .hw.init = &(struct clk_init_data){ @@ -1273,7 +1273,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = { static struct clk_regmap meson8b_vclk_div4_div_gate = { .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_CLK_DIV, + .offset = HHI_VID_CLK_CNTL, .bit_idx = 2, }, .hw.init = &(struct clk_init_data){ @@ -1303,7 +1303,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = { static struct clk_regmap meson8b_vclk_div6_div_gate = { .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_CLK_DIV, + .offset = HHI_VID_CLK_CNTL, .bit_idx = 3, }, .hw.init = &(struct clk_init_data){ @@ -1333,7 +1333,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = { static struct clk_regmap meson8b_vclk_div12_div_gate = { .data = &(struct clk_regmap_gate_data){ - .offset = HHI_VID_CLK_DIV, + .offset = HHI_VID_CLK_CNTL, .bit_idx = 4, }, .hw.init = &(struct clk_init_data){ From patchwork Fri Apr 17 18:41:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 11495939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 684EB912 for ; Fri, 17 Apr 2020 18:41:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 50FA020780 for ; Fri, 17 Apr 2020 18:41:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=googlemail.com header.i=@googlemail.com header.b="LB3xbvk8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729258AbgDQSlp (ORCPT ); Fri, 17 Apr 2020 14:41:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729136AbgDQSlo (ORCPT ); Fri, 17 Apr 2020 14:41:44 -0400 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900A9C061A0C; Fri, 17 Apr 2020 11:41:44 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id i10so4167088wrv.10; Fri, 17 Apr 2020 11:41:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p4RArEPtRb6yXEdgtQ3ovyy6FMchkA9pg/LkRnSfJR8=; b=LB3xbvk8qJejz7tCjtEyfb58WU6LIalruJuOoQB1Cneg3/jqPgHlbv12NNDaHlpzmV o4uu9ADrf4vAphiHiJGYnZeemkZ8JE8PszXtVht45LbV0jh+JbkeLCUgh+NQv3ew0EET 5OiBadJ8IJ60jWXZcJ9Mh/m0VvlOUHi4cRATM4vw8O+eKPsyatKhe+icKhBA2UTl0dad OLrmY/o1wUQK/j6xSJ9Pka6ITAWn4HHjRddCbGUV2CsNveMOBp6rZIwhb03JPd0/FdGw erl8L7qmaKONyIRCGNvpUFl9zUFYxMecqk3JJryPWqoARSS8D+vPJJSMwceyE8a2smeE sQgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p4RArEPtRb6yXEdgtQ3ovyy6FMchkA9pg/LkRnSfJR8=; b=sVNVKiXQH6qrORXRmzEMDiGYzre2Ql2TUYXCSIaeHEEHnx5hs5cIAHxj23qxMlg3Ct IeRoBm0ja9IQ+XRajyenkDBdsORXjNIfKdE9g5xNeL96EnZzeH2MdmWDz5fD+9SwmLF8 MawFfdjGYg/18utl2+qeYMF6lhLvESAQwS1K1/DqUBGKsJiaAej7d2Dfi03hburHqI/L cMq/Ib8Eiggu5GfIrMtzcR+Le745vDnKutdw7L7xXz0zSNj76HUeoZnGk78Nqebxu9Vi cAzfHcZRFcqUtYD/iNQ5d3IXL2K4+/RThpMJmnveCgtrhuye4LP6EYzTJIaI9mIEBTjA h8mQ== X-Gm-Message-State: AGi0PuYpadrW3gWc2sE+Fj/9hJ1nmDbRHhW272b+f4rBmSdB51Yi22Pg IC7YQLSynLzueNpI+Asv5yM= X-Google-Smtp-Source: APiQypLp5qHymcuJPKjzUtOnmkQmLSVUjfmU7kNQvo46lL7qlgyByinKLdOTrFJU3TOKc0KrRY21yw== X-Received: by 2002:adf:f884:: with SMTP id u4mr5203954wrp.171.1587148903269; Fri, 17 Apr 2020 11:41:43 -0700 (PDT) Received: from localhost.localdomain (p200300F137142E00428D5CFFFEB99DB8.dip0.t-ipconnect.de. [2003:f1:3714:2e00:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id c17sm33237391wrp.28.2020.04.17.11.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2020 11:41:42 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org Cc: narmstrong@baylibre.com, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 4/4] clk: meson: meson8b: Make the CCF use the glitch-free VPU mux Date: Fri, 17 Apr 2020 20:41:27 +0200 Message-Id: <20200417184127.1319871-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> References: <20200417184127.1319871-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The "vpu_0" or "vpu_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1" tree when "vpu_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the VPU clock. Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/meson8b.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 6d1727e62b55..811af1c11456 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2063,7 +2063,7 @@ static struct clk_regmap meson8b_vpu_0 = { &meson8b_vpu_0_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; @@ -2134,10 +2134,18 @@ static struct clk_regmap meson8b_vpu_1 = { &meson8b_vpu_1_div.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, }, }; +/* + * The VPU clock has two two identical clock trees (vpu_0 and vpu_1) + * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can + * actually manage this glitch-free mux because it does top-to-bottom + * updates the each clock tree and switches to the "inactive" one when + * CLK_SET_RATE_GATE is set. + * Meson8 only has vpu_0 and no glitch-free mux. + */ static struct clk_regmap meson8b_vpu = { .data = &(struct clk_regmap_mux_data){ .offset = HHI_VPU_CLK_CNTL, @@ -2152,7 +2160,7 @@ static struct clk_regmap meson8b_vpu = { &meson8b_vpu_1.hw, }, .num_parents = 2, - .flags = CLK_SET_RATE_NO_REPARENT, + .flags = CLK_SET_RATE_PARENT, }, };