From patchwork Mon Apr 20 19:08:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499683 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 186EC81 for ; Mon, 20 Apr 2020 19:09:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00B22208FE for ; Mon, 20 Apr 2020 19:09:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AjFvPXB3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725897AbgDTTJW (ORCPT ); Mon, 20 Apr 2020 15:09:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725896AbgDTTJW (ORCPT ); Mon, 20 Apr 2020 15:09:22 -0400 Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDF68C061A0C; Mon, 20 Apr 2020 12:09:21 -0700 (PDT) Received: by mail-wm1-x342.google.com with SMTP id x4so795177wmj.1; Mon, 20 Apr 2020 12:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MryED8uai1n3gclYsGl5qk+GTHUCazZ5O/sEZ7i7aTw=; b=AjFvPXB3NEFW2PxnuZMSlnLdaQZRCuRYUfLf63TlgpoiN4aCakwkGh216tynJP/KPY hCxzvDllrz2vAAo8p8AHIdRZ3HJ3c7T4Qcy/cCcqvMDOiASUmI5IpvPVj1+roqra4CjB 4skiMm+SGw4PvK1V3rvjGeBvvQfjfY1CsPb9Z5nk1qC4iRJl+4m59BHeJ8pEBNoRFjBr SRO40pP73+/JTdzi0ob40DkALMrrLNs5mcR6qtxTQ/zxiPRSY4aYc3HEaqLg1KsVefyC FBhWNKxxzWDP/k60HkT2uzcrI+pLnrJc5eSsvCblxqhpyRZ6cvyongxXXYylXPkV7m5T wCIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MryED8uai1n3gclYsGl5qk+GTHUCazZ5O/sEZ7i7aTw=; b=rAkw4LbkSMhA4VQw6VAom5AK506K9N+bF7qpCYky7xre/lL9M0HcKRvoijqcsWSAFh OiczP83tSN7dGOnamHe0QL68+qvbD9oOBJxyYVZQVVPiXRwy8xgYm0+4/1ykEWn+XpZE WgO/hprowi6kI2UTa8UE4EES3zM7eKPBmSbAYs45y81y+9z1d3UfRdUaMw0QfqszcrR1 0H5JmoHCRHjseimiXejUpuuJ+mxnB+N0TXnM00iFH2NSMaU5aN26NucQxpEvJjkyddwU zhAoSwNEX3yYDsMbXSlf0vziN2m4UPscoF23uRJuNKyYbzv2FZEjnQgJMM9QJXzqwKR8 ZQhg== X-Gm-Message-State: AGi0PuYxnxEcuxxzCXnwcRlBfzFxIom0BwJ/EyAKw3MhMv/UJ0qsk7AZ B2sv2/crA2oT1LqMKeI9R8E= X-Google-Smtp-Source: APiQypLsyKNAgvuWGyKHGw0G7eoRaKGEavFsr5XFrPv90rLPDoF8meIeiXS8YTK3tz3/3UW6G4vYbg== X-Received: by 2002:a1c:1bcb:: with SMTP id b194mr931818wmb.4.1587409760724; Mon, 20 Apr 2020 12:09:20 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:20 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Florian Fainelli , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 1/9] spi: bcm-qspi: Handle clock probe deferral Date: Mon, 20 Apr 2020 15:08:45 -0400 Message-Id: <20200420190853.45614-2-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Florian Fainelli The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional(). Signed-off-by: Florian Fainelli Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 23d295f36c80..74f4579c3f6a 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1222,6 +1222,11 @@ int bcm_qspi_probe(struct platform_device *pdev, } qspi = spi_master_get_devdata(master); + + qspi->clk = devm_clk_get_optional(&pdev->dev, NULL); + if (IS_ERR(qspi->clk)) + return PTR_ERR(qspi->clk); + qspi->pdev = pdev; qspi->trans_pos.trans = NULL; qspi->trans_pos.byte = 0; @@ -1335,13 +1340,6 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->soc_intc = NULL; } - qspi->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(qspi->clk)) { - dev_warn(dev, "unable to get clock\n"); - ret = PTR_ERR(qspi->clk); - goto qspi_probe_err; - } - ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "failed to prepare clock\n"); From patchwork Mon Apr 20 19:08:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DF2171892 for ; Mon, 20 Apr 2020 19:09:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7D0F20857 for ; Mon, 20 Apr 2020 19:09:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BKpBsOGS" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727769AbgDTTJZ (ORCPT ); Mon, 20 Apr 2020 15:09:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725896AbgDTTJY (ORCPT ); Mon, 20 Apr 2020 15:09:24 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE39FC061A0C; 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Mon, 20 Apr 2020 12:09:22 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:22 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Date: Mon, 20 Apr 2020 15:08:46 -0400 Message-Id: <20200420190853.45614-3-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Added documentation for compatibility for brcmstb SoCs : 7425, 7429, 7435, 7216, 7278 Signed-off-by: Kamal Dasu --- .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt index ad7ac80a3841..f5e518d099f2 100644 --- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt @@ -26,6 +26,16 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs From patchwork Mon Apr 20 19:08:47 2020 Content-Type: text/plain; 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Mon, 20 Apr 2020 12:09:24 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:24 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Florian Fainelli , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Date: Mon, 20 Apr 2020 15:08:47 -0400 Message-Id: <20200420190853.45614-4-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Florian Fainelli Older MIPS chips have a QSPI/MSPI controller that does not have the MSPI_REV offset, reading from that offset will cause a bus error. Match their compatible string and do not perform a read from that register in that case. Signed-off-by: Florian Fainelli Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 50 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 74f4579c3f6a..d901dcb10d06 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -91,6 +91,7 @@ #define MSPI_MSPI_STATUS 0x020 #define MSPI_CPTQP 0x024 #define MSPI_SPCR3 0x028 +#define MSPI_REV 0x02c #define MSPI_TXRAM 0x040 #define MSPI_RXRAM 0x0c0 #define MSPI_CDRAM 0x140 @@ -217,6 +218,8 @@ struct bcm_qspi { struct bcm_qspi_dev_id *dev_ids; struct completion mspi_done; struct completion bspi_done; + u8 mspi_maj_rev; + u8 mspi_min_rev; }; static inline bool has_bspi(struct bcm_qspi *qspi) @@ -1190,8 +1193,35 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { .exec_op = bcm_qspi_exec_mem_op, }; +struct bcm_qspi_data { + bool has_mspi_rev; +}; + +static const struct bcm_qspi_data bcm_qspi_no_rev_data = { + .has_mspi_rev = false, +}; + +static const struct bcm_qspi_data bcm_qspi_rev_data = { + .has_mspi_rev = true, +}; + static const struct of_device_id bcm_qspi_of_match[] = { - { .compatible = "brcm,spi-bcm-qspi" }, + { + .compatible = "brcm,spi-bcm7425-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm7429-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm7435-qspi", + .data = &bcm_qspi_no_rev_data, + }, + { + .compatible = "brcm,spi-bcm-qspi", + .data = &bcm_qspi_rev_data, + }, {}, }; MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); @@ -1199,12 +1229,15 @@ MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); int bcm_qspi_probe(struct platform_device *pdev, struct bcm_qspi_soc_intc *soc_intc) { + const struct of_device_id *of_id = NULL; + const struct bcm_qspi_data *data; struct device *dev = &pdev->dev; struct bcm_qspi *qspi; struct spi_master *master; struct resource *res; int irq, ret = 0, num_ints = 0; u32 val; + u32 rev = 0; const char *name = NULL; int num_irqs = ARRAY_SIZE(qspi_irq_tab); @@ -1212,9 +1245,12 @@ int bcm_qspi_probe(struct platform_device *pdev, if (!dev->of_node) return -ENODEV; - if (!of_match_node(bcm_qspi_of_match, dev->of_node)) + of_id = of_match_node(bcm_qspi_of_match, dev->of_node); + if (!of_id) return -ENODEV; + data = of_id->data; + master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); if (!master) { dev_err(dev, "error allocating spi_master\n"); @@ -1349,6 +1385,16 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->base_clk = clk_get_rate(qspi->clk); qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); + if (data->has_mspi_rev) { + rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); + /* some older revs do not have a MSPI_REV register */ + if ((rev & 0xff) == 0xff) + rev = 0; + } + + qspi->mspi_maj_rev = (rev >> 4) & 0xf; + qspi->mspi_min_rev = rev & 0xf; + bcm_qspi_hw_init(qspi); init_completion(&qspi->mspi_done); init_completion(&qspi->bspi_done); From patchwork Mon Apr 20 19:08:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C273181 for ; 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Mon, 20 Apr 2020 12:09:26 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:26 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Date: Mon, 20 Apr 2020 15:08:48 -0400 Message-Id: <20200420190853.45614-5-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As per the spi core implementation for MSPI devices when the transfer is the last one in the message, the chip may stay selected until the next transfer. On multi-device SPI busses with nothing blocking messages going to other devices, this is just a performance hint; starting a message to another device deselects this one. But in other cases, this can be used to ensure correctness. Some devices need protocol transactions to be built from a series of spi_message submissions, where the content of one message is determined by the results of previous messages and where the whole transaction ends when the chipselect goes intactive. On CS change after completing the last serial transfer, the MSPI driver drives SSb pin CDRAM register correctly according comments in core spi.h as shown below: case 1) EOM =1, cs_change =0: SSb inactive case 2) EOM =1, cs_change =1: SSb active case 3) EOM =0, cs_change =0: SSb active case 4) EOM =0, cs_change =1: SSb inactive Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index d901dcb10d06..c48c399dce53 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -615,19 +615,15 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi, if (qt->trans->cs_change && (flags & TRANS_STATUS_BREAK_CS_CHANGE)) ret |= TRANS_STATUS_BREAK_CS_CHANGE; - if (ret) - goto done; - dev_dbg(&qspi->pdev->dev, "advance msg exit\n"); if (bcm_qspi_mspi_transfer_is_last(qspi, qt)) - ret = TRANS_STATUS_BREAK_EOM; + ret |= TRANS_STATUS_BREAK_EOM; else - ret = TRANS_STATUS_BREAK_NO_BYTES; + ret |= TRANS_STATUS_BREAK_NO_BYTES; qt->trans = NULL; } -done: dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n", qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret); return ret; @@ -774,7 +770,16 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); - if (tstatus & TRANS_STATUS_BREAK_DESELECT) { + /* + * case 1) EOM =1, cs_change =0: SSb inactive + * case 2) EOM =1, cs_change =1: SSb stay active + * case 3) EOM =0, cs_change =0: SSb stay active + * case 4) EOM =0, cs_change =1: SSb inactive + */ + if (((tstatus & TRANS_STATUS_BREAK_DESELECT) + == TRANS_STATUS_BREAK_CS_CHANGE) || + ((tstatus & TRANS_STATUS_BREAK_DESELECT) + == TRANS_STATUS_BREAK_EOM)) { mspi_cdram = read_cdram_slot(qspi, slot - 1) & ~MSPI_CDRAM_CONT_BIT; write_cdram_slot(qspi, slot - 1, mspi_cdram); From patchwork Mon Apr 20 19:08:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 07FFC92C for ; Mon, 20 Apr 2020 19:10:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E480520BED for ; Mon, 20 Apr 2020 19:09:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G+XEOCZj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726294AbgDTTJc (ORCPT ); Mon, 20 Apr 2020 15:09:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727914AbgDTTJa (ORCPT ); Mon, 20 Apr 2020 15:09:30 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB1B8C061A0F; Mon, 20 Apr 2020 12:09:29 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id i10so13541264wrv.10; Mon, 20 Apr 2020 12:09:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZyjxQT2w1tfyUymmhQNajH9/aDxm1dT9gvQiJybw7YI=; b=G+XEOCZj6su1PzRZCtoH0nu5WMOzfz2daC0WPumyvY2vQ3IJQ+LjVeT794H6LNT+nV Gg1eJCUkFYRgZKpVb+k3zG40YGui1Nlfs2wvXKpaaPU/Bqp5hrkg6n27afo884ZOE7DW aEomaRd4jCRU92LEWHRhMLJqR+qjO463Q5enhyArFeXbgOWtjk4uODDJKlx4y+1OenRa B+BkMAvWzINLz1nvaB/cUj2uBpd4cUdzicgLVE1BRHr95/v1gWyvbVIbZSqY4AybkI+0 L/AyVS2IcYgVUA+tYtbnJxbPrWhrSaVpycYZXelJEWvS2KdDwYzpZB0mFK3jmKSpb5td kZ2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZyjxQT2w1tfyUymmhQNajH9/aDxm1dT9gvQiJybw7YI=; b=RzzGSuiFeP6C1j1vxn1V8gY5OBuFUSD5w51fL1IEuKC2Lv9YIGPR3RQdrHmiVpENeF hZ5AIV0UmMtG5/QF6CchCQBDyqsw8aLPcwm+nKcloiq8f3PtX6j21WxpfY0LQAFIy147 bVwL1zgqUBrWony7LlBEfgfmLdnHtqnDLbqKCqdXA6n8dCjk8/K0w25JfjiNpXJ/cbb9 jd0xkmc6ylf3CeeV2DyEYKIiz0eKMe4kCIhVne6IhwSfzjM3DXTx19ncr/O6w5zK4WH4 vkv9mtnKA6Zt6zA8joLVenDx0LpXznRfMkS0QbI2MhNeMiI0BqtqQuodV2YmpiqpRixB nn+w== X-Gm-Message-State: AGi0PuYzhuzCFd4zGglam0Lm7jRLXfsezikgaakjvtD6rxoMczwCwvP7 5liz1XWpKLNLtsWHcq1MxIbEAlpovoM= X-Google-Smtp-Source: APiQypI/JiQuMFWECgwhXvwdIgWcJ/osdqQG6/N2n1+wmdAVIYTADeOeMW5EsZDRr/gaT/vSX2twqQ== X-Received: by 2002:adf:cc8d:: with SMTP id p13mr21151345wrj.114.1587409768680; Mon, 20 Apr 2020 12:09:28 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:28 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: Justin Chen , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Date: Mon, 20 Apr 2020 15:08:49 -0400 Message-Id: <20200420190853.45614-6-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Justin Chen Currently we set the tx/rx buffer to 0xff when NULL. This causes problems with some spi slaves where 0xff is a valid command. Looking at other drivers, the tx/rx buffer is usually set to 0x00 when NULL. Following this convention solves the issue. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Justin Chen Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index c48c399dce53..e00208801c8b 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -669,7 +669,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots) if (buf) buf[tp.byte] = read_rxram_slot_u8(qspi, slot); dev_dbg(&qspi->pdev->dev, "RD %02x\n", - buf ? buf[tp.byte] : 0xff); + buf ? buf[tp.byte] : 0x0); } else { u16 *buf = tp.trans->rx_buf; @@ -677,7 +677,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots) buf[tp.byte / 2] = read_rxram_slot_u16(qspi, slot); dev_dbg(&qspi->pdev->dev, "RD %04x\n", - buf ? buf[tp.byte] : 0xffff); + buf ? buf[tp.byte / 2] : 0x0); } update_qspi_trans_byte_count(qspi, &tp, @@ -732,13 +732,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi) while (!tstatus && slot < MSPI_NUM_CDRAM) { if (tp.trans->bits_per_word <= 8) { const u8 *buf = tp.trans->tx_buf; - u8 val = buf ? buf[tp.byte] : 0xff; + u8 val = buf ? buf[tp.byte] : 0x00; write_txram_slot_u8(qspi, slot, val); dev_dbg(&qspi->pdev->dev, "WR %02x\n", val); } else { const u16 *buf = tp.trans->tx_buf; - u16 val = buf ? buf[tp.byte / 2] : 0xffff; + u16 val = buf ? buf[tp.byte / 2] : 0x0000; write_txram_slot_u16(qspi, slot, val); dev_dbg(&qspi->pdev->dev, "WR %04x\n", val); From patchwork Mon Apr 20 19:08:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A57B9913 for ; Mon, 20 Apr 2020 19:09:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BF4D2084D for ; Mon, 20 Apr 2020 19:09:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MA9Hc7It" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727944AbgDTTJd (ORCPT ); Mon, 20 Apr 2020 15:09:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725896AbgDTTJc (ORCPT ); Mon, 20 Apr 2020 15:09:32 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAF49C061A10; Mon, 20 Apr 2020 12:09:31 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id z6so818807wml.2; Mon, 20 Apr 2020 12:09:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jF5s6mIDV3imWHwN3gxECUXiGCch+faubGbjA6qiFuo=; b=MA9Hc7It1IJZS+3VUl8IaZyr9hEDq/mPbwd2Pq14bW3UdHhu3Dabnrqnz0uKE2ACn0 RI4VbmAncJlw5s7+wqp6aqxucd/Lzwu70Zs2RxmHCrMmOhE10y3nfl4lnHk+3AFT3Rlh T6QC/lqivqxOPHLl4kyK0K89R/iPqKz6M0aiphsxPEfi+zYGa55qPoZh8qlHhgmWecuh JhEDEjaFvZgMcT+X8wbdysuG4376TwlrcbdWs9ZT26LfI/m6LwW9YjMojxgbzi/K+dn/ PbisGkgdwDoMXsWyOTQK7I1mgMwHwHcIZ74Wh+vpBtGStJ1r5EydNlwvHBGVuxq1CuYz 584w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jF5s6mIDV3imWHwN3gxECUXiGCch+faubGbjA6qiFuo=; b=jbnpT6awTHD4knoQunGFIWdLhslGiSIaogFQrnjoRSY3XGIj3xAX9rlvYX2BbkRoAY zLqJ+LyKQbL3U6zHeOLdndS3f1UNZpuFcj00++E5FvQX+p6o3FRGglZOyF1rHvraT6sW updKlaaokOAfyx+w4VOJEjHck2kTuvf2okrNBJQl6IwcN1KiLmjvPblRUbVuuaUE0+HN meFtvlF+kB7sOlAwyK00gVt+H754gCdXM9lKjr92STR9ys5dE6bgPi7eWkp725kn6jGH VSbERCWwHbr9abig8PeCUBx8ypnmzkslRSocdg2qIk33FUjSMHEamgtxzOJR1zC/ZePJ qSNw== X-Gm-Message-State: AGi0PuZMxzyXlFz253M5lIyE+q4WesEr0XXPViG307C9tnpDhWN756LD 5ZfXmSS4aOgscw99LUBNHd8= X-Google-Smtp-Source: APiQypLRVea+hlqZbX7g3aJ3ofjkpxEYOpCmtuezTVESJGLwrvrSTxpYQYGNwxv6uiXrQpOstFAbiw== X-Received: by 2002:a05:600c:2941:: with SMTP id n1mr872602wmd.25.1587409770565; Mon, 20 Apr 2020 12:09:30 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:30 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Date: Mon, 20 Apr 2020 15:08:50 -0400 Message-Id: <20200420190853.45614-7-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org SCMI only passes clk_prepare_enable() and clk_disable_unprepare(), made changes to suspend/resume ops to use the appropriate calls so that PM works for ARM and ARM64 platforms. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index e00208801c8b..a3936ae5a860 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1455,7 +1455,7 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev) bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); spi_master_suspend(qspi->master); - clk_disable(qspi->clk); + clk_disable_unprepare(qspi->clk); bcm_qspi_hw_uninit(qspi); return 0; @@ -1473,7 +1473,7 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev) qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE, true); - ret = clk_enable(qspi->clk); + ret = clk_prepare_enable(qspi->clk); if (!ret) spi_master_resume(qspi->master); From patchwork Mon Apr 20 19:08:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499691 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC1A981 for ; Mon, 20 Apr 2020 19:09:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDC8722247 for ; Mon, 20 Apr 2020 19:09:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OMMAVUyB" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727981AbgDTTJf (ORCPT ); Mon, 20 Apr 2020 15:09:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727953AbgDTTJe (ORCPT ); Mon, 20 Apr 2020 15:09:34 -0400 Received: from mail-wr1-x441.google.com (mail-wr1-x441.google.com [IPv6:2a00:1450:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1538CC061A0C; Mon, 20 Apr 2020 12:09:34 -0700 (PDT) Received: by mail-wr1-x441.google.com with SMTP id x18so13609071wrq.2; Mon, 20 Apr 2020 12:09:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OZ96LAcwn+BELPZteh+FF1ZZG0PwSRcuJ8BBRDIlsU=; b=OMMAVUyBDJP+KFHWCoSsdWuf67ugu0h1aOcdG92e9Rk2nRnFxxm2PEp0aAX/tYuOEc wR5AkOMJp+xAsI60sMbTGZ9TAgnE1q9F2huBaA2dkn0XuTdXt5rFo4O0BoVmF9kUFE8e c1S7MVNi0nnK7PzrffD3UtA2lMQNYrJk4L++4FxOx8oGsmfqqtIcjTG4qpXkFOJBKX0Q bAmcvNDlkNlmJJlfDzYJNISNW7kN46xksRSOdy13wIGLvW96Uhs/vbk27z1KgdU1Iidd RjNNQl/iksd/co0em1TIwAOH8xfJZVpPGtRLGHW7/mY3K0tjY5ZPtK1+TlUffGtE77Ig e2Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OZ96LAcwn+BELPZteh+FF1ZZG0PwSRcuJ8BBRDIlsU=; b=ONhCy6M97/tI+hVgN8wX8L3FUTz1JikAd/BCQ2SxB2BqZhV7SWxdGKmea19e0HMDVP aba6xc31wEFledIzIYFicqn6yrrcjJMruiQjXtr8sgGBQ+0lfM9OlUm1p7wsJobAL6zZ 1G7VU3nTQMOQqIQTcvG+UWlxOAcufVbBCnQZH36KXpbVcSwBK9MFCYdqObKjFuv8BwPH NeGujN2bV2U5e5aujIJLvfF4Yzd6eNVS/kNSsLFgY2iwcb7ZPvOPkQ818giCnFWLoT4g wnifX/zmpRWctHTzklVTsEKiZz0kV04pEoF7JkKnNhftKsYTcfAxG140hUx0repl0Hr+ idnA== X-Gm-Message-State: AGi0PuZdx9XQXFp4+j1zQIPt4ysB/P7VnPItOBGb2i7fw/22+18lnwXR 76AF2puqjiS8xf1bjg+sRNg= X-Google-Smtp-Source: APiQypI+/BCVqeRq7QtED9MoxzHJxEBtobaZ5O/7EtxqFKhAxsE2XNO3e80+wWFUCImWNvU6kcfUCw== X-Received: by 2002:a5d:6b89:: with SMTP id n9mr14890993wrx.356.1587409772866; Mon, 20 Apr 2020 12:09:32 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:32 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Date: Mon, 20 Apr 2020 15:08:51 -0400 Message-Id: <20200420190853.45614-8-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of 1-7, while the default value prohibits these values and requires a minimum clock divider value of 8. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index a3936ae5a860..edc601dbf221 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -107,13 +107,15 @@ #define MSPI_SPCR2_SPE BIT(6) #define MSPI_SPCR2_CONT_AFTER_CMD BIT(7) +#define MSPI_SPCR3_FASTBR BIT(0) +#define MSPI_SPCR3_FASTDT BIT(1) + #define MSPI_MSPI_STATUS_SPIF BIT(0) #define INTR_BASE_BIT_SHIFT 0x02 #define INTR_COUNT 0x07 #define NUM_CHIPSELECT 4 -#define QSPI_SPBR_MIN 8U #define QSPI_SPBR_MAX 255U #define OPCODE_DIOR 0xBB @@ -227,6 +229,25 @@ static inline bool has_bspi(struct bcm_qspi *qspi) return qspi->bspi_mode; } +/* hardware supports spcr3 and fast baud-rate */ +static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) +{ + if (!has_bspi(qspi) && + ((qspi->mspi_maj_rev >= 1) && + (qspi->mspi_min_rev >= 5))) + return true; + + return false; +} + +static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) +{ + if (bcm_qspi_has_fastbr(qspi)) + return 1; + else + return 8; +} + /* Read qspi controller register*/ static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type, unsigned int offset) @@ -534,7 +555,7 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, if (xp->speed_hz) spbr = qspi->base_clk / (2 * xp->speed_hz); - spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX); + spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX); bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); spcr = MSPI_MASTER_BIT; @@ -544,6 +565,14 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, spcr |= xp->mode & 3; bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); + if (bcm_qspi_has_fastbr(qspi)) { + spcr = 0; + + /* enable fastbr */ + spcr |= MSPI_SPCR3_FASTBR; + bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); + } + qspi->last_parms = *xp; } @@ -1388,7 +1417,6 @@ int bcm_qspi_probe(struct platform_device *pdev, } qspi->base_clk = clk_get_rate(qspi->clk); - qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); if (data->has_mspi_rev) { rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); @@ -1400,6 +1428,8 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->mspi_maj_rev = (rev >> 4) & 0xf; qspi->mspi_min_rev = rev & 0xf; + qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); + bcm_qspi_hw_init(qspi); init_completion(&qspi->mspi_done); init_completion(&qspi->bspi_done); From patchwork Mon Apr 20 19:08:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499687 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E422B81 for ; Mon, 20 Apr 2020 19:09:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CC95B20857 for ; Mon, 20 Apr 2020 19:09:37 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 20 Apr 2020 12:09:34 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Date: Mon, 20 Apr 2020 15:08:52 -0400 Message-Id: <20200420190853.45614-9-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Adding support for MSPI sys clk 108Mhz available on 7216 and 7278 BRCMSTB SoCs. Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 44 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index edc601dbf221..99f2cfcbb50c 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -109,6 +109,11 @@ #define MSPI_SPCR3_FASTBR BIT(0) #define MSPI_SPCR3_FASTDT BIT(1) +#define MSPI_SPCR3_SYSCLKSEL_MASK GENMASK(11, 10) +#define MSPI_SPCR3_SYSCLKSEL_27 (MSPI_SPCR3_SYSCLKSEL_MASK & \ + ~(BIT(10) | BIT(11))) +#define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \ + BIT(11)) #define MSPI_MSPI_STATUS_SPIF BIT(0) @@ -117,6 +122,7 @@ #define NUM_CHIPSELECT 4 #define QSPI_SPBR_MAX 255U +#define MSPI_BASE_FREQ 27000000UL #define OPCODE_DIOR 0xBB #define OPCODE_QIOR 0xEB @@ -222,6 +228,7 @@ struct bcm_qspi { struct completion bspi_done; u8 mspi_maj_rev; u8 mspi_min_rev; + bool mspi_spcr3_sysclk; }; static inline bool has_bspi(struct bcm_qspi *qspi) @@ -240,6 +247,17 @@ static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) return false; } +/* hardware supports sys clk 108Mhz */ +static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) +{ + if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || + ((qspi->mspi_maj_rev >= 1) && + (qspi->mspi_min_rev >= 6)))) + return true; + + return false; +} + static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi) { if (bcm_qspi_has_fastbr(qspi)) @@ -570,6 +588,15 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, /* enable fastbr */ spcr |= MSPI_SPCR3_FASTBR; + + if (bcm_qspi_has_sysclk_108(qspi)) { + /* SYSCLK_108 */ + spcr |= MSPI_SPCR3_SYSCLKSEL_108; + qspi->base_clk = MSPI_BASE_FREQ * 4; + /* Change spbr as we changed sysclk */ + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4); + } + bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); } @@ -1229,14 +1256,22 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = { struct bcm_qspi_data { bool has_mspi_rev; + bool has_spcr3_sysclk; }; static const struct bcm_qspi_data bcm_qspi_no_rev_data = { .has_mspi_rev = false, + .has_spcr3_sysclk = false, }; static const struct bcm_qspi_data bcm_qspi_rev_data = { .has_mspi_rev = true, + .has_spcr3_sysclk = false, +}; + +static const struct bcm_qspi_data bcm_qspi_spcr3_data = { + .has_mspi_rev = true, + .has_spcr3_sysclk = true, }; static const struct of_device_id bcm_qspi_of_match[] = { @@ -1256,6 +1291,14 @@ static const struct of_device_id bcm_qspi_of_match[] = { .compatible = "brcm,spi-bcm-qspi", .data = &bcm_qspi_rev_data, }, + { + .compatible = "brcm,spi-bcm7216-qspi", + .data = &bcm_qspi_spcr3_data, + }, + { + .compatible = "brcm,spi-bcm7278-qspi", + .data = &bcm_qspi_spcr3_data, + }, {}, }; MODULE_DEVICE_TABLE(of, bcm_qspi_of_match); @@ -1427,6 +1470,7 @@ int bcm_qspi_probe(struct platform_device *pdev, qspi->mspi_maj_rev = (rev >> 4) & 0xf; qspi->mspi_min_rev = rev & 0xf; + qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk; qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); From patchwork Mon Apr 20 19:08:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 11499689 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 04A0781 for ; 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Mon, 20 Apr 2020 12:09:37 -0700 (PDT) Received: from mail.broadcom.com ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id y5sm621251wru.15.2020.04.20.12.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 12:09:36 -0700 (PDT) From: Kamal Dasu To: Kamal Dasu , bcm-kernel-feedback-list@broadcom.com, Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Date: Mon, 20 Apr 2020 15:08:53 -0400 Message-Id: <20200420190853.45614-10-kdasu.kdev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200420190853.45614-1-kdasu.kdev@gmail.com> References: <20200420190853.45614-1-kdasu.kdev@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Kamal Dasu --- drivers/spi/spi-bcm-qspi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 99f2cfcbb50c..681d09085175 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -576,11 +576,17 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi, spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX); bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); - spcr = MSPI_MASTER_BIT; + if (!qspi->mspi_maj_rev) + /* legacy controller */ + spcr = MSPI_MASTER_BIT; + else + spcr = 0; + /* for 16 bit the data should be zero */ if (xp->bits_per_word != 16) spcr |= xp->bits_per_word << 2; spcr |= xp->mode & 3; + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); if (bcm_qspi_has_fastbr(qspi)) {