From patchwork Tue Apr 21 13:21:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501369 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EBCE6CA for ; Tue, 21 Apr 2020 13:23:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56A4120CC7 for ; Tue, 21 Apr 2020 13:23:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726780AbgDUNXl (ORCPT ); Tue, 21 Apr 2020 09:23:41 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2821 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729024AbgDUNXk (ORCPT ); Tue, 21 Apr 2020 09:23:40 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id F152E6FFEFC3FD0F9E6A; Tue, 21 Apr 2020 21:23:35 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:27 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 1/6] ACPI / APEI: Add support to queuing up the non-fatal HW errors and notify Date: Tue, 21 Apr 2020 14:21:31 +0100 Message-ID: <20200421132136.1595-2-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add queuing up the non-fatal HW errors to the work queue and interface to notify the registered kernel drivers for the error recovery. The interface enables drivers to register the callback functions to receive the error notification, including the vendor-specific HW errors and supports handling the non-fatal HW errors in the process context. Suggested-by: Borislav Petkov Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 127 +++++++++++++++++++++++++++++++++++++++ include/acpi/ghes.h | 28 +++++++++ 2 files changed, 155 insertions(+) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 24c9642e8fc7..5c0ab5422311 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -63,6 +64,11 @@ #define GHES_ESTATUS_CACHES_SIZE 4 #define GHES_ESTATUS_IN_CACHE_MAX_NSEC 10000000000ULL + +#define GHES_EVENT_RING_SIZE 256 +#define GHES_GDATA_POOL_MIN_ALLOC_ORDER 3 +#define GHES_GDATA_POOL_MIN_SIZE 65536 + /* Prevent too many caches are allocated because of RCU */ #define GHES_ESTATUS_CACHE_ALLOCED_MAX (GHES_ESTATUS_CACHES_SIZE * 3 / 2) @@ -122,6 +128,19 @@ static DEFINE_MUTEX(ghes_list_mutex); */ static DEFINE_SPINLOCK(ghes_notify_lock_irq); +struct ghes_event_entry { + struct acpi_hest_generic_data *gdata; + int error_severity; +}; + +static DEFINE_KFIFO(ghes_event_ring, struct ghes_event_entry, + GHES_EVENT_RING_SIZE); + +static DEFINE_SPINLOCK(ghes_event_ring_lock); + +static struct gen_pool *ghes_gdata_pool; +static unsigned long ghes_gdata_pool_size_request; + static struct gen_pool *ghes_estatus_pool; static unsigned long ghes_estatus_pool_size_request; @@ -188,6 +207,40 @@ int ghes_estatus_pool_init(int num_ghes) return -ENOMEM; } +int ghes_gdata_pool_init(void) +{ + unsigned long addr, len; + int rc; + + ghes_gdata_pool = gen_pool_create(GHES_GDATA_POOL_MIN_ALLOC_ORDER, -1); + if (!ghes_gdata_pool) + return -ENOMEM; + + if (ghes_gdata_pool_size_request < GHES_GDATA_POOL_MIN_SIZE) + ghes_gdata_pool_size_request = GHES_GDATA_POOL_MIN_SIZE; + + len = ghes_gdata_pool_size_request; + addr = (unsigned long)vmalloc(PAGE_ALIGN(len)); + if (!addr) + goto err_pool_alloc; + + vmalloc_sync_mappings(); + + rc = gen_pool_add(ghes_gdata_pool, addr, PAGE_ALIGN(len), -1); + if (rc) + goto err_pool_add; + + return 0; + +err_pool_add: + vfree((void *)addr); + +err_pool_alloc: + gen_pool_destroy(ghes_gdata_pool); + + return -ENOMEM; +} + static int map_gen_v2(struct ghes *ghes) { return apei_map_generic_address(&ghes->generic_v2->read_ack_register); @@ -247,6 +300,10 @@ static struct ghes *ghes_new(struct acpi_hest_generic *generic) goto err_unmap_status_addr; } + ghes_gdata_pool_size_request += generic->records_to_preallocate * + generic->max_sections_per_record * + generic->max_raw_data_length; + return ghes; err_unmap_status_addr: @@ -490,6 +547,49 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) #endif } +static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); + +/** + * ghes_register_event_notifier - register an event notifier + * for the non-fatal HW errors. + * @nb: pointer to the notifier_block structure of the event handler. + * + * return 0 : SUCCESS, non-zero : FAIL + */ +int ghes_register_event_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&ghes_event_notify_list, nb); +} +EXPORT_SYMBOL_GPL(ghes_register_event_notifier); + +/** + * ghes_unregister_event_notifier - unregister the previously + * registered event notifier. + * @nb: pointer to the notifier_block structure of the event handler. + */ +void ghes_unregister_event_notifier(struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&ghes_event_notify_list, nb); +} +EXPORT_SYMBOL_GPL(ghes_unregister_event_notifier); + +static void ghes_event_work_func(struct work_struct *work) +{ + struct ghes_event_entry entry; + u32 len; + + while (kfifo_get(&ghes_event_ring, &entry)) { + blocking_notifier_call_chain(&ghes_event_notify_list, + entry.error_severity, + entry.gdata); + len = acpi_hest_get_size(entry.gdata) + + acpi_hest_get_error_length(entry.gdata); + gen_pool_free(ghes_gdata_pool, (unsigned long)entry.gdata, len); + } +} + +static DECLARE_WORK(ghes_event_work, ghes_event_work_func); + static void ghes_do_proc(struct ghes *ghes, const struct acpi_hest_generic_status *estatus) { @@ -498,6 +598,8 @@ static void ghes_do_proc(struct ghes *ghes, guid_t *sec_type; const guid_t *fru_id = &guid_null; char *fru_text = ""; + struct ghes_event_entry event_entry; + u32 len; sev = ghes_severity(estatus->error_severity); apei_estatus_for_each_section(estatus, gdata) { @@ -509,6 +611,25 @@ static void ghes_do_proc(struct ghes *ghes, if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT) fru_text = gdata->fru_text; + len = acpi_hest_get_record_size(gdata); + event_entry.gdata = (void *)gen_pool_alloc(ghes_gdata_pool, + len); + if (!event_entry.gdata) { + pr_warn(GHES_PFX "ghes gdata pool alloc fail\n"); + break; + } + + memcpy(event_entry.gdata, gdata, len); + event_entry.error_severity = sev; + + if (kfifo_in_spinlocked(&ghes_event_ring, &event_entry, 1, + &ghes_event_ring_lock)) + schedule_work(&ghes_event_work); + else { + pr_warn(GHES_PFX "ghes event queue full\n"); + break; + } + if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) { struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata); @@ -1346,6 +1467,12 @@ static int __init ghes_init(void) else pr_info(GHES_PFX "Failed to enable APEI firmware first mode.\n"); + rc = ghes_gdata_pool_init(); + if (rc) { + pr_warn(GHES_PFX "ghes_gdata_pool_init failed\n"); + goto err; + } + return 0; err: return rc; diff --git a/include/acpi/ghes.h b/include/acpi/ghes.h index e3f1cddb4ac8..a3dd82069069 100644 --- a/include/acpi/ghes.h +++ b/include/acpi/ghes.h @@ -50,6 +50,34 @@ enum { GHES_SEV_PANIC = 0x3, }; + +#ifdef CONFIG_ACPI_APEI_GHES +/** + * ghes_register_event_notifier - register an event notifier + * for the non-fatal HW errors. + * @nb: pointer to the notifier_block structure of the event notifier. + * + * Return : 0 - SUCCESS, non-zero - FAIL. + */ +int ghes_register_event_notifier(struct notifier_block *nb); + +/** + * ghes_unregister_event_notifier - unregister the previously + * registered event notifier. + * @nb: pointer to the notifier_block structure of the event notifier. + */ +void ghes_unregister_event_notifier(struct notifier_block *nb); +#else +static inline int ghes_register_event_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} + +static inline void ghes_unregister_event_notifier(struct notifier_block *nb) +{ +} +#endif + int ghes_estatus_pool_init(int num_ghes); /* From drivers/edac/ghes_edac.c */ From patchwork Tue Apr 21 13:21:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501361 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9DF666CA for ; Tue, 21 Apr 2020 13:23:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F0852078C for ; Tue, 21 Apr 2020 13:23:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729024AbgDUNXo (ORCPT ); Tue, 21 Apr 2020 09:23:44 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2822 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728864AbgDUNXn (ORCPT ); Tue, 21 Apr 2020 09:23:43 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0F239F6509CB6C65CFB; Tue, 21 Apr 2020 21:23:41 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:34 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 2/6] ACPI / APEI: Add callback for memory errors to the GHES notifier Date: Tue, 21 Apr 2020 14:21:32 +0100 Message-ID: <20200421132136.1595-3-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add callback function for handling the memory errors to the GHES notifier. Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 55 ++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 13 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 5c0ab5422311..053c4a2ed96c 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -471,23 +471,33 @@ static void ghes_clear_estatus(struct ghes *ghes, ghes_ack_error(ghes->generic_v2); } -static void ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata, int sev) +static int ghes_handle_memory_failure(struct notifier_block *nb, + unsigned long event, void *data) { #ifdef CONFIG_ACPI_APEI_MEMORY_FAILURE unsigned long pfn; int flags = -1; + int sev = event; + struct acpi_hest_generic_data *gdata = data; int sec_sev = ghes_severity(gdata->error_severity); struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata); + if (!guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PLATFORM_MEM)) + return NOTIFY_DONE; + + ghes_edac_report_mem_error(sev, mem_err); + + arch_apei_report_mem_error(sev, mem_err); + if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) - return; + return NOTIFY_STOP; pfn = mem_err->physical_addr >> PAGE_SHIFT; if (!pfn_valid(pfn)) { pr_warn_ratelimited(FW_WARN GHES_PFX "Invalid address in generic error data: %#llx\n", mem_err->physical_addr); - return; + return NOTIFY_STOP; } /* iff following two events can be handled properly by now */ @@ -500,6 +510,7 @@ static void ghes_handle_memory_failure(struct acpi_hest_generic_data *gdata, int if (flags != -1) memory_failure_queue(pfn, flags); #endif + return NOTIFY_STOP; } /* @@ -547,6 +558,22 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) #endif } +static struct notifier_block ghes_notifier_mem_error = { + .notifier_call = ghes_handle_memory_failure, +}; + +struct ghes_error_handler_list { + const char *name; + struct notifier_block *nb; +}; + +static const struct ghes_error_handler_list ghes_error_handler_list[] = { + { + .name = "ghes_notifier_mem_error", + .nb = &ghes_notifier_mem_error, + }, +}; + static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); /** @@ -630,15 +657,7 @@ static void ghes_do_proc(struct ghes *ghes, break; } - if (guid_equal(sec_type, &CPER_SEC_PLATFORM_MEM)) { - struct cper_sec_mem_err *mem_err = acpi_hest_get_payload(gdata); - - ghes_edac_report_mem_error(sev, mem_err); - - arch_apei_report_mem_error(sev, mem_err); - ghes_handle_memory_failure(gdata, sev); - } - else if (guid_equal(sec_type, &CPER_SEC_PCIE)) { + if (guid_equal(sec_type, &CPER_SEC_PCIE)) { ghes_handle_aer(gdata); } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { @@ -1431,7 +1450,7 @@ static struct platform_driver ghes_platform_driver = { static int __init ghes_init(void) { - int rc; + int rc, i; if (acpi_disabled) return -ENODEV; @@ -1473,6 +1492,16 @@ static int __init ghes_init(void) goto err; } + for (i = 0; i < ARRAY_SIZE(ghes_error_handler_list); i++) { + const struct ghes_error_handler_list *list = + &ghes_error_handler_list[i]; + rc = ghes_register_event_notifier(list->nb); + if (rc) { + pr_warn(GHES_PFX "fail to register %s\n", list->name); + goto err; + } + } + return 0; err: return rc; From patchwork Tue Apr 21 13:21:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501367 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E88E714B4 for ; Tue, 21 Apr 2020 13:23:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7F1B20CC7 for ; Tue, 21 Apr 2020 13:23:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728904AbgDUNXt (ORCPT ); Tue, 21 Apr 2020 09:23:49 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2823 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728864AbgDUNXt (ORCPT ); Tue, 21 Apr 2020 09:23:49 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 21F483B7C04644112CD7; Tue, 21 Apr 2020 21:23:46 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:39 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 3/6] ACPI / APEI: Add callback for AER to the GHES notifier Date: Tue, 21 Apr 2020 14:21:33 +0100 Message-ID: <20200421132136.1595-4-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add callback function for handling the AER to the GHES notifier. Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 053c4a2ed96c..67ef1742fc93 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -527,11 +527,16 @@ static int ghes_handle_memory_failure(struct notifier_block *nb, * GHES_SEV_PANIC does not make it to this handling since the kernel must * panic. */ -static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) +static int ghes_handle_aer(struct notifier_block *nb, unsigned long event, + void *data) { #ifdef CONFIG_ACPI_APEI_PCIEAER + struct acpi_hest_generic_data *gdata = data; struct cper_sec_pcie *pcie_err = acpi_hest_get_payload(gdata); + if (!guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PCIE)) + return NOTIFY_DONE; + if (pcie_err->validation_bits & CPER_PCIE_VALID_DEVICE_ID && pcie_err->validation_bits & CPER_PCIE_VALID_AER_INFO) { unsigned int devfn; @@ -556,12 +561,17 @@ static void ghes_handle_aer(struct acpi_hest_generic_data *gdata) pcie_err->aer_info); } #endif + return NOTIFY_STOP; } static struct notifier_block ghes_notifier_mem_error = { .notifier_call = ghes_handle_memory_failure, }; +static struct notifier_block ghes_notifier_aer = { + .notifier_call = ghes_handle_aer, +}; + struct ghes_error_handler_list { const char *name; struct notifier_block *nb; @@ -572,6 +582,10 @@ static const struct ghes_error_handler_list ghes_error_handler_list[] = { .name = "ghes_notifier_mem_error", .nb = &ghes_notifier_mem_error, }, + { + .name = "ghes_notifier_aer", + .nb = &ghes_notifier_aer, + }, }; static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); @@ -657,10 +671,7 @@ static void ghes_do_proc(struct ghes *ghes, break; } - if (guid_equal(sec_type, &CPER_SEC_PCIE)) { - ghes_handle_aer(gdata); - } - else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { + if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); log_arm_hw_error(err); From patchwork Tue Apr 21 13:21:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501371 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9952013B2 for ; Tue, 21 Apr 2020 13:24:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8B39721556 for ; Tue, 21 Apr 2020 13:24:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729084AbgDUNYA (ORCPT ); Tue, 21 Apr 2020 09:24:00 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2824 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728864AbgDUNX6 (ORCPT ); Tue, 21 Apr 2020 09:23:58 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3EF206D6AE95EF88C47E; Tue, 21 Apr 2020 21:23:56 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:45 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 4/6] ACPI / APEI: Add callback for ARM HW errors to the GHES notifier Date: Tue, 21 Apr 2020 14:21:34 +0100 Message-ID: <20200421132136.1595-5-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add callback function for handling the ARM HW errors to the GHES notifier. Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 67ef1742fc93..3b89c7621a0d 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -564,6 +564,20 @@ static int ghes_handle_aer(struct notifier_block *nb, unsigned long event, return NOTIFY_STOP; } +static int ghes_handle_arm_hw_error(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct acpi_hest_generic_data *gdata = data; + struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); + + if (!guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PROC_ARM)) + return NOTIFY_DONE; + + log_arm_hw_error(err); + + return NOTIFY_STOP; +} + static struct notifier_block ghes_notifier_mem_error = { .notifier_call = ghes_handle_memory_failure, }; @@ -572,6 +586,10 @@ static struct notifier_block ghes_notifier_aer = { .notifier_call = ghes_handle_aer, }; +static struct notifier_block ghes_notifier_arm_hw_error = { + .notifier_call = ghes_handle_arm_hw_error, +}; + struct ghes_error_handler_list { const char *name; struct notifier_block *nb; @@ -586,6 +604,10 @@ static const struct ghes_error_handler_list ghes_error_handler_list[] = { .name = "ghes_notifier_aer", .nb = &ghes_notifier_aer, }, + { + .name = "ghes_notifier_arm_hw_error", + .nb = &ghes_notifier_arm_hw_error, + }, }; static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); @@ -670,12 +692,7 @@ static void ghes_do_proc(struct ghes *ghes, pr_warn(GHES_PFX "ghes event queue full\n"); break; } - - if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { - struct cper_sec_proc_arm *err = acpi_hest_get_payload(gdata); - - log_arm_hw_error(err); - } else { + { void *err = acpi_hest_get_payload(gdata); log_non_standard_event(sec_type, fru_id, fru_text, From patchwork Tue Apr 21 13:21:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501379 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7257B6CA for ; Tue, 21 Apr 2020 13:24:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 63D6A2084D for ; Tue, 21 Apr 2020 13:24:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729098AbgDUNYF (ORCPT ); Tue, 21 Apr 2020 09:24:05 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2825 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728864AbgDUNYE (ORCPT ); Tue, 21 Apr 2020 09:24:04 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6CF5271FE9D8EE5F270D; Tue, 21 Apr 2020 21:24:01 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:51 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 5/6] ACPI / APEI: Add callback for non-standard HW errors to the GHES notifier Date: Tue, 21 Apr 2020 14:21:35 +0100 Message-ID: <20200421132136.1595-6-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add callback function for the non-standard HW errors to the GHES notifier. Signed-off-by: Shiju Jose --- drivers/acpi/apei/ghes.c | 56 ++++++++++++++++++++++++++-------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 3b89c7621a0d..0c27ea8ea943 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -578,6 +578,34 @@ static int ghes_handle_arm_hw_error(struct notifier_block *nb, return NOTIFY_STOP; } +static int ghes_handle_non_standard_event(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct acpi_hest_generic_data *gdata = data; + void *err = acpi_hest_get_payload(gdata); + int sec_sev; + guid_t *sec_type; + const guid_t *fru_id = &guid_null; + char *fru_text = ""; + + if (guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PLATFORM_MEM) || + guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PCIE) || + guid_equal((guid_t *)gdata->section_type, &CPER_SEC_PROC_ARM)) + return NOTIFY_DONE; + + sec_type = (guid_t *)gdata->section_type; + sec_sev = ghes_severity(gdata->error_severity); + if (gdata->validation_bits & CPER_SEC_VALID_FRU_ID) + fru_id = (guid_t *)gdata->fru_id; + + if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT) + fru_text = gdata->fru_text; + + log_non_standard_event(sec_type, fru_id, fru_text, sec_sev, + err, gdata->error_data_length); + return NOTIFY_OK; +} + static struct notifier_block ghes_notifier_mem_error = { .notifier_call = ghes_handle_memory_failure, }; @@ -590,6 +618,10 @@ static struct notifier_block ghes_notifier_arm_hw_error = { .notifier_call = ghes_handle_arm_hw_error, }; +static struct notifier_block ghes_notifier_non_standard_event = { + .notifier_call = ghes_handle_non_standard_event, +}; + struct ghes_error_handler_list { const char *name; struct notifier_block *nb; @@ -608,6 +640,10 @@ static const struct ghes_error_handler_list ghes_error_handler_list[] = { .name = "ghes_notifier_arm_hw_error", .nb = &ghes_notifier_arm_hw_error, }, + { + .name = "ghes_notifier_non_standard_event", + .nb = &ghes_notifier_non_standard_event, + }, }; static BLOCKING_NOTIFIER_HEAD(ghes_event_notify_list); @@ -656,24 +692,13 @@ static DECLARE_WORK(ghes_event_work, ghes_event_work_func); static void ghes_do_proc(struct ghes *ghes, const struct acpi_hest_generic_status *estatus) { - int sev, sec_sev; + int sev; struct acpi_hest_generic_data *gdata; - guid_t *sec_type; - const guid_t *fru_id = &guid_null; - char *fru_text = ""; struct ghes_event_entry event_entry; u32 len; sev = ghes_severity(estatus->error_severity); apei_estatus_for_each_section(estatus, gdata) { - sec_type = (guid_t *)gdata->section_type; - sec_sev = ghes_severity(gdata->error_severity); - if (gdata->validation_bits & CPER_SEC_VALID_FRU_ID) - fru_id = (guid_t *)gdata->fru_id; - - if (gdata->validation_bits & CPER_SEC_VALID_FRU_TEXT) - fru_text = gdata->fru_text; - len = acpi_hest_get_record_size(gdata); event_entry.gdata = (void *)gen_pool_alloc(ghes_gdata_pool, len); @@ -692,13 +717,6 @@ static void ghes_do_proc(struct ghes *ghes, pr_warn(GHES_PFX "ghes event queue full\n"); break; } - { - void *err = acpi_hest_get_payload(gdata); - - log_non_standard_event(sec_type, fru_id, fru_text, - sec_sev, err, - gdata->error_data_length); - } } } From patchwork Tue Apr 21 13:21:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiju Jose X-Patchwork-Id: 11501381 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE4086CA for ; Tue, 21 Apr 2020 13:24:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7136208E4 for ; Tue, 21 Apr 2020 13:24:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729127AbgDUNYR (ORCPT ); Tue, 21 Apr 2020 09:24:17 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2862 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1729116AbgDUNYJ (ORCPT ); Tue, 21 Apr 2020 09:24:09 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 60FDE7DE4715E0B517C6; Tue, 21 Apr 2020 21:24:06 +0800 (CST) Received: from DESKTOP-6T4S3DQ.china.huawei.com (10.47.83.77) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Tue, 21 Apr 2020 21:23:56 +0800 From: Shiju Jose To: , , , , , , , , , , , , CC: , , , , Shiju Jose Subject: [RESEND PATCH v7 6/6] PCI: hip: Add handling of HiSilicon HIP PCIe controller errors Date: Tue, 21 Apr 2020 14:21:36 +0100 Message-ID: <20200421132136.1595-7-shiju.jose@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200421132136.1595-1-shiju.jose@huawei.com> References: <20200421132136.1595-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.77] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Yicong Yang The HiSilicon HIP PCIe controller is capable of handling errors on root port and perform port reset separately at each root port. Add error handling driver for HIP PCIe controller to log and report recoverable errors. Perform root port reset and restore link status after the recovery. Following are some of the PCIe controller's recoverable errors 1. completion transmission timeout error. 2. CRS retry counter over the threshold error. 3. ECC 2 bit errors 4. AXI bresponse/rresponse errors etc. The driver placed in the drivers/pci/controller/ because the HIP PCIe controller does not use DWC ip. Signed-off-by: Yicong Yang Signed-off-by: Shiju Jose --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 336 +++++++++++++++++++++++++++++++ 3 files changed, 345 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c --- drivers/pci/controller/Kconfig | 8 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-hisi-error.c | 323 +++++++++++++++++++++++ 3 files changed, 332 insertions(+) create mode 100644 drivers/pci/controller/pcie-hisi-error.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 20bf00f587bd..8bc6111480c8 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -268,6 +268,14 @@ config PCI_HYPERV_INTERFACE The Hyper-V PCI Interface is a helper driver allows other drivers to have a common interface with the Hyper-V PCI frontend driver. +config PCIE_HISI_ERR + depends on ARM64 || COMPILE_TEST + depends on ACPI + bool "HiSilicon HIP PCIe controller error handling driver" + help + Say Y here if you want error handling support + for the PCIe controller's errors on HiSilicon HIP SoCs + source "drivers/pci/controller/dwc/Kconfig" source "drivers/pci/controller/cadence/Kconfig" endmenu diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index 01b2502a5323..94f37b3d9929 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o +obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff --git a/drivers/pci/controller/pcie-hisi-error.c b/drivers/pci/controller/pcie-hisi-error.c new file mode 100644 index 000000000000..cc721070e07b --- /dev/null +++ b/drivers/pci/controller/pcie-hisi-error.c @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for handling the PCIe controller errors on + * HiSilicon HIP SoCs. + * + * Copyright (c) 2018-2019 HiSilicon Limited. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define HISI_PCIE_ERR_INFO_SIZE 1024 + +/* HISI PCIe controller error definitions */ +#define HISI_PCIE_ERR_MISC_REGS 33 + +#define HISI_PCIE_SUB_MODULE_ID_AP 0 +#define HISI_PCIE_SUB_MODULE_ID_TL 1 +#define HISI_PCIE_SUB_MODULE_ID_MAC 2 +#define HISI_PCIE_SUB_MODULE_ID_DL 3 +#define HISI_PCIE_SUB_MODULE_ID_SDI 4 + +#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0) +#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1) +#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2) +#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3) +#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4) +#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5) +#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6) +#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7) +#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8) +#define HISI_PCIE_LOCAL_VALID_ERR_MISC 9 + +#define HISI_ERR_SEV_RECOVERABLE 0 +#define HISI_ERR_SEV_FATAL 1 +#define HISI_ERR_SEV_CORRECTED 2 +#define HISI_ERR_SEV_NONE 3 + +static guid_t hisi_pcie_sec_type = GUID_INIT(0xB2889FC9, 0xE7D7, 0x4F9D, + 0xA8, 0x67, 0xAF, 0x42, 0xE9, 0x8B, 0xE7, 0x72); + +#define HISI_PCIE_CORE_ID(v) ((v) >> 3) +#define HISI_PCIE_PORT_ID(core, v) (((v) >> 1) + ((core) << 3)) +#define HISI_PCIE_CORE_PORT_ID(v) (((v) % 8) << 1) + +struct hisi_pcie_error_data { + u64 val_bits; + u8 version; + u8 soc_id; + u8 socket_id; + u8 nimbus_id; + u8 sub_module_id; + u8 core_id; + u8 port_id; + u8 err_severity; + u16 err_type; + u8 reserv[2]; + u32 err_misc[HISI_PCIE_ERR_MISC_REGS]; +}; + +struct hisi_pcie_error_private { + struct notifier_block nb; + struct platform_device *pdev; +}; + +static char *hisi_pcie_sub_module_name(u8 id) +{ + switch (id) { + case HISI_PCIE_SUB_MODULE_ID_AP: return "AP Layer"; + case HISI_PCIE_SUB_MODULE_ID_TL: return "TL Layer"; + case HISI_PCIE_SUB_MODULE_ID_MAC: return "MAC Layer"; + case HISI_PCIE_SUB_MODULE_ID_DL: return "DL Layer"; + case HISI_PCIE_SUB_MODULE_ID_SDI: return "SDI Layer"; + } + + return "unknown"; +} + +static char *hisi_pcie_error_severity(u8 err_sev) +{ + switch (err_sev) { + case HISI_ERR_SEV_RECOVERABLE: return "recoverable"; + case HISI_ERR_SEV_FATAL: return "fatal"; + case HISI_ERR_SEV_CORRECTED: return "corrected"; + case HISI_ERR_SEV_NONE: return "none"; + } + + return "unknown"; +} + +static int hisi_pcie_port_reset(struct platform_device *pdev, + u32 chip_id, u32 port_id) +{ + struct device *dev = &pdev->dev; + acpi_handle handle = ACPI_HANDLE(dev); + union acpi_object arg[3]; + struct acpi_object_list arg_list; + acpi_status s; + unsigned long long data = 0; + + arg[0].type = ACPI_TYPE_INTEGER; + arg[0].integer.value = chip_id; + arg[1].type = ACPI_TYPE_INTEGER; + arg[1].integer.value = HISI_PCIE_CORE_ID(port_id); + arg[2].type = ACPI_TYPE_INTEGER; + arg[2].integer.value = HISI_PCIE_CORE_PORT_ID(port_id); + + arg_list.count = 3; + arg_list.pointer = arg; + + s = acpi_evaluate_integer(handle, "RST", &arg_list, &data); + if (ACPI_FAILURE(s)) { + dev_err(dev, "No RST method\n"); + return -EIO; + } + + if (data) { + dev_err(dev, "Failed to Reset\n"); + return -EIO; + } + + return 0; +} + +static int hisi_pcie_port_do_recovery(struct platform_device *dev, + u32 chip_id, u32 port_id) +{ + acpi_status s; + struct device *device = &dev->dev; + acpi_handle root_handle = ACPI_HANDLE(device); + struct acpi_pci_root *pci_root; + struct pci_bus *root_bus; + struct pci_dev *pdev; + u32 domain, busnr, devfn; + + s = acpi_get_parent(root_handle, &root_handle); + if (ACPI_FAILURE(s)) + return -ENODEV; + pci_root = acpi_pci_find_root(root_handle); + if (!pci_root) + return -ENODEV; + root_bus = pci_root->bus; + domain = pci_root->segment; + + busnr = root_bus->number; + devfn = PCI_DEVFN(port_id, 0); + pdev = pci_get_domain_bus_and_slot(domain, busnr, devfn); + if (!pdev) { + dev_info(device, "Fail to get root port %04x:%02x:%02x.%d device\n", + domain, busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); + return -ENODEV; + } + + pci_stop_and_remove_bus_device_locked(pdev); + pci_dev_put(pdev); + + if (hisi_pcie_port_reset(dev, chip_id, port_id)) + return -EIO; + + /* + * The initialization time of subordinate devices after + * hot reset is no more than 1s, which is required by + * the PCI spec v5.0 sec 6.6.1. The time will shorten + * if Readiness Notifications mechanisms are used. But + * wait 1s here to adapt any conditions. + */ + ssleep(1UL); + + /* add root port and downstream devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(root_bus); + pci_unlock_rescan_remove(); + + return 0; +} + +static void hisi_pcie_handle_error(const struct hisi_pcie_error_data *error, + struct platform_device *pdev) +{ + char buf[HISI_PCIE_ERR_INFO_SIZE]; + char *p = buf, *end = buf + sizeof(buf); + struct device *dev = &pdev->dev; + u32 i; + int rc; + + if (error->val_bits == 0) { + dev_warn(dev, "%s: no valid error information\n", __func__); + return; + } + + /* Logging */ + p += snprintf(p, end - p, "[ Table version=%d ", error->version); + if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID) + p += snprintf(p, end - p, "SOC ID=%d ", error->soc_id); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID) + p += snprintf(p, end - p, "socket ID=%d ", error->socket_id); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID) + p += snprintf(p, end - p, "nimbus ID=%d ", error->nimbus_id); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID) + p += snprintf(p, end - p, "sub module=%s ", + hisi_pcie_sub_module_name(error->sub_module_id)); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID) + p += snprintf(p, end - p, "core ID=core%d ", error->core_id); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID) + p += snprintf(p, end - p, "port ID=port%d ", error->port_id); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY) + p += snprintf(p, end - p, "error severity=%s ", + hisi_pcie_error_severity(error->err_severity)); + + if (error->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE) + p += snprintf(p, end - p, "error type=0x%x ", error->err_type); + + p += snprintf(p, end - p, "]\n"); + dev_info(dev, "\nHISI : HIP : PCIe controller error\n"); + dev_info(dev, "%s\n", buf); + + dev_info(dev, "Reg Dump:\n"); + for (i = 0; i < HISI_PCIE_ERR_MISC_REGS; i++) { + if (error->val_bits & + BIT_ULL(HISI_PCIE_LOCAL_VALID_ERR_MISC + i)) + dev_info(dev, + "ERR_MISC_%d=0x%x\n", i, error->err_misc[i]); + } + + /* Recovery for the PCIe controller errors */ + if (error->err_severity == HISI_ERR_SEV_RECOVERABLE) { + /* try reset PCI port for the error recovery */ + rc = hisi_pcie_port_do_recovery(pdev, error->socket_id, + HISI_PCIE_PORT_ID(error->core_id, error->port_id)); + if (rc) { + dev_info(dev, "fail to do hisi pcie port reset\n"); + return; + } + } +} + +static int hisi_pcie_notify_error(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct acpi_hest_generic_data *gdata = data; + const struct hisi_pcie_error_data *error_data = + acpi_hest_get_payload(gdata); + struct hisi_pcie_error_private *priv = + container_of(nb, struct hisi_pcie_error_private, nb); + struct platform_device *pdev = priv->pdev; + struct device *dev = &pdev->dev; + u8 socket; + + if (device_property_read_u8(dev, "socket", &socket)) + return NOTIFY_DONE; + + if (!guid_equal((guid_t *)gdata->section_type, &hisi_pcie_sec_type) || + error_data->socket_id != socket) + return NOTIFY_DONE; + + hisi_pcie_handle_error(error_data, pdev); + + return NOTIFY_OK; +} + +static int hisi_pcie_error_handler_probe(struct platform_device *pdev) +{ + struct hisi_pcie_error_private *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->nb.notifier_call = hisi_pcie_notify_error; + priv->pdev = pdev; + ret = ghes_register_event_notifier(&priv->nb); + if (ret) { + dev_err(&pdev->dev, "%s : ghes_register_event_notifier fail\n", + __func__); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int hisi_pcie_error_handler_remove(struct platform_device *pdev) +{ + struct hisi_pcie_error_private *priv = platform_get_drvdata(pdev); + + if (priv) + ghes_unregister_event_notifier(&priv->nb); + + kfree(priv); + + return 0; +} + +static const struct acpi_device_id hisi_pcie_acpi_match[] = { + { "HISI0361", 0 }, + { } +}; + +static struct platform_driver hisi_pcie_error_handler_driver = { + .driver = { + .name = "hisi-pcie-error-handler", + .acpi_match_table = hisi_pcie_acpi_match, + }, + .probe = hisi_pcie_error_handler_probe, + .remove = hisi_pcie_error_handler_remove, +}; +module_platform_driver(hisi_pcie_error_handler_driver); + +MODULE_DESCRIPTION("HiSilicon HIP PCIe controller error handling driver"); +MODULE_LICENSE("GPL v2");