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[76.210.143.223]) by smtp.gmail.com with ESMTPSA id y187sm3193810pfg.16.2020.04.21.12.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 12:19:21 -0700 (PDT) Subject: [PULL] RISC-V Patches for 5.0-rc4 Date: Tue, 21 Apr 2020 12:09:55 -0700 Message-Id: <20200421191001.92644-1-palmerdabbelt@google.com> X-Mailer: git-send-email 2.26.1.301.g55bc3eb7cb9-goog MIME-Version: 1.0 Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org From: Palmer Dabbelt To: Peter Maydell Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=palmerdabbelt@google.com; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 20038cd7a8412feeb49c01f6ede89e36c8995472: Update version for v5.0.0-rc3 release (2020-04-15 20:51:54 +0100) are available in the Git repository at: git@github.com:palmer-dabbelt/qemu.git tags/riscv-for-master-5.0-rc4 for you to fetch changes up to 8a7ce6ac908a8ef30d6a81fe8334c3c942670949: riscv/sifive_u: Add a serial property to the sifive_u machine (2020-04-21 10:54:59 -0700) ---------------------------------------------------------------- RISC-V Patches for 5.0-rc4 This contains handful of patches that I'd like to target for 5.0. I know it's a bit late, I thought I'd already sent these out but must have managed to miss doing so. The patches include: * A handful of fixes to PTE lookups related to H-mode support. * The addition of a serial number fo the SiFive U implementetaion, which allows bootloaders to generate a sane MAC address. These pass "make check" and boot Linux for me. ---------------------------------------------------------------- Peter: Sorry I dropped the ball here. I can understand if it's too late for 5.0, but if there's still going to be an rc4 then I'd love to have these included. ---------------------------------------------------------------- Alistair Francis (5): target/riscv: Don't set write permissions on dirty PTEs riscv: Don't use stage-2 PTE lookup protection flags riscv: AND stage-1 and stage-2 protection flags riscv/sifive_u: Fix up file ordering riscv/sifive_u: Add a serial property to the sifive_u SoC Bin Meng (1): riscv/sifive_u: Add a serial property to the sifive_u machine hw/riscv/sifive_u.c | 137 ++++++++++++++++++++++++++------------------ include/hw/riscv/sifive_u.h | 3 + target/riscv/cpu_helper.c | 17 +++--- 3 files changed, 94 insertions(+), 63 deletions(-)