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Sat, 25 Apr 2020 12:05:11 -0700 (PDT) Date: Sun, 26 Apr 2020 00:35:02 +0530 From: Syed Nayyar Waris To: akpm@linux-foundation.org Subject: [PATCH v2 3/6] gpio: thermal: Utilize for_each_set_clump macro Message-ID: <66296904e2ffce670c14576dfc7ea56417c670ab.1587840668.git.syednwaris@gmail.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200425_120512_455784_38A86004 X-CRM114-Status: GOOD ( 14.47 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1043 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [syednwaris[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: amit.kucheria@verdurent.com, yamada.masahiro@socionext.com, linus.walleij@linaro.org, daniel.lezcano@linaro.org, vilhelm.gray@gmail.com, linux-kernel@vger.kernel.org, bgolaszewski@baylibre.com, linux-gpio@vger.kernel.org, linux-pm@vger.kernel.org, rui.zhang@intel.com, andriy.shevchenko@linux.intel.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch replaces all the existing for_each_set_clump8 and related function calls in the drivers (gpio and thermal) with the equivalent new generic for_each_set_clump macro. Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Masahiro Yamada Cc: Zhang Rui Cc: Daniel Lezcano Cc: Amit Kucheria Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v2: - No change. drivers/gpio/gpio-104-dio-48e.c | 8 ++++---- drivers/gpio/gpio-104-idi-48.c | 4 ++-- drivers/gpio/gpio-74x164.c | 4 ++-- drivers/gpio/gpio-gpio-mm.c | 8 ++++---- drivers/gpio/gpio-max3191x.c | 4 ++-- drivers/gpio/gpio-pca953x.c | 4 ++-- drivers/gpio/gpio-pci-idio-16.c | 8 ++++---- drivers/gpio/gpio-pcie-idio-24.c | 8 ++++---- drivers/gpio/gpio-pisosr.c | 4 ++-- drivers/gpio/gpio-uniphier.c | 4 ++-- drivers/gpio/gpio-ws16c48.c | 8 ++++---- drivers/thermal/intel/intel_soc_dts_iosf.c | 6 +++--- 12 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48e.c index 1f7d9bb..60f0383 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -192,11 +192,11 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { port_addr = dio48egpio->base + ports[offset / 8]; port_state = inb(port_addr) & gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; @@ -233,11 +233,11 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *chip, unsigned long bitmask; unsigned long flags; - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { index = offset / 8; port_addr = dio48egpio->base + ports[index]; - bitmask = bitmap_get_value8(bits, offset) & gpio_mask; + bitmask = bitmap_get_value(bits, offset, 8) & gpio_mask; raw_spin_lock_irqsave(&dio48egpio->lock, flags); diff --git a/drivers/gpio/gpio-104-idi-48.c b/drivers/gpio/gpio-104-idi-48.c index d350ac0..03553a31 100644 --- a/drivers/gpio/gpio-104-idi-48.c +++ b/drivers/gpio/gpio-104-idi-48.c @@ -94,11 +94,11 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { port_addr = idi48gpio->base + ports[offset / 8]; port_state = inb(port_addr) & gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; diff --git a/drivers/gpio/gpio-74x164.c b/drivers/gpio/gpio-74x164.c index 05637d5..a836433 100644 --- a/drivers/gpio/gpio-74x164.c +++ b/drivers/gpio/gpio-74x164.c @@ -79,9 +79,9 @@ static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long bitmask; mutex_lock(&chip->lock); - for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { + for_each_set_clump(offset, bankmask, mask, chip->registers * 8, 8) { bank = chip->registers - 1 - offset / 8; - bitmask = bitmap_get_value8(bits, offset) & bankmask; + bitmask = bitmap_get_value(bits, offset, 8) & bankmask; chip->buffer[bank] &= ~bankmask; chip->buffer[bank] |= bitmask; diff --git a/drivers/gpio/gpio-gpio-mm.c b/drivers/gpio/gpio-gpio-mm.c index b89b8c5..5790bb7 100644 --- a/drivers/gpio/gpio-gpio-mm.c +++ b/drivers/gpio/gpio-gpio-mm.c @@ -181,11 +181,11 @@ static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { port_addr = gpiommgpio->base + ports[offset / 8]; port_state = inb(port_addr) & gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; @@ -223,11 +223,11 @@ static void gpiomm_gpio_set_multiple(struct gpio_chip *chip, unsigned long bitmask; unsigned long flags; - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { index = offset / 8; port_addr = gpiommgpio->base + ports[index]; - bitmask = bitmap_get_value8(bits, offset) & gpio_mask; + bitmask = bitmap_get_value(bits, offset, 8) & gpio_mask; spin_lock_irqsave(&gpiommgpio->lock, flags); diff --git a/drivers/gpio/gpio-max3191x.c b/drivers/gpio/gpio-max3191x.c index 310d1a2..e59f09b 100644 --- a/drivers/gpio/gpio-max3191x.c +++ b/drivers/gpio/gpio-max3191x.c @@ -245,7 +245,7 @@ static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask, goto out_unlock; bitmap_zero(bits, gpio->ngpio); - for_each_set_clump8(bit, gpio_mask, mask, gpio->ngpio) { + for_each_set_clump(bit, gpio_mask, mask, gpio->ngpio, 8) { unsigned int chipnum = bit / MAX3191X_NGPIO; if (max3191x_chip_is_faulting(max3191x, chipnum)) { @@ -255,7 +255,7 @@ static int max3191x_get_multiple(struct gpio_chip *gpio, unsigned long *mask, in = ((u8 *)max3191x->xfer.rx_buf)[chipnum * wordlen]; in &= gpio_mask; - bitmap_set_value8(bits, in, bit); + bitmap_set_value(bits, in, bit, 8); } out_unlock: diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 60ae18e..c1bc8fa 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -343,7 +343,7 @@ static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long int i, ret; for (i = 0; i < NBANK(chip); i++) - value[i] = bitmap_get_value8(val, i * BANK_SZ); + value[i] = bitmap_get_value(val, i * BANK_SZ, 8); ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); if (ret < 0) { @@ -367,7 +367,7 @@ static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long * } for (i = 0; i < NBANK(chip); i++) - bitmap_set_value8(val, value[i], i * BANK_SZ); + bitmap_set_value(val, value[i], i * BANK_SZ, 8); return 0; } diff --git a/drivers/gpio/gpio-pci-idio-16.c b/drivers/gpio/gpio-pci-idio-16.c index 638d665..f970756 100644 --- a/drivers/gpio/gpio-pci-idio-16.c +++ b/drivers/gpio/gpio-pci-idio-16.c @@ -112,11 +112,11 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *chip, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { port_addr = ports[offset / 8]; port_state = ioread8(port_addr) & gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; @@ -167,11 +167,11 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip, unsigned long flags; unsigned long out_state; - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { index = offset / 8; port_addr = ports[index]; - bitmask = bitmap_get_value8(bits, offset) & gpio_mask; + bitmask = bitmap_get_value(bits, offset, 8) & gpio_mask; raw_spin_lock_irqsave(&idio16gpio->lock, flags); diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c index 1d47579..be5cb13 100644 --- a/drivers/gpio/gpio-pcie-idio-24.c +++ b/drivers/gpio/gpio-pcie-idio-24.c @@ -215,7 +215,7 @@ static int idio_24_gpio_get_multiple(struct gpio_chip *chip, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { index = offset / 8; /* read bits from current gpio port (port 6 is TTL GPIO) */ @@ -228,7 +228,7 @@ static int idio_24_gpio_get_multiple(struct gpio_chip *chip, port_state &= gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; @@ -291,10 +291,10 @@ static void idio_24_gpio_set_multiple(struct gpio_chip *chip, unsigned long out_state; const unsigned long out_mode_mask = BIT(1); - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { + for_each_set_clump(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8, 8) { index = offset / 8; - bitmask = bitmap_get_value8(bits, offset) & gpio_mask; + bitmask = bitmap_get_value(bits, offset, 8) & gpio_mask; raw_spin_lock_irqsave(&idio24gpio->lock, flags); diff --git a/drivers/gpio/gpio-pisosr.c b/drivers/gpio/gpio-pisosr.c index 6698fea..5c9c73c 100644 --- a/drivers/gpio/gpio-pisosr.c +++ b/drivers/gpio/gpio-pisosr.c @@ -103,9 +103,9 @@ static int pisosr_gpio_get_multiple(struct gpio_chip *chip, pisosr_gpio_refresh(gpio); bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { + for_each_set_clump(offset, gpio_mask, mask, chip->ngpio, 8) { buffer_state = gpio->buffer[offset / 8] & gpio_mask; - bitmap_set_value8(bits, buffer_state, offset); + bitmap_set_value(bits, buffer_state, offset, 8); } return 0; diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index f99f3c1..47738d8 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -149,9 +149,9 @@ static void uniphier_gpio_set_multiple(struct gpio_chip *chip, { unsigned long i, bank, bank_mask, bank_bits; - for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { + for_each_set_clump(i, bank_mask, mask, chip->ngpio, UNIPHIER_GPIO_LINES_PER_BANK) { bank = i / UNIPHIER_GPIO_LINES_PER_BANK; - bank_bits = bitmap_get_value8(bits, i); + bank_bits = bitmap_get_value(bits, i, UNIPHIER_GPIO_LINES_PER_BANK); uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, bank_mask, bank_bits); diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c index cb510df..87b532c 100644 --- a/drivers/gpio/gpio-ws16c48.c +++ b/drivers/gpio/gpio-ws16c48.c @@ -137,11 +137,11 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, /* clear bits array to a clean slate */ bitmap_zero(bits, chip->ngpio); - for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { + for_each_set_clump(offset, gpio_mask, mask, chip->ngpio, 8) { port_addr = ws16c48gpio->base + offset / 8; port_state = inb(port_addr) & gpio_mask; - bitmap_set_value8(bits, port_state, offset); + bitmap_set_value(bits, port_state, offset, 8); } return 0; @@ -182,13 +182,13 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, unsigned long bitmask; unsigned long flags; - for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { + for_each_set_clump(offset, gpio_mask, mask, chip->ngpio, 8) { index = offset / 8; port_addr = ws16c48gpio->base + index; /* mask out GPIO configured for input */ gpio_mask &= ~ws16c48gpio->io_state[index]; - bitmask = bitmap_get_value8(bits, offset) & gpio_mask; + bitmask = bitmap_get_value(bits, offset, 8) & gpio_mask; raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); diff --git a/drivers/thermal/intel/intel_soc_dts_iosf.c b/drivers/thermal/intel/intel_soc_dts_iosf.c index f75271b..39b6305 100644 --- a/drivers/thermal/intel/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel/intel_soc_dts_iosf.c @@ -123,7 +123,7 @@ static int update_trip_temp(struct intel_soc_dts_sensor_entry *dts, return status; update_ptps = store_ptps; - bitmap_set_value8(&update_ptps, temp_out & 0xFF, thres_index * 8); + bitmap_set_value(&update_ptps, temp_out & 0xFF, thres_index * 8, 8); out = update_ptps; status = iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, @@ -237,7 +237,7 @@ static int sys_get_curr_temp(struct thermal_zone_device *tzd, return status; raw = out; - out = bitmap_get_value8(&raw, dts->id * 8) - SOC_DTS_TJMAX_ENCODING; + out = bitmap_get_value(&raw, dts->id * 8, 8) - SOC_DTS_TJMAX_ENCODING; *temp = sensors->tj_max - out * 1000; return 0; @@ -314,7 +314,7 @@ static int add_dts_thermal_zone(int id, struct intel_soc_dts_sensor_entry *dts, trip_mask = 0; else { ptps = store_ptps; - for_each_set_clump8(i, trip, &ptps, writable_trip_cnt * 8) + for_each_set_clump(i, trip, &ptps, writable_trip_cnt * 8, 8) trip_mask &= ~BIT(i / 8); } dts->trip_mask = trip_mask; From patchwork Sat Apr 25 19:06:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 11510031 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EC6971392 for ; Sat, 25 Apr 2020 19:07:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCA4D2074F for ; Sat, 25 Apr 2020 19:07:13 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Sat, 25 Apr 2020 12:07:06 -0700 (PDT) Received: from syed ([106.223.101.50]) by smtp.gmail.com with ESMTPSA id q63sm8501398pfb.178.2020.04.25.12.07.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 25 Apr 2020 12:07:06 -0700 (PDT) Date: Sun, 26 Apr 2020 00:36:59 +0530 From: Syed Nayyar Waris To: akpm@linux-foundation.org Subject: [PATCH v2 6/6] gpio: xilinx: Utilize for_each_set_clump macro Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200425_120707_178349_2451BDE9 X-CRM114-Status: GOOD ( 15.29 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1041 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [syednwaris[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, vilhelm.gray@gmail.com, michal.simek@xilinx.com, bgolaszewski@baylibre.com, andriy.shevchenko@linux.intel.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch reimplements the xgpio_set_multiple function in drivers/gpio/gpio-xilinx.c to use the new for_each_set_clump macro. Instead of looping for each bit in xgpio_set_multiple function, now we can check each channel at a time and save cycles. Cc: Linus Walleij Cc: Bartosz Golaszewski Cc: Michal Simek Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v2: - No change. drivers/gpio/gpio-xilinx.c | 64 ++++++++++++++++++++++++---------------------- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 67f9f82..428207f 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -136,39 +136,43 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - unsigned long flags; + unsigned long flags[2]; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; - - spin_lock_irqsave(&chip->gpio_lock[index], flags); - - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock[index], flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } + u32 *const state = chip->gpio_state; + unsigned int *const width = chip->gpio_width; + const unsigned long state_size = BITS_PER_TYPE(*state); + unsigned long offset, clump; + size_t index; + +#define TOTAL_BITS BITS_PER_TYPE(chip->gpio_state) + DECLARE_BITMAP(old, TOTAL_BITS); + DECLARE_BITMAP(new, TOTAL_BITS); + DECLARE_BITMAP(changed, TOTAL_BITS); + + spin_lock_irqsave(&chip->gpio_lock[0], flags[0]); + spin_lock_irqsave(&chip->gpio_lock[1], flags[1]); + + bitmap_set_value(old, state[0], 0, width[0]); + bitmap_set_value(old, state[1], width[0], width[1]); + bitmap_replace(new, old, bits, mask, gc->ngpio); + + bitmap_set_value(old, state[0], 0, state_size); + bitmap_set_value(old, state[1], state_size, state_size); + state[0] = bitmap_get_value(new, 0, width[0]); + state[1] = bitmap_get_value(new, width[0], width[1]); + bitmap_set_value(new, state[0], 0, state_size); + bitmap_set_value(new, state[1], state_size, state_size); + bitmap_xor(changed, old, new, TOTAL_BITS); + + for_each_set_clump(offset, clump, changed, TOTAL_BITS, state_size) { + index = offset / state_size; + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + + index * XGPIO_CHANNEL_OFFSET, + state[index]); } - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + spin_unlock_irqrestore(&chip->gpio_lock[1], flags[1]); + spin_unlock_irqrestore(&chip->gpio_lock[0], flags[0]); } /**