From patchwork Wed Apr 29 20:46:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518351 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C22381 for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8377221707 for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="IQhJtA3O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726974AbgD2UqY (ORCPT ); Wed, 29 Apr 2020 16:46:24 -0400 Received: from plaes.org ([188.166.43.21]:34960 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726456AbgD2UqX (ORCPT ); Wed, 29 Apr 2020 16:46:23 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 92F91406D2; Wed, 29 Apr 2020 20:46:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193180; bh=oXxncios4NGf2aktHiZX8FnCvunPuUkRAB5eO78zbrg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IQhJtA3O6U6JCR32OoY0yGZk+wkoR+mazjBOT2uiJTHCusppZ2YPufw/sgfbmANCu UDqRAeOOmk8wz4ILHVCOJkGEH6SEsUfzdkPSadRR/GLi/ataECoiQx7PoN568Zx4nO qFsPMesW6/IxRbvUMYm0cAW83f+vIjQh26akHkO17W31aaLyBgEFdk+gJwacuNMmYO oAh2spSY91Fz6L7j7oENLHG56F3M+Dfp4dhOxE2+tbzQgLvWORrYsbd/DecsKwjBUy 5dYJe+HQQ7ZTEtx80OjzkiXYYqZsgcbCvJ3gAp4PN62a/deQhNVdx0kCUIyomm2yBd frsWFybK4wQNQ== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 1/6] clk: sunxi-ng: a20: Register regmap for sun7i CCU Date: Wed, 29 Apr 2020 23:46:07 +0300 Message-Id: <20200429204612.31883-2-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On sun7i, the gmac clock is handled by the dwmac-sunxi driver, but its configuration register is located in the CCU register range, requiring proper regmap setup. In order to do that, we use CLK_OF_DECLARE_DRIVER to initialize sun7i ccu, which clears the OF_POPULATED flag, allowing the platform device to probe the same resource with proper device node. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 60 +++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c index f32366d9336e..fbdf9ecf21b8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1478,5 +1480,61 @@ static void __init sun7i_a20_ccu_setup(struct device_node *node) { sun4i_ccu_init(node, &sun7i_a20_ccu_desc); } -CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu", +CLK_OF_DECLARE_DRIVER(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu", sun7i_a20_ccu_setup); + +/* + * Regmap for the GMAC driver (dwmac-sunxi) to allow access to + * GMAC configuration register. + */ +#define SUN7I_A20_GMAC_CFG_REG 0x164 +static bool sun7i_a20_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN7I_A20_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun7i_a20_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x1f4, /* clk_out_b */ + + .readable_reg = sun7i_a20_ccu_regmap_accessible_reg, + .writeable_reg = sun7i_a20_ccu_regmap_accessible_reg, +}; + +static int sun7i_a20_ccu_probe_regmap(struct platform_device *pdev) +{ + void __iomem *reg; + struct resource *res; + struct regmap *regmap; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun7i_a20_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return 0; +} + +static const struct of_device_id sun7i_a20_ccu_ids[] = { + { .compatible = "allwinner,sun7i-a20-ccu"}, + { } +}; + +static struct platform_driver sun7i_a20_ccu_driver = { + .probe = sun7i_a20_ccu_probe_regmap, + .driver = { + .name = "sun7i-a20-ccu", + .of_match_table = sun7i_a20_ccu_ids, + }, +}; +builtin_platform_driver(sun7i_a20_ccu_driver); From patchwork Wed Apr 29 20:46:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518369 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 601C881 for ; Wed, 29 Apr 2020 20:47:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 496B121D79 for ; Wed, 29 Apr 2020 20:47:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="gpuPNDZs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727830AbgD2Uqz (ORCPT ); Wed, 29 Apr 2020 16:46:55 -0400 Received: from plaes.org ([188.166.43.21]:35020 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727823AbgD2Uqy (ORCPT ); Wed, 29 Apr 2020 16:46:54 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 317AE40982; Wed, 29 Apr 2020 20:46:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193182; bh=iBYb49MohVTATz4R/8x9Z94Kuj2gJif8RNrCb2NzudQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gpuPNDZsbpNXEodt3H8N7cFkS/KzbFx5NP6wVyEhhASy+yfwMvMrsCmWggT7chfDP y2UyzMN0wV9FPVTu+BiE8HRPypTmGAkn3aprcU4HhraffAXA/AXODTG/QGrVDOi9zK mzF6UQxVdgC5iEbpa0k6TPPYfJHKOhMgYkvJMaOrwtAuuApdMOB/iBGB46c/GeTd2j qOMBByxn1d3K/Y1ffPUpwIbq6IniFFh1G+INFfeUWJFzXX/1dre4Aw9CKtpqfdMCnv HB7MHiW159lpDBjOVl7aKkIY4xF2cWB5RHBBG259UK7a/4NJ3rv2vfpaUqOjK+Lgc8 mx9oK/pd+VXgA== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 2/6] clk: sunxi-ng: a31: Register regmap for sun6i CCU Date: Wed, 29 Apr 2020 23:46:08 +0300 Message-Id: <20200429204612.31883-3-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On sun6i, the gmac clock is handled by the dwmac-sunxi driver, but its configuration register is located in the CCU register range, requiring proper regmap setup. In order to do that, we use CLK_OF_DECLARE_DRIVER to initialize sun7i ccu, which clears the OF_POPULATED flag, allowing the platform device to probe the same resource with device node. Signed-off-by: Priit Laes --- drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 60 +++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index 9b40d53266a3..086eb93a4efd 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -1262,5 +1262,61 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node) ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, &sun6i_a31_cpu_nb); } -CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", - sun6i_a31_ccu_setup); +CLK_OF_DECLARE_DRIVER(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", + sun6i_a31_ccu_setup); + +/* + * Regmap for the GMAC driver (dwmac-sunxi) to allow access to + * GMAC configuration register. + */ +#define SUN6I_A31_GMAC_CFG_REG 0xD0 +static bool sun6i_a31_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN6I_A31_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun6i_a31_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x308, /* clk_out_b */ + + .readable_reg = sun6i_a31_ccu_regmap_accessible_reg, + .writeable_reg = sun6i_a31_ccu_regmap_accessible_reg, +}; + +static int sun6i_a31_ccu_probe_regmap(struct platform_device *pdev) +{ + void __iomem *reg; + struct resource *res; + struct regmap *regmap; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun6i_a31_ccu_regmap_accessible_reg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return 0; +} + +static const struct of_device_id sun6i_a31_ccu_ids[] = { + { .compatible = "allwinner,sun6i-a31-ccu"}, + { } +}; + +static struct platform_driver sun6i_a31_ccu_driver = { + .probe = sun6i_a31_ccu_probe_regmap, + .driver = { + .name = "sun6i-a31-ccu", + .of_match_table = sun6i_a31_ccu_ids, + }, +}; +builtin_platform_driver(sun6i_a31_ccu_driver); From patchwork Wed Apr 29 20:46:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518353 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED01F92C for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D107E2192A for ; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="muALmyfm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726456AbgD2Uq1 (ORCPT ); Wed, 29 Apr 2020 16:46:27 -0400 Received: from plaes.org ([188.166.43.21]:34982 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727049AbgD2Uq0 (ORCPT ); Wed, 29 Apr 2020 16:46:26 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id C509740A4A; Wed, 29 Apr 2020 20:46:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193184; bh=vozgkxdGukZkw97VZxaA46SLq3vMd9Wmn6ITkjlRwzM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=muALmyfmKI5x02+uA4+LCgaYszU/T90rPKS7f7FgI4pIQlHoNk7s5FwLpp4xM67Na jJEHh26IsedVkgQUJCl97efrVgZ7RVu5bpO70jDVACHPg+LAJ479am0pxeSV98vGgC sY5Fi02A24DqBoH0mNLyVQ+06ZQfGIh3smIr/IXVQbbHCW8FFMG330IPYs3oyHmVNk iuU5yBW+CUIDi3KRTWXBZSyPey/ZW47CGomzkHtWQIlz4eNpwmVqAA258nRSZuGi6f gUa1Zs62dB4pSgSl8i7j57zVL/suFmKeNOgNohkF1Hefkld6NjUk8fmEJQj0JJGxd0 +t8DGmoFk2jgQ== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 3/6] net: stmmac: dwmac-sunxi: Implement syscon-based clock handling Date: Wed, 29 Apr 2020 23:46:09 +0300 Message-Id: <20200429204612.31883-4-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Convert the sun7i-gmac driver to use a regmap-based driver, instead of relying on the custom clock implementation. This allows to get rid of the last custom clock in the sun7i device tree making the sun7i fully CCU-compatible. Compatibility with existing devicetrees is retained. Signed-off-by: Priit Laes --- .../net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 130 ++++++++++++++++-- 1 file changed, 122 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c index 0e1ca2cba3c7..206398f7a2af 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c @@ -12,8 +12,11 @@ #include #include #include +#include #include #include +#include +#include #include "stmmac_platform.h" @@ -22,11 +25,23 @@ struct sunxi_priv_data { int clk_enabled; struct clk *tx_clk; struct regulator *regulator; + struct regmap_field *regmap_field; +}; + +/* EMAC clock register @ 0x164 in the CCU address range */ +static const struct reg_field ccu_reg_field = { + .reg = 0x164, + .lsb = 0, + .msb = 31, }; #define SUN7I_GMAC_GMII_RGMII_RATE 125000000 #define SUN7I_GMAC_MII_RATE 25000000 +#define SUN7I_A20_CLK_MASK GENMASK(2, 0) +#define SUN7I_A20_RGMII_CLK (BIT(2) | BIT(1)) +#define SUN7I_A20_MII_CLK 0 + static int sun7i_gmac_init(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; @@ -38,7 +53,20 @@ static int sun7i_gmac_init(struct platform_device *pdev, void *priv) return ret; } - /* Set GMAC interface port mode + if (gmac->regmap_field) { + if (phy_interface_mode_is_rgmii(gmac->interface)) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + return clk_prepare_enable(gmac->tx_clk); + } + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + return clk_enable(gmac->tx_clk); + } + + /* Legacy devicetree clock (allwinner,sun7i-a20-gmac-clk) support: * * The GMAC TX clock lines are configured by setting the clock * rate, which then uses the auto-reparenting feature of the @@ -62,9 +90,16 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) { struct sunxi_priv_data *gmac = priv; - if (gmac->clk_enabled) { + if (gmac->regmap_field) { + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, 0); clk_disable(gmac->tx_clk); - gmac->clk_enabled = 0; + } else { + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + if (gmac->clk_enabled) { + clk_disable(gmac->tx_clk); + gmac->clk_enabled = 0; + } } clk_unprepare(gmac->tx_clk); @@ -72,10 +107,55 @@ static void sun7i_gmac_exit(struct platform_device *pdev, void *priv) regulator_disable(gmac->regulator); } +static struct regmap *sun7i_gmac_get_syscon_from_dev(struct device_node *node) +{ + struct device_node *syscon_node; + struct platform_device *syscon_pdev; + struct regmap *regmap = NULL; + + syscon_node = of_parse_phandle(node, "syscon", 0); + if (!syscon_node) + return ERR_PTR(-ENODEV); + + syscon_pdev = of_find_device_by_node(syscon_node); + if (!syscon_pdev) { + /* platform device might not be probed yet */ + regmap = ERR_PTR(-EPROBE_DEFER); + goto out_put_node; + } + + /* If no regmap is found then the other device driver is at fault */ + regmap = dev_get_regmap(&syscon_pdev->dev, NULL); + if (!regmap) + regmap = ERR_PTR(-EINVAL); + + platform_device_put(syscon_pdev); +out_put_node: + of_node_put(syscon_node); + return regmap; +} + static void sun7i_fix_speed(void *priv, unsigned int speed) { struct sunxi_priv_data *gmac = priv; + if (gmac->regmap_field) { + clk_disable(gmac->tx_clk); + clk_unprepare(gmac->tx_clk); + if (speed == 1000) + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_RGMII_CLK); + else + regmap_field_update_bits(gmac->regmap_field, + SUN7I_A20_CLK_MASK, + SUN7I_A20_MII_CLK); + clk_prepare_enable(gmac->tx_clk); + return; + } + + /* Handle legacy devicetree clock (sun7i-a20-gmac-clk) */ + /* only GMII mode requires us to reconfigure the clock lines */ if (gmac->interface != PHY_INTERFACE_MODE_GMII) return; @@ -102,6 +182,8 @@ static int sun7i_gmac_probe(struct platform_device *pdev) struct stmmac_resources stmmac_res; struct sunxi_priv_data *gmac; struct device *dev = &pdev->dev; + struct device_node *syscon_node; + struct regmap *regmap = NULL; int ret; ret = stmmac_get_platform_resources(pdev, &stmmac_res); @@ -124,11 +206,43 @@ static int sun7i_gmac_probe(struct platform_device *pdev) goto err_remove_config_dt; } - gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); - if (IS_ERR(gmac->tx_clk)) { - dev_err(dev, "could not get tx clock\n"); - ret = PTR_ERR(gmac->tx_clk); - goto err_remove_config_dt; + /* Attempt to fetch syscon node... */ + syscon_node = of_parse_phandle(dev->of_node, "syscon", 0); + if (syscon_node) { + gmac->tx_clk = devm_clk_get(dev, "stmmaceth"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "Could not get TX clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + + regmap = sun7i_gmac_get_syscon_from_dev(pdev->dev.of_node); + if (IS_ERR(regmap)) + regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "syscon"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); + goto err_remove_config_dt; + } + + gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, + ccu_reg_field); + + if (IS_ERR(gmac->regmap_field)) { + ret = PTR_ERR(gmac->regmap_field); + dev_err(dev, "Unable to map syscon register: %d\n", ret); + goto err_remove_config_dt; + } + /* ...or fall back to legacy clock setup */ + } else { + gmac->tx_clk = devm_clk_get(dev, "allwinner_gmac_tx"); + if (IS_ERR(gmac->tx_clk)) { + dev_err(dev, "could not get tx clock\n"); + ret = PTR_ERR(gmac->tx_clk); + goto err_remove_config_dt; + } + dev_info(dev, "allwinner_gmac_tx support is deprecated!\n"); } /* Optional regulator for PHY */ From patchwork Wed Apr 29 20:46:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518365 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 612EC81 for ; Wed, 29 Apr 2020 20:47:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40FAC214D8 for ; Wed, 29 Apr 2020 20:47:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="ffDlUeuf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727874AbgD2UrJ (ORCPT ); Wed, 29 Apr 2020 16:47:09 -0400 Received: from plaes.org ([188.166.43.21]:35024 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727850AbgD2Uq7 (ORCPT ); Wed, 29 Apr 2020 16:46:59 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id D789440AF0; Wed, 29 Apr 2020 20:46:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193186; bh=vMo2TanI9GatNd59nOo9RI6zU3bToC+1dQv+F9Smax0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ffDlUeufauuoxFHGEN5d8Qaun4h95SBfuOJN8ElGVTF3o8YKdyywlB63loQJbtjHN IFd7iDKB+op4gl/yfMubDxwnqxvKrtEdIpHlZguhjF49a3XB1n856GBtHPauRBl/ak w2n82M9FQK8yLCDrZfAGmjDCNy7FNNVRfIJNIY/pSQsjAmddr59JVCEET6i60zIQq5 G0OaxCQuUVr0R4wbntqTRYjjLdML7HoTL2hKQANOI298gERNIfbIXmOTEKvgCXm/h0 MRqyKswe28vDe2dGM1vJ3327ixfrD0CW8rmpcV9vKtjQmj1eQog5J8PL0llRtXHIJx GLKsU+M1cGKwQ== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 4/6] dt-bindings: net: sun7i-gmac: Add syscon support Date: Wed, 29 Apr 2020 23:46:10 +0300 Message-Id: <20200429204612.31883-5-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Now that driver supports syscon-based regmap access, document also the devicetree binding. Signed-off-by: Priit Laes --- .../bindings/net/allwinner,sun7i-a20-gmac.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml index 703d0d886884..c41d7c598c19 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun7i-a20-gmac.yaml @@ -29,17 +29,26 @@ properties: clocks: items: - description: GMAC main clock + + # Deprecated - description: TX clock clock-names: items: - const: stmmaceth + + # Deprecated - const: allwinner_gmac_tx phy-supply: description: PHY regulator + syscon: + $ref: /schemas/types.yaml#definitions/phandle + description: + Phandle to the device containing the GMAC clock register + required: - compatible - reg @@ -48,6 +57,7 @@ required: - clocks - clock-names - phy-mode + - syscon unevaluatedProperties: false @@ -55,11 +65,12 @@ examples: - | gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&syscon>; reg = <0x01c50000 0x10000>; interrupts = <0 85 1>; interrupt-names = "macirq"; - clocks = <&ahb_gates 49>, <&gmac_tx>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ahb_gates 49>; + clock-names = "stmmaceth"; phy-mode = "mii"; }; From patchwork Wed Apr 29 20:46:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518355 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 469AA81 for ; Wed, 29 Apr 2020 20:46:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D7362137B for ; Wed, 29 Apr 2020 20:46:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="ZA8/lHmz" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727049AbgD2Uqa (ORCPT ); Wed, 29 Apr 2020 16:46:30 -0400 Received: from plaes.org ([188.166.43.21]:34982 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727093AbgD2Uq3 (ORCPT ); Wed, 29 Apr 2020 16:46:29 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 75E48411A4; Wed, 29 Apr 2020 20:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193187; bh=4Nyq2+q+6gFl8xdUXrX7ogdDuJtGtGSha4s+xAB0G6E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZA8/lHmzMQuXj6T6y9Xe46t1VLVwUt7NOx0b2fenM13e5PBJ+y76kicCKBrxJeRjN O50M9Ge7PhNyBmtDB9AhiDmlZwI/ywWpA+IOnpJKLjgx0yKRU2OsvKUc74S7HO3dJb BGrM91i27CuehE2tBcA8OH7/+Llt+w34t+BpsZsO6Eqe/QBFMBxbU0O6bJtj2P9SU7 3H2OkfWSvQGNNpLRnD5+OuHkXNqb3z9ACW/O1pkLlMQjZsPuvLr5XEUOmJ3vH6Khwy 7bTdYzZzMiVr/V59FeQvjldu+70AYzoxaMZWis/8DzFgOSxcyf3pn9okOU63LmbjD9 WbqKwASDZojSg== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 5/6] ARM: dts: sun7i: Use syscon-based implementation for gmac Date: Wed, 29 Apr 2020 23:46:11 +0300 Message-Id: <20200429204612.31883-6-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use syscon-based approach to access gmac clock configuration register, instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and dummy clocks making sun7i fully CCU-compatible. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun7i-a20.dtsi | 36 +++----------------------------- 1 file changed, 3 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index ffe1d10a1a84..750962a94fad 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -219,37 +219,6 @@ osc32k: clk-32k { clock-frequency = <32768>; clock-output-names = "osc32k"; }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c20164 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c20164 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; @@ -1511,11 +1480,12 @@ mali: gpu@1c40000 { gmac: ethernet@1c50000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c50000 0x10000>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB_GMAC>; + clock-names = "stmmaceth"; snps,pbl = <2>; snps,fixed-burst; snps,force_sf_dma_mode; From patchwork Wed Apr 29 20:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priit Laes X-Patchwork-Id: 11518363 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8409181 for ; Wed, 29 Apr 2020 20:47:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B4EA20BED for ; Wed, 29 Apr 2020 20:47:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=plaes.org header.i=@plaes.org header.b="iXIpe3Y+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727892AbgD2UrD (ORCPT ); Wed, 29 Apr 2020 16:47:03 -0400 Received: from plaes.org ([188.166.43.21]:35034 "EHLO plaes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727874AbgD2UrC (ORCPT ); Wed, 29 Apr 2020 16:47:02 -0400 Received: from localhost (unknown [IPv6:2001:1530:1000:d397:940e:6b9e:3deb:3]) by plaes.org (Postfix) with ESMTPSA id 27C2F406D2; Wed, 29 Apr 2020 20:46:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=plaes.org; s=mail; t=1588193189; bh=hD8MO8nZG7cWOQMyvrg2gESOCiX1BXG9t5neHczu/iA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iXIpe3Y+PbIFsrKy3pI5oWGv70swaGWQqS0jNKqF7Fa+apASm3B0MrhusmrrJct93 apTgFtSE9y10wyorWdpzYyKvpYnoAoLHS9WsVhI85vFWnpdNgOY6X3m1BMjVnXWNvi o9575D9Z3tGZHvKXj4E9BCpabTbKzYDx3kxJieWWTIz+bw1eYx7+SFBxvcnxfwyRke OXvYI21clbu6d52frM234CHwkvxIq8JelPajlOQmVK8uCWFAbvK1X2ftMF/7VhUjmn qPy3JuXulTak3ZaFlnenKIVtgdGLHxoTW8F2s/59pxl+bzI1SOLS1ErlzZsOONWpzY ywl/yvEglystw== From: Priit Laes To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Priit Laes Subject: [PATCH v2 6/6] ARM: dts: sun6i: Use syscon-based implementation for gmac Date: Wed, 29 Apr 2020 23:46:12 +0300 Message-Id: <20200429204612.31883-7-plaes@plaes.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429204612.31883-1-plaes@plaes.org> References: <20200429204612.31883-1-plaes@plaes.org> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Use syscon-based approach to access gmac clock configuration register instead of relying on a custom clock driver. As a bonus, we can now drop the custom clock implementation and the dummy clocks. Signed-off-by: Priit Laes --- arch/arm/boot/dts/sun6i-a31.dtsi | 35 +++----------------------------- 1 file changed, 3 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index f3425a66fc0a..fcf8a242741f 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -228,36 +228,6 @@ osc32k: clk-32k { clock-output-names = "ext_osc32k"; }; - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: clk-mii-phy-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: clk-gmac-int-tx { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@1c200d0 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x01c200d0 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; }; de: display-engine { @@ -943,11 +913,12 @@ i2c3: i2c@1c2b800 { gmac: ethernet@1c30000 { compatible = "allwinner,sun7i-a20-gmac"; + syscon = <&ccu>; reg = <0x01c30000 0x1054>; interrupts = ; interrupt-names = "macirq"; - clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; + clocks = <&ccu CLK_AHB1_EMAC>; + clock-names = "stmmaceth"; resets = <&ccu RST_AHB1_EMAC>; reset-names = "stmmaceth"; snps,pbl = <2>;