From patchwork Thu Apr 30 21:45:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521693 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A113913 for ; Thu, 30 Apr 2020 21:46:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 34FE42071C for ; Thu, 30 Apr 2020 21:46:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="GAoDKWFL"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="IEibsAiA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 34FE42071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=GIlK1AZ1QA/0n9CsbHgXAsg3qn7UfdYldsoGCUFMVV8=; b=GAoDKWFLx3c3Mb6gn/RFdcA4CP nPYIeh+GaN2c4T+Qunr2EA4PfPtSxdcTmues/oMP38UMd14F/oIrI+YnZMc62/0FxUf9omeAV9d5p BsiMET0fO+RdI0G7Ivxh1QKhRyG4LU2VdeLVgpSLiZA3tDBd1Cl5AYh2kKnc2hbegtV9wWfV2LobJ 0dq0EsNdXLu7JRC/6n5Zc4u+AN0awrQELAKCrLP/LXbLe9xwVgiLBi4fi2NiMU54uJIfW2PepzDB8 igo2uvAXFZsMrP4Lu+XHumY4X3dEAcN8sXZcelBc4unxbjww3KartrS2bNMqqpFvl+y5mhNgP1OTX nu/gAsvw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0G-0006tu-Ue; Thu, 30 Apr 2020 21:45:56 +0000 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0D-0006rg-Rg for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:45:55 +0000 Received: by mail-pl1-x644.google.com with SMTP id u22so2831733plq.12 for ; Thu, 30 Apr 2020 14:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=L+A6rotdTZxuFABPL+Mc8AuyhvfS/Z9BRk0edgcGHN8=; b=IEibsAiA0rVwYMfX9NMNP/+o0qp1andbmRkUO/7YuIRfgZ4klD05m5FOaC5Q/7r4Cu 47nkdFF13Ub4i1HvJgTuj1IJehuh47WChSL2kI609rHzU+GPDASqeo4Sl8NwGt/brMiJ PsuP+pHPTB17joqerUC3qF5rniE208ua+kQbA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=L+A6rotdTZxuFABPL+Mc8AuyhvfS/Z9BRk0edgcGHN8=; b=SHoTCGsB5oWbbpicccrSjqshS0qypIXP7qwoGEwYTXOGDKLW4pPHP+9XAPL8iq1InY V8uv2GZk6w7wvAhvFUaBVXwFv19uNwZrvXPAx6phSDVbYu9UXGRl8vT7KqNEqiBQm/Eg KV7QmpIYiAM7ZchGxM0ZMdk6Ak9MCD0ilDinYCOgRBGkD2xXpzBgVAKJ9+dTMLwFxEGs 1POcr9Lu1Tb49wrpXFHaOfm0009BYuk4eVSpU/2+KonY7z9vx1Fvjo/b4Gu0LcA35GGg 9t0leXvKbIEkZQvDe3XalkGPBpbIn9LvySEhjf0b21ySX1YZffnQmBqcpgCW5YA4jOj3 qNuw== X-Gm-Message-State: AGi0Pua4hRH5c0Yjf6Oz7tBEzAQngtcXDU0L/VD0iXt+8jItON0g3Ehn Y2bpf906NUGakrwWN272x3DcRA== X-Google-Smtp-Source: APiQypLnH1Jab9Wyt6jG9QX1cU/qhcktpVbGrf3kZVfPHEVBcSKjwLnpjGoafd5HtRIPx1leuFp0Bw== X-Received: by 2002:a17:90a:2004:: with SMTP id n4mr1003560pjc.190.1588283153100; Thu, 30 Apr 2020 14:45:53 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:45:52 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 1/7] phy: Add Rockchip PCIe PHY driver Date: Fri, 1 May 2020 03:15:23 +0530 Message-Id: <20200430214529.18887-2-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144553_901644_9870D8AB X-CRM114-Status: GOOD ( 16.24 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add the Rockchip PCIe PHY driver as part of Generic PHY framework. Signed-off-by: Jagan Teki --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 6 + drivers/phy/rockchip/phy-rockchip-pcie.c | 271 +++++++++++++++++++++++ 5 files changed, 289 insertions(+) create mode 100644 drivers/phy/rockchip/Kconfig create mode 100644 drivers/phy/rockchip/Makefile create mode 100644 drivers/phy/rockchip/phy-rockchip-pcie.c diff --git a/drivers/Kconfig b/drivers/Kconfig index e34a22708c..2fe23f953c 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -76,6 +76,8 @@ source "drivers/phy/allwinner/Kconfig" source "drivers/phy/marvell/Kconfig" +source "drivers/phy/rockchip/Kconfig" + source "drivers/pinctrl/Kconfig" source "drivers/power/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 4208750428..94e8c5da17 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -91,6 +91,7 @@ obj-y += dfu/ obj-$(CONFIG_PCH) += pch/ obj-y += phy/allwinner/ obj-y += phy/marvell/ +obj-y += phy/rockchip/ obj-y += rtc/ obj-y += scsi/ obj-y += sound/ diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig new file mode 100644 index 0000000000..477c68920b --- /dev/null +++ b/drivers/phy/rockchip/Kconfig @@ -0,0 +1,9 @@ +# +# Phy drivers for Rockchip platforms +# +config PHY_ROCKCHIP_PCIE + bool "Rockchip PCIe PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Enable this to support the Rockchip PCIe PHY. diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile new file mode 100644 index 0000000000..4d19ccdfd0 --- /dev/null +++ b/drivers/phy/rockchip/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Amarula Solutions(India) +# + +obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c new file mode 100644 index 0000000000..83928cffe0 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: (GPL-2.0-only) +/* + * Rockchip PCIe PHY driver + * + * Copyright (C) 2020 Amarula Solutions(India) + * Copyright (C) 2016 Shawn Lin + * Copyright (C) 2016 ROCKCHIP, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(x + 16) set to 1 the BIT(x) can be written. + */ +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +#define PHY_MAX_LANE_NUM 4 +#define PHY_CFG_DATA_SHIFT 7 +#define PHY_CFG_ADDR_SHIFT 1 +#define PHY_CFG_DATA_MASK 0xf +#define PHY_CFG_ADDR_MASK 0x3f +#define PHY_CFG_RD_MASK 0x3ff +#define PHY_CFG_WR_ENABLE 1 +#define PHY_CFG_WR_DISABLE 1 +#define PHY_CFG_WR_SHIFT 0 +#define PHY_CFG_WR_MASK 1 +#define PHY_CFG_PLL_LOCK 0x10 +#define PHY_CFG_CLK_TEST 0x10 +#define PHY_CFG_CLK_SCC 0x12 +#define PHY_CFG_SEPE_RATE BIT(3) +#define PHY_CFG_PLL_100M BIT(3) +#define PHY_PLL_LOCKED BIT(9) +#define PHY_PLL_OUTPUT BIT(10) +#define PHY_LANE_RX_DET_SHIFT 11 +#define PHY_LANE_RX_DET_TH 0x1 +#define PHY_LANE_IDLE_OFF 0x1 +#define PHY_LANE_IDLE_MASK 0x1 +#define PHY_LANE_IDLE_A_SHIFT 3 +#define PHY_LANE_IDLE_B_SHIFT 4 +#define PHY_LANE_IDLE_C_SHIFT 5 +#define PHY_LANE_IDLE_D_SHIFT 6 + +struct rockchip_pcie_phy_data { + unsigned int pcie_conf; + unsigned int pcie_status; + unsigned int pcie_laneoff; +}; + +struct rockchip_pcie_phy { + void *reg_base; + struct clk refclk; + struct reset_ctl phy_rst; + const struct rockchip_pcie_phy_data *data; +}; + +static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data) +{ + u32 reg; + + reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT); + reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_conf); + + udelay(1); + + reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_conf); + + udelay(1); + + reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE, + PHY_CFG_WR_MASK, + PHY_CFG_WR_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_conf); +} + +static int rockchip_pcie_phy_power_on(struct phy *phy) +{ + struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev); + int ret = 0; + u32 reg, status; + + ret = reset_deassert(&priv->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_conf); + + reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_laneoff); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&priv->dev, "pll lock timeout!\n"); + goto err_pll_lock; + } + + phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); + phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); + + ret = -ETIMEDOUT; + ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status, + status, + !(status & PHY_PLL_OUTPUT), + 20 * 1000, + 50); + if (ret) { + dev_err(&priv->dev, "pll output enable timeout!\n"); + goto err_pll_lock; + } + + reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK, + PHY_CFG_ADDR_MASK, + PHY_CFG_ADDR_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_conf); + + ret = -EINVAL; + ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status, + status, + status & PHY_PLL_LOCKED, + 20 * 1000, + 50); + if (ret) { + dev_err(&priv->dev, "pll relock timeout!\n"); + goto err_pll_lock; + } + + return 0; + +err_pll_lock: + reset_assert(&priv->phy_rst); + return ret; +} + +static int rockchip_pcie_phy_power_off(struct phy *phy) +{ + struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev); + int ret; + u32 reg; + + reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF, + PHY_LANE_IDLE_MASK, + PHY_LANE_IDLE_A_SHIFT); + writel(reg, priv->reg_base + priv->data->pcie_laneoff); + + ret = reset_assert(&priv->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + return ret; + } + + return 0; +} + +static int rockchip_pcie_phy_init(struct phy *phy) +{ + struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev); + int ret; + + ret = clk_enable(&priv->refclk); + if (ret) { + dev_err(dev, "failed to enable refclk clock\n"); + return ret; + } + + ret = reset_assert(&priv->phy_rst); + if (ret) { + dev_err(dev, "failed to assert phy reset\n"); + goto err_reset; + } + + return 0; + +err_reset: + clk_disable(&priv->refclk); + return ret; +} + +static int rockchip_pcie_phy_exit(struct phy *phy) +{ + struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev); + + clk_disable(&priv->refclk); + + return 0; +} + +static struct phy_ops rockchip_pcie_phy_ops = { + .init = rockchip_pcie_phy_init, + .power_on = rockchip_pcie_phy_power_on, + .power_off = rockchip_pcie_phy_power_off, + .exit = rockchip_pcie_phy_exit, +}; + +static int rockchip_pcie_phy_probe(struct udevice *dev) +{ + struct rockchip_pcie_phy *priv = dev_get_priv(dev); + int ret; + + priv->data = (const struct rockchip_pcie_phy_data *) + dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + ret = clk_get_by_name(dev, "refclk", &priv->refclk); + if (ret) { + dev_err(dev, "failed to get refclk clock phandle\n"); + return ret; + } + + ret = reset_get_by_name(dev, "phy", &priv->phy_rst); + if (ret) { + dev_err(dev, "failed to get phy reset phandle\n"); + return ret; + } + + return 0; +} + +static const struct rockchip_pcie_phy_data rk3399_pcie_data = { + .pcie_conf = 0xe220, + .pcie_status = 0xe2a4, + .pcie_laneoff = 0xe214, +}; + +static const struct udevice_id rockchip_pcie_phy_ids[] = { + { + .compatible = "rockchip,rk3399-pcie-phy", + .data = (ulong)&rk3399_pcie_data, + }, + { /* sentile */ } +}; + +U_BOOT_DRIVER(rockchip_pcie_phy) = { + .name = "rockchip_pcie_phy", + .id = UCLASS_PHY, + .of_match = rockchip_pcie_phy_ids, + .ops = &rockchip_pcie_phy_ops, + .probe = rockchip_pcie_phy_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy), +}; From patchwork Thu Apr 30 21:45:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521695 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F91A15AB for ; Thu, 30 Apr 2020 21:46:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D6982071C for ; Thu, 30 Apr 2020 21:46:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="mmVcRqHr"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="a1u4SNqw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D6982071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=/Hzi00IDl5PvC1NY3VbXMuvBv34X0Ilb4tvxjCV97oM=; b=mmVcRqHr46MIlNc8garA/mLTCH QnsXshInbchSaaVbvzu8QbslfbiCU66ea+XDvMkOVsPRYTvq3taQSNpkVX3Fop5g1pdHIbwlIkh8u HIyGt3DWtYXSh+EtC7EXnhxtfKi9NmV8uFgw5tjhzoQYe9XgGiRJKAia7CrTOceiwjBYOx41SOJfK fNhDE4X+xpvkhectZfIGCKzv/CmkekHckSCus1rc77PKnOc9RyI4uAEW7LyybY9bg0HYVoMwj2jiq dOqUaKpZhDMgVF/xfRoH5dqKnYn7ok2+8We31epfjYAnREuEdrvrlu6G7CW/2kD7c7O5GvXghf5eF 1KXqeSWg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0L-0006y3-7s; Thu, 30 Apr 2020 21:46:01 +0000 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0I-0006vO-Gd for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:45:59 +0000 Received: by mail-pg1-x543.google.com with SMTP id n11so3542117pgl.9 for ; Thu, 30 Apr 2020 14:45:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=40olgW3N0Uw63GCK12v84nv1cBBanm0u/AYCKonjKBo=; b=a1u4SNqwRxeD6DYb1+5uX8jPpR9a7aXmY6v1cMa2x76p3mGVPZSRFDI/1juR5Egn1U wlr65BI+blDnAu4I4KZmr0vm495wjWdI2sEDiSiuzNa6nSjSVmGlKn2UwUD3Ib/SJshl HhEd3a0JPmqJ9l1EtQ0xboDKYJw679Y3a4k0w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=40olgW3N0Uw63GCK12v84nv1cBBanm0u/AYCKonjKBo=; b=e2civ7daznUyCP/1ZVansyOus1/rqfs9SQ3PV6SDTQbRa2/FHos2Ik4cckSo+B7Myq 6Ydm0T7OqwAtuQ0+AxjFN1lbggztDuHby51i0mcXA7B4jAXRgl63BhB+HBvqSeybZfqj 76GareiRJ3vlKAlTP5GzIrRxRaMrwQ4b/cHsO+GBs8bwOuNm496RLnECXdzSy8XROSsn Y4nb3wDiGhfjgk1/ZQfkCic4FmrIRg6Il/AnmvAMdYFIq+KLcM3DVhTozIiV6EJaJZIj CMM+E66EHMnF26j0upO7TEyZkiFCx83Rbcp/45+l1MVm5UaKouaszZ2bkRrZkI9ldCbd PWew== X-Gm-Message-State: AGi0PubUPmTZ1Nl2AZh5fCr54h13wfsXGa+uA8Pe3mQ/R7+uqmdbiUGv 97ylOG15+EjlR/xzEpNl/B2WdQ== X-Google-Smtp-Source: APiQypIg0JjBUbAw54m9+hDQKijdoeHiVypHgB75BmQ23RKMp1/BjLZtFIMVOr+G+PcoJBPqk+MpQw== X-Received: by 2002:a63:e210:: with SMTP id q16mr1033945pgh.26.1588283157626; Thu, 30 Apr 2020 14:45:57 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:45:56 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 2/7] clk: rk3399: Enable/Disable the USB2PHY clk Date: Fri, 1 May 2020 03:15:24 +0530 Message-Id: <20200430214529.18887-3-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144558_557317_DF29FF17 X-CRM114-Status: UNSURE ( 8.03 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:543 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki --- drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 7feba92f9e..b1c89ea127 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1091,6 +1091,12 @@ static int rk3399_clk_enable(struct clk *clk) case SCLK_MACREF_OUT: rk_clrreg(&priv->cru->clkgate_con[5], BIT(6)); break; + case SCLK_USB2PHY0_REF: + rk_clrreg(&priv->cru->clkgate_con[6], BIT(5)); + break; + case SCLK_USB2PHY1_REF: + rk_clrreg(&priv->cru->clkgate_con[6], BIT(6)); + break; case ACLK_GMAC: rk_clrreg(&priv->cru->clkgate_con[32], BIT(0)); break; @@ -1167,6 +1173,12 @@ static int rk3399_clk_disable(struct clk *clk) case SCLK_MACREF_OUT: rk_setreg(&priv->cru->clkgate_con[5], BIT(6)); break; + case SCLK_USB2PHY0_REF: + rk_setreg(&priv->cru->clkgate_con[6], BIT(5)); + break; + case SCLK_USB2PHY1_REF: + rk_setreg(&priv->cru->clkgate_con[6], BIT(6)); + break; case ACLK_GMAC: rk_setreg(&priv->cru->clkgate_con[32], BIT(0)); break; From patchwork Thu Apr 30 21:45:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521697 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E58A815AB for ; Thu, 30 Apr 2020 21:46:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C15712071C for ; Thu, 30 Apr 2020 21:46:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bxcMsGEo"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="hew9vsu2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C15712071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=NtqzPY877z1fFitIvIXJsx5wruwe4JDD/9z2xtE1+cY=; b=bxcMsGEoFlH4HN7af2EFaQKRGm VSrySxZoxZfYaGGpIErtUPYwLM5xb/JW+Te3AIB6YO1ACLGGcOJDOlMPQqLoFCR2FE7fakIdITat9 IplO2PsDac8d7VNiigZe/VONoaFfRA1D17x4CDaPaoFC5iV4NJEp7IT2Oft7mP8gZEXNe2E3UPaX9 wBKnTz0sqrVeuksVRf70i6ez08y56DAGZFcZfMcvwkOrTQgjrMA9BFC1wFtocG8MZnRsqL9Y/N/Wi mbViiFQXFHQ58i1+4ft7clBxxc1+xBPLDxYCI3/6322Blj/7zjC1F1E3Vw0l9n2Vu/0/tiK9uyXZj C0UkRUEw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0Q-00072I-68; Thu, 30 Apr 2020 21:46:06 +0000 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0N-000706-H6 for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:46:05 +0000 Received: by mail-pj1-x1043.google.com with SMTP id t40so1485146pjb.3 for ; Thu, 30 Apr 2020 14:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oD5CV2O7MmwLAjEtD/L06xey03PjjQ+hL9rWy48y+08=; b=hew9vsu2YAJvtV9NYbSSxPnkEzcY0eN/qhc9A1BvrVem5QRO19RZpDKmbb9qirjTHF 9jxLjn/oiOGHiu8lIBVhOicwrMUi6lE1puYTIu+asT70gcSyWXX9WiwRs68YCXxXaINx 9Jdw34zQsUhQXDNCbAgRUA+8i+Y13Fisz2pJY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oD5CV2O7MmwLAjEtD/L06xey03PjjQ+hL9rWy48y+08=; b=N5Zy4y/cnB7dGh7Rg78ppjBFS0z8KuRZH/hCetfUnU6mW43+GWxU6ChbJ62MsxNuZt 0U2U3qjSH3xkdmFHyNfoxyk8+FZSnAocsRqpDM5N5RhWDrnaFXdgM7Fkl1vGFiaAsSRI eEW9n7B6/udxdvx0CKohpTEgSeO2VNM6tUxVX1PW/MiLLdUfXS18cdc+DU0ZuLAr2TF6 OsB+qp6J6gnoH1F+4S36jj7GbPYSsptGe9P8EgdhWY/1XixSp8T1U9oKoDIH+j+7osh7 hcrDYcfJb+Q3MpSDPqSKhE1GlEuc/kBwM+Fa1Q1Thhl39FoBp3ov3acaNPl2MmwxRx8/ se4A== X-Gm-Message-State: AGi0Pub+jhqRRAyq+LnBVk4j1ZxJGVAJeuKXkCVyxCangA4fwZ7UzxPW D+kYW7got2Dk4XV+pJXjQN49jA== X-Google-Smtp-Source: APiQypLKpsX9LnMWOJC8aRxrYR0KTDxZpNzPpWTJcP6JHzn6f/0hsX/2mYJCu5JF3qPcXsD16+ZKQA== X-Received: by 2002:a17:902:a5c2:: with SMTP id t2mr1074951plq.151.1588283162491; Thu, 30 Apr 2020 14:46:02 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:46:01 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 3/7] phy: rockchip: Add Rockchip USB2PHY driver Date: Fri, 1 May 2020 03:15:25 +0530 Message-Id: <20200430214529.18887-4-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144603_570467_6837375D X-CRM114-Status: GOOD ( 17.38 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1043 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki --- drivers/phy/rockchip/Kconfig | 7 + drivers/phy/rockchip/Makefile | 1 + drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 312 ++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb2.c diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig index 477c68920b..f7ddac4744 100644 --- a/drivers/phy/rockchip/Kconfig +++ b/drivers/phy/rockchip/Kconfig @@ -7,3 +7,10 @@ config PHY_ROCKCHIP_PCIE select PHY help Enable this to support the Rockchip PCIe PHY. + +config PHY_ROCKCHIP_INNO_USB2 + bool "Rockchip INNO USB2PHY Driver" + depends on ARCH_ROCKCHIP + select PHY + help + Support for Rockchip USB2.0 PHY with Innosilicon IP block. diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile index 4d19ccdfd0..82d771b70b 100644 --- a/drivers/phy/rockchip/Makefile +++ b/drivers/phy/rockchip/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o +obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c new file mode 100644 index 0000000000..dd4905d834 --- /dev/null +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Rockchip USB2.0 PHY with Innosilicon IP block driver + * + * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (C) 2020 Amarula Solutions(India) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define usleep_range(a, b) udelay((b)) +#define BIT_WRITEABLE_SHIFT 16 + +enum rockchip_usb2phy_port_id { + USB2PHY_PORT_OTG, + USB2PHY_PORT_HOST, + USB2PHY_NUM_PORTS, +}; + +struct usb2phy_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +struct rockchip_usb2phy_port_cfg { + struct usb2phy_reg phy_sus; + struct usb2phy_reg bvalid_det_en; + struct usb2phy_reg bvalid_det_st; + struct usb2phy_reg bvalid_det_clr; + struct usb2phy_reg ls_det_en; + struct usb2phy_reg ls_det_st; + struct usb2phy_reg ls_det_clr; + struct usb2phy_reg utmi_avalid; + struct usb2phy_reg utmi_bvalid; + struct usb2phy_reg utmi_ls; + struct usb2phy_reg utmi_hstdet; +}; + +struct rockchip_usb2phy_cfg { + unsigned int reg; + const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; +}; + +struct rockchip_usb2phy { + void *reg_base; + struct clk phyclk; + const struct rockchip_usb2phy_cfg *phy_cfg; +}; + +static inline int property_enable(void *reg_base, + const struct usb2phy_reg *reg, bool en) +{ + unsigned int val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return writel(val, reg_base + reg->offset); +} + +static const +struct rockchip_usb2phy_port_cfg *us2phy_get_port(struct phy *phy) +{ + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg; + + return &phy_cfg->port_cfgs[phy->id]; +} + +static int rockchip_usb2phy_power_on(struct phy *phy) +{ + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + + property_enable(priv->reg_base, &port_cfg->phy_sus, false); + + /* waiting for the utmi_clk to become stable */ + usleep_range(1500, 2000); + + return 0; +} + +static int rockchip_usb2phy_power_off(struct phy *phy) +{ + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + + property_enable(priv->reg_base, &port_cfg->phy_sus, true); + + return 0; +} + +static int rockchip_usb2phy_init(struct phy *phy) +{ + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + int ret; + + ret = clk_enable(&priv->phyclk); + if (ret) { + dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret); + return ret; + } + + if (phy->id == USB2PHY_PORT_OTG) { + property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true); + property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true); + } else if (phy->id == USB2PHY_PORT_HOST) { + property_enable(priv->reg_base, &port_cfg->bvalid_det_clr, true); + property_enable(priv->reg_base, &port_cfg->bvalid_det_en, true); + } + + return 0; +} + +static int rockchip_usb2phy_exit(struct phy *phy) +{ + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + + clk_disable(&priv->phyclk); + + return 0; +} + +static int rockchip_usb2phy_of_xlate(struct phy *phy, + struct ofnode_phandle_args *args) +{ + const char *name = phy->dev->name; + + if (!strcasecmp(name, "host-port")) + phy->id = USB2PHY_PORT_HOST; + else if (!strcasecmp(name, "otg-port")) + phy->id = USB2PHY_PORT_OTG; + else + dev_err(phy->dev, "improper %s device\n", name); + + return 0; +} + +static struct phy_ops rockchip_usb2phy_ops = { + .init = rockchip_usb2phy_init, + .exit = rockchip_usb2phy_exit, + .power_on = rockchip_usb2phy_power_on, + .power_off = rockchip_usb2phy_power_off, + .of_xlate = rockchip_usb2phy_of_xlate, +}; + +static int rockchip_usb2phy_probe(struct udevice *dev) +{ + struct rockchip_usb2phy *priv = dev_get_priv(dev); + const struct rockchip_usb2phy_cfg *phy_cfgs; + unsigned int reg; + int index, ret; + + priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->reg_base)) + return PTR_ERR(priv->reg_base); + + ret = dev_read_u32_index(dev, "reg", 1, ®); + if (ret) { + dev_err(dev, "failed to read reg property (ret = %d)\n", ret); + return ret; + } + + phy_cfgs = (const struct rockchip_usb2phy_cfg *) + dev_get_driver_data(dev); + if (!phy_cfgs) + return -EINVAL; + + /* find out a proper config which can be matched with dt. */ + index = 0; + while (phy_cfgs[index].reg) { + if (phy_cfgs[index].reg == reg) { + priv->phy_cfg = &phy_cfgs[index]; + break; + } + + ++index; + } + + if (!priv->phy_cfg) { + dev_err(dev, "failed find proper phy-cfg\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "phyclk", &priv->phyclk); + if (ret) { + dev_err(dev, "failed to get the phyclk (ret=%d)\n", ret); + return ret; + } + + return 0; +} + +static int rockchip_usb2phy_bind(struct udevice *dev) +{ + struct udevice *usb2phy_dev; + ofnode node; + const char *name; + int ret = 0; + + dev_for_each_subnode(node, dev) { + if (!ofnode_valid(node)) { + dev_info(dev, "subnode %s not found\n", dev->name); + return -ENXIO; + } + + name = ofnode_get_name(node); + dev_dbg(dev, "subnode %s\n", name); + + ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port", + name, node, &usb2phy_dev); + if (ret) { + dev_err(dev, + "'%s' cannot bind 'rockchip_usb2phy_port'\n", name); + return ret; + } + } + + return ret; +} + +static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = { + { + .reg = 0xe450, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe454, 1, 0, 2, 1 }, + .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, + .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, + .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, + .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, + .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } + } + }, + }, + { + .reg = 0xe460, + .port_cfgs = { + [USB2PHY_PORT_OTG] = { + .phy_sus = { 0xe464, 1, 0, 2, 1 }, + .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, + .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, + .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, + .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, + .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, + }, + [USB2PHY_PORT_HOST] = { + .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, + .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, + .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, + .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, + .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, + .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } + } + }, + }, + { /* sentinel */ } +}; + +static const struct udevice_id rockchip_usb2phy_ids[] = { + { + .compatible = "rockchip,rk3399-usb2phy", + .data = (ulong)&rk3399_usb2phy_cfgs, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(rockchip_usb2phy_port) = { + .name = "rockchip_usb2phy_port", + .id = UCLASS_PHY, + .ops = &rockchip_usb2phy_ops, +}; + +U_BOOT_DRIVER(rockchip_usb2phy) = { + .name = "rockchip_usb2phy", + .id = UCLASS_PHY, + .of_match = rockchip_usb2phy_ids, + .probe = rockchip_usb2phy_probe, + .bind = rockchip_usb2phy_bind, + .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy), +}; From patchwork Thu Apr 30 21:45:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521699 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CFDB913 for ; Thu, 30 Apr 2020 21:46:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A8DF2071C for ; Thu, 30 Apr 2020 21:46:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WE3vxsrU"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="N+e0TZAA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A8DF2071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=UUd216Yy4+BBt1hZpztOygMh1M8K/iqz93Xt25bxLmk=; b=WE3vxsrU6EevoVd8WwBU8SmQ12 /bRmfKinf5kdV3LyD7lCFV7ZFj18Ih/nhOFRsuoNkZ4no++RWIDod9+0iLfdW0GEMNn4xAnPYbEFf +vxwt/Q/6AAgDCuttbW228apqXo0+C06QOhqWuyqgayc/sTu8PW2rDcebGijU5s9ss7R5L9uVxtaR m/ixDMjfxqCGRjFidJDHrHE1Z8DpxqMtNluQca4g52QufxX0IE9Y/Xu0ZCXrmrprRani85nnX4uwt /ZqptOl5sZ8UbYPxAYqy55wvZ8OhldDsqw9KOXS/wwaLazqLkWznrp2M0pzdrAE0EZghzvrNFVVR4 NP7k9pxw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0U-00075H-74; Thu, 30 Apr 2020 21:46:10 +0000 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0R-00073i-KT for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:46:09 +0000 Received: by mail-pl1-x644.google.com with SMTP id f8so2848153plt.2 for ; Thu, 30 Apr 2020 14:46:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6+Nlz4K5CVynOeUhqGSCw2yzk9Vj1GohEKvgEtpoNmY=; b=N+e0TZAAmnoKRWcks/q4GkQcYiQn/zz4cQXR9qKa1yUSU8td47eDw5MhOC0P5WkF9+ YpB4H6c/AOHzdL8WI6x6ro8FVn00712TSl9jqJ5wdh5V+wtZwRAVBbTCfIzenQPm9ulF oH1aIUV/u5XfC13VzbeWKQM7pgnbtLI40KCOc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6+Nlz4K5CVynOeUhqGSCw2yzk9Vj1GohEKvgEtpoNmY=; b=LnZPwCtJaK2Rywh8dyVWR/X3M0asSAaT4N7cMsRz2zAdfgCnjUd54Abfr3Wkx7tZP7 rdDg3MQLqHeyn9g5BTZeUDENFwRGUCTWh0eoY3HcvdyfRy/3GBbg+2ej5o5DPtJ7xNXw 4QeASmBMA49t6o6zvJbmPls/OqisM95F+WonG1/5bEQoq4AYBcCZShwavDCBqAIGmuqh SXWCe9DY+8azeXYFDVs17JNQi1Sv3TyQqglXU6alQ79I2qAOAtYeDzgoIyyWRQ+USEjw l13sIjWLTojyfciWzsYIbqe9g18oklszefSp0Ns0cnyOmWLypFAcJQ5UpgIpc2+P+Ep7 MWHg== X-Gm-Message-State: AGi0PuZNEZw5/f8k6tCr+nvINEmCT4YY+QmdY3x23uAgnZ2GNX/yloZW pyjdMAifwz4Qy0zWxlaueMw4mA== X-Google-Smtp-Source: APiQypIw+kLZYZR29St6sa96ZnWn/xIfs5rajLJcjnJIiSIhdDMeGQny0E3DjDsWmmpbrmKvU37PSQ== X-Received: by 2002:a17:90a:d0c3:: with SMTP id y3mr953589pjw.25.1588283167057; Thu, 30 Apr 2020 14:46:07 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:46:06 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 4/7] arm64: dts: rk3399: Move u2phy into root port Date: Fri, 1 May 2020 03:15:26 +0530 Message-Id: <20200430214529.18887-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144607_672106_EA7C2061 X-CRM114-Status: GOOD ( 12.20 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Yes, This is changing the actual device tree u2phy structure but the problem with the current Generic PHY subsystem is unable to find PHY if the PHY node is not part of the root structure. This will be reverted once we support the PHY subsystem to get the PHY even though it is not part of the root node or any other relevant solution. Signed-off-by: Jagan Teki --- arch/arm/dts/rk3399.dtsi | 108 +++++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 74f2c3d490..6c77f25f23 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1387,60 +1387,6 @@ status = "disabled"; }; - u2phy0: usb2-phy@e450 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe450 0x10>; - clocks = <&cru SCLK_USB2PHY0_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy0_480m"; - status = "disabled"; - - u2phy0_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy0_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - - u2phy1: usb2-phy@e460 { - compatible = "rockchip,rk3399-usb2phy"; - reg = <0xe460 0x10>; - clocks = <&cru SCLK_USB2PHY1_REF>; - clock-names = "phyclk"; - #clock-cells = <0>; - clock-output-names = "clk_usbphy1_480m"; - status = "disabled"; - - u2phy1_host: host-port { - #phy-cells = <0>; - interrupts = ; - interrupt-names = "linestate"; - status = "disabled"; - }; - - u2phy1_otg: otg-port { - #phy-cells = <0>; - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - status = "disabled"; - }; - }; - emmc_phy: phy@f780 { compatible = "rockchip,rk3399-emmc-phy"; reg = <0xf780 0x24>; @@ -1462,6 +1408,60 @@ }; }; + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0x0 0xe450 0x0 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@e460 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0x0 0xe460 0x0 0x10>; + clocks = <&cru SCLK_USB2PHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy1_480m"; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + tcphy0: phy@ff7c0000 { compatible = "rockchip,rk3399-typec-phy"; reg = <0x0 0xff7c0000 0x0 0x40000>; From patchwork Thu Apr 30 21:45:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521701 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B67B015AB for ; Thu, 30 Apr 2020 21:46:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 950BD2071C for ; Thu, 30 Apr 2020 21:46:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="eXQDkCw8"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="FjlRFlzN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 950BD2071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JPLYG/235JYOmrUZVRACLCoP58dTOo5yiKuro/UjUw0=; b=eXQDkCw8PFgFiW SbY3Q5XxJGcTilzUFxmKjKpRDojURa0CMC4NiAoMgWM4EmUZsbx3FHWpi6HPw/m36ag0rjidpiDjs g5sVHG9FMVJLrWNhEkIxOXFLL4AedHefLdAIjCTjM6cdS44owjSM5FcJi6501Ol00Kx3t9atlMFJr sjoQ06d52rBFLwWYa2pKAYwrb13INb8Z0hrxgb5ii2Kv9+9j5tJixedvC/gWqEeDMUcdbPTIuEyrN DchTiXwTcYTNHz8WvtHKSwoUkvddPg3MVFEMRm8+i4emkdBsFgdqYXa9X8aBBA/gzN1cWFreOHpXT Ywr9pCK61VNnDq3ILJAA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0Z-00079G-5J; Thu, 30 Apr 2020 21:46:15 +0000 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0W-00076z-Li for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:46:14 +0000 Received: by mail-pj1-x1042.google.com with SMTP id hi11so1452029pjb.3 for ; Thu, 30 Apr 2020 14:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O57oZmFtIDGFaxieo8Ue9ldC2XvrWM9IRe2TgB3VW1I=; b=FjlRFlzNjJ4QTAz88BGvH8yu5KbIB7JZ5s9l4AsGwaDA6lHpuaU/KA1T1PzocQgiZe qWy6qC7pbGdcHvNY3K+WotxKwPtmRtwFpDN+cE/1YgFYmYQFp11pL0WehBKdmv3hAIak /EapCJDMQiwfzjUGrWFPVFVWyEWVM4eloWeFU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O57oZmFtIDGFaxieo8Ue9ldC2XvrWM9IRe2TgB3VW1I=; b=UGJjjIoS4AaQrD8F7J6ml7IQ+NL+PX2d6VAUiDyGVbF9yqhGVZnq1+j2wOl4mTRz10 rJc6LQUEuvI+34diNxZdJxRWpXB3wGvcDdyH/jRFnAaxkVYyAVp58WTEiHYfDV2ImyU4 4VShk6n9HrdXKkb6YWHYtRQiLCF2reoFFCByViidVdbK3ds6ugky7yVGbagVev2CDARW eJRCNQ2n7ObjdQ7OOlet0/7N5bjMfQcgBC73oSqzJPACZdQNW7bs3i7znBj5bDDej1DR uu6uYoCFE+DKX53WcjU+H0SBoL1GusmVA64T3E6cPriA6QR9XzPvbPu8tVM50UKZi24y U+4w== X-Gm-Message-State: AGi0PuYBk/k/vEbgNhPHi1lo7jw8milVfqu1zC4VwRJg9r7gYT8PuAXa 2fhj3D6boNb17O9zn8vFsgkqhQ== X-Google-Smtp-Source: APiQypLzM74/M2BaKixpzy6nbEGMLTrFmBjhc1AhWnvuSaZkp04y6tBVsDpfPjfapjCX6BqCriwYTA== X-Received: by 2002:a17:902:8202:: with SMTP id x2mr1084618pln.287.1588283171707; Thu, 30 Apr 2020 14:46:11 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:46:10 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 5/7] arm64: dts: rk3399: Move pcie_phy into root port Date: Fri, 1 May 2020 03:15:27 +0530 Message-Id: <20200430214529.18887-6-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144612_719842_C4DC40EE X-CRM114-Status: GOOD ( 12.67 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1042 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Yes, This is changing the actual device tree pcie_phy structure but the problem with the current Generic PHY subsystem is unable to find PHY if the PHY node is not part of the root structure and also PHY parent is non-PHY type. This will be reverted once we support the PHY subsystem to get the PHY whose parent has non-PHY type or any other relevant solution.    Signed-off-by: Jagan Teki --- arch/arm/dts/rk3399.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 6c77f25f23..dea76032bf 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -1395,17 +1395,17 @@ #phy-cells = <0>; status = "disabled"; }; + }; - pcie_phy: pcie-phy { - compatible = "rockchip,rk3399-pcie-phy"; - clocks = <&cru SCLK_PCIEPHY_REF>; - clock-names = "refclk"; - #phy-cells = <1>; - resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; - reset-names = "phy"; - status = "disabled"; - }; + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + #phy-cells = <1>; + resets = <&cru SRST_PCIEPHY>; + drive-impedance-ohm = <50>; + reset-names = "phy"; + status = "disabled"; }; u2phy0: usb2-phy@e450 { From patchwork Thu Apr 30 21:45:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521703 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B6C415AB for ; Thu, 30 Apr 2020 21:46:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EE04F2071C for ; Thu, 30 Apr 2020 21:46:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="i3vMfNwk"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Amp9dCYN" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EE04F2071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ddgsTIrS9nbXBeKL37Ce2lh5/Te1pS528qvCCC3XDUE=; b=i3vMfNwkavx11qjnj7EgidZXR5 D9Gz7vqKuGyjKTtOrnmtzWfyplsnF5cPxXfyrNdQmTe8zqUMQj6t3++MGU+lXvKq/KvqioaNck9yq omt32JvL+vVMoiPdCA9LgcG/SgNPF32apjtr8mnx82+zev3PUEIxZui5//OnzkXnBpK5K1CS4ZjtX 7tICXARSBxB+rf2Q6Sq4/RubUOAJ7OLHRrWHECMRsJIcbDBwGSJ+dxtUrBW49h8l1bkEH5u34mdnQ LUpkMi7Ujx7ek/4zXCtmkxPAZq7vM44BUOxZD93vhPYVWr0inTtTcMV23ngEYIBW/bPjAhAQKjx+J h+L13VhA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0d-0007Cb-2u; Thu, 30 Apr 2020 21:46:19 +0000 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0a-0007Av-P6 for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:46:18 +0000 Received: by mail-pl1-x644.google.com with SMTP id h11so2831128plr.11 for ; Thu, 30 Apr 2020 14:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GHqGyS+RUNZNqKAv2qm8I0WbTjNQhsUbrp1rtNyYubk=; b=Amp9dCYNq2Jqi5j1lGLikHCt+3FAkFX2u1fmA1DAuJWOskANXrjeqi2A3QhnQJqRkO AOeYeeAmGwdpoOEJRXVjHWL4PiG74pfTRAuFQ1PXIrtvvMxuJUFID+qPQ7+Chu/bY1JC uFif488aX09YLg87JiVHmRwzrhMjZYj4dKzZc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GHqGyS+RUNZNqKAv2qm8I0WbTjNQhsUbrp1rtNyYubk=; b=ryJ+V1j2NKM+slauVKXPK6mf0tPACIxHDjpYfvxSKZHHepOKfs76kCBAh4DS4OW0q7 TFmfDptZs+Odw9r5/pzghuRW1YOA24j/CNn0PipKjpwwExm4itwDvl65nXHi6mtnnifH rCBuNc88mIIHEc5beHog0ekqmcttBwM/mwGu83nXvZmzWAdIXcxaueIHK7Z7D8a9J6lu cK58JSh948xQjAMaz6iUJgUcUw1oS87g2+WUK2bPb+x//uMwVy6IlINtL6LIxo4d8oaj vzPNRYXOoeqRjAjjZQPj0BBAJ+12nxnaMLTXyN5X74jeCM8xEzzg1aljtQUBWBMmOheT 5YQQ== X-Gm-Message-State: AGi0PuYI2FoUQOuBSp6xot4oXTYRRrK4s4H2vsXRRn23iHFCaX2X27s4 jcMs5OdIxpdZ1DmaaTjzaXKiaA== X-Google-Smtp-Source: APiQypILla+f5XhFs2P0a25DFWI4zk1Fe0UXIougKpkLB47+mVXL3wiMRFv0JI2H3GyqhASGd1evEw== X-Received: by 2002:a17:90a:8c3:: with SMTP id 3mr946549pjn.147.1588283176252; Thu, 30 Apr 2020 14:46:16 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:46:15 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 6/7] pci: rockchip: Switch to generic-phy Date: Fri, 1 May 2020 03:15:28 +0530 Message-Id: <20200430214529.18887-7-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144616_819384_BDECE823 X-CRM114-Status: GOOD ( 13.30 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Now, we have a PCIe PHY driver as part of the Generic PHY framework. Let's use it instead of legacy PHY driver. Signed-off-by: Jagan Teki --- drivers/pci/pcie_rockchip.c | 20 ++++++++++---------- drivers/pci/pcie_rockchip.h | 5 +++++ 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 82a8396e42..3e4ba9635f 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -159,8 +159,6 @@ static int rockchip_pcie_atr_init(struct rockchip_pcie *priv) static int rockchip_pcie_init_port(struct udevice *dev) { struct rockchip_pcie *priv = dev_get_priv(dev); - struct rockchip_pcie_phy *phy = pcie_get_phy(priv); - struct rockchip_pcie_phy_ops *ops = phy_get_ops(phy); u32 cr, val, status; int ret; @@ -185,7 +183,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) return ret; } - ret = ops->init(phy); + ret = generic_phy_init(&priv->pcie_phy); if (ret) { dev_err(dev, "failed to init phy (ret=%d)\n", ret); goto err_exit_phy; @@ -242,7 +240,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG); - ret = ops->power_on(phy); + ret = generic_phy_power_on(&priv->pcie_phy); if (ret) { dev_err(dev, "failed to power on phy (ret=%d)\n", ret); goto err_power_off_phy; @@ -311,9 +309,9 @@ static int rockchip_pcie_init_port(struct udevice *dev) return 0; err_power_off_phy: - ops->power_off(phy); + generic_phy_power_off(&priv->pcie_phy); err_exit_phy: - ops->exit(phy); + generic_phy_exit(&priv->pcie_phy); return ret; } @@ -436,6 +434,12 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) return ret; } + ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy); + if (ret) { + dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret); + return ret; + } + return 0; } @@ -453,10 +457,6 @@ static int rockchip_pcie_probe(struct udevice *dev) if (ret) return ret; - ret = rockchip_pcie_phy_get(dev); - if (ret) - return ret; - ret = rockchip_pcie_set_vpcie(dev); if (ret) return ret; diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h index c3a0a2846d..4b06110bfe 100644 --- a/drivers/pci/pcie_rockchip.h +++ b/drivers/pci/pcie_rockchip.h @@ -9,6 +9,8 @@ * */ +#include + #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) @@ -126,6 +128,9 @@ struct rockchip_pcie { struct udevice *vpcie3v3; struct udevice *vpcie1v8; struct udevice *vpcie0v9; + + /* phy */ + struct phy pcie_phy; }; int rockchip_pcie_phy_get(struct udevice *dev); From patchwork Thu Apr 30 21:45:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 11521705 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CC50913 for ; Thu, 30 Apr 2020 21:46:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28F212071C for ; Thu, 30 Apr 2020 21:46:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="IRrJ8bw8"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Af8s7f5o" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 28F212071C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=DRgpAHZYscfG+f9ApSgBzU65FXuf6dUaHiYRWkzxP3I=; b=IRrJ8bw81Hq+PHRvqMLNBxLxiS w6u9ni4OUw2Sei3FWY0CvV54vtAS1ex0c+HX8hB2HDqfUdGDmAj69ha+cROOc9xVD6ZkeqDpziMwt pTI8BtcSGPLsJQjSiikeHzJsJrCz79MJ4R3fNtuj+FVnSV4f+DwjGQunqhR3+ySnmOC99j12XNCyK Yt0vzQ57kMdUqvb1+wfMiYRV7XlVDmQtkadbnVSn9MzKMVT7J2ZIJnPWMgtLLQoRwxhjc6IIY0IHt /NrImql1R6pX2vdtbD/ySPh7M9WDHXqNyZoxxz01Rvog7M7qgG4GZjg7+qcFpn3jupjb+U/z5sa88 raYichOg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0i-0007Gl-Uc; Thu, 30 Apr 2020 21:46:24 +0000 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jUH0f-0007ES-H5 for linux-rockchip@lists.infradead.org; Thu, 30 Apr 2020 21:46:23 +0000 Received: by mail-pg1-x543.google.com with SMTP id d3so3556456pgj.6 for ; Thu, 30 Apr 2020 14:46:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xMV5+war9q+lO4Dguz3Z/0skJPu2J+02fu/fMUfRfPc=; b=Af8s7f5o5hn0jLL0yDDDOROqen1FvdDYkiDy40uR5VvrlyiJd9zZG69giACQ5OlAWM HA7Zcoz3UTS98XVQRsYhNVQD5Hluy0uL55er06+fHfSJGZ4I3ZdkNpmk1OoKJIBFG3nh C75Fyru372QHgdQlCidMZRgz6nT6zUBII3Izw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xMV5+war9q+lO4Dguz3Z/0skJPu2J+02fu/fMUfRfPc=; b=Ti98NcZkoRXKkaEtLqTJ3TjPM/WsAppi0kyg3XvcuBbeD5LldVdiyq4GjVOUUlF3DI lLloaeY+QvCZA8uEWUt39v6+Fb+A0xkEKcZ/BfU63xf3azJuFA5XMCB1/Ezgj7EdiECM +BYpy+l+Uc7yIzWVpg/p20GPShmdceoAROG7bZbkNFLQfxbq3WiHrnyj/xAOX1Vx3FKY L7cHRfCUnt7m5WdO5obNnL+zafcvbcM9RUOby0QF7Ue+sdENd77B1QAyhy2pLomuj9XM JTRoy2Iwg8nvE4e0MvcegmaQif4s9SbgHde3twZLX95M5Xv+PmSXsDauH3MhpGSlunQE GzoA== X-Gm-Message-State: AGi0PuZSBAtKKRpuzB/BDmVTNZoH8RjmbIAWi4/apQINR/iloIiF+4Ex L7W+1nn1+r2S51a423cE3hlycw== X-Google-Smtp-Source: APiQypKbPJnXAg7ywE7cDB7eYZNoeE4syQ5LtfGv9kQt1ID+BUFj3W03iPXUK2XqEH1l7j3dssbKIA== X-Received: by 2002:a63:7742:: with SMTP id s63mr1014611pgc.133.1588283180854; Thu, 30 Apr 2020 14:46:20 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c809:c7d5:a9f2:11c6:8c6c:2861]) by smtp.gmail.com with ESMTPSA id p64sm615243pjp.7.2020.04.30.14.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 14:46:19 -0700 (PDT) From: Jagan Teki To: Kever Yang , Simon Glass , Philipp Tomsich , Tom Rini , Frank Wang , William Wu , Shawn Lin , Heiko Stuebner , Patrice Chotard Subject: [RFC 7/7] pci: rockchip: Drop legacy PHY driver Date: Fri, 1 May 2020 03:15:29 +0530 Message-Id: <20200430214529.18887-8-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200430214529.18887-1-jagan@amarulasolutions.com> References: <20200430214529.18887-1-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200430_144621_573240_8072F238 X-CRM114-Status: GOOD ( 13.76 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:543 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: u-boot@lists.denx.de, linux-amarula@amarulasolutions.com, Jagan Teki , linux-rockchip@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Drop the legacy PHY driver and it's associated code since the PHY handling driver now part of Generic PHY framework. Signed-off-by: Jagan Teki --- drivers/pci/Makefile | 2 +- drivers/pci/pcie_rockchip.c | 75 +++++++++++- drivers/pci/pcie_rockchip.h | 147 ----------------------- drivers/pci/pcie_rockchip_phy.c | 205 -------------------------------- 4 files changed, 74 insertions(+), 355 deletions(-) delete mode 100644 drivers/pci/pcie_rockchip.h delete mode 100644 drivers/pci/pcie_rockchip_phy.c diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 955351c5c2..493e9354dd 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -43,4 +43,4 @@ obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o -obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o pcie_rockchip_phy.o +obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 3e4ba9635f..cf24479f85 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -25,10 +26,80 @@ #include #include -#include "pcie_rockchip.h" - DECLARE_GLOBAL_DATA_PTR; +#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) +#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) + +#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) +#define PCIE_CLIENT_BASE 0x0 +#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) +#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) +#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) +#define PCIE_CLIENT_BASIC_STATUS1 0x0048 +#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) +#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) +#define PCIE_LINK_UP(x) \ + (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) +#define PCIE_RC_NORMAL_BASE 0x800000 +#define PCIE_LM_BASE 0x900000 +#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) +#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 +#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) +#define PCIE_LM_RCBARPIE BIT(19) +#define PCIE_LM_RCBARPIS BIT(20) +#define PCIE_RC_BASE 0xa00000 +#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) +#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) +#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) +#define PCIE_ATR_BASE 0xc00000 +#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) +#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) +#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) +#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) +#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) +#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) +#define PCIE_ATR_HDR_MEM 0x2 +#define PCIE_ATR_HDR_IO 0x6 +#define PCIE_ATR_HDR_CFG_TYPE0 0xa +#define PCIE_ATR_HDR_CFG_TYPE1 0xb +#define PCIE_ATR_HDR_RID BIT(23) + +#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) +#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) + +struct rockchip_pcie { + fdt_addr_t axi_base; + fdt_addr_t apb_base; + int first_busno; + struct udevice *dev; + + /* resets */ + struct reset_ctl core_rst; + struct reset_ctl mgmt_rst; + struct reset_ctl mgmt_sticky_rst; + struct reset_ctl pipe_rst; + struct reset_ctl pm_rst; + struct reset_ctl pclk_rst; + struct reset_ctl aclk_rst; + + /* gpio */ + struct gpio_desc ep_gpio; + + /* vpcie regulators */ + struct udevice *vpcie12v; + struct udevice *vpcie3v3; + struct udevice *vpcie1v8; + struct udevice *vpcie0v9; + + /* phy */ + struct phy pcie_phy; +}; + static int rockchip_pcie_off_conf(pci_dev_t bdf, uint offset) { unsigned int bus = PCI_BUS(bdf); diff --git a/drivers/pci/pcie_rockchip.h b/drivers/pci/pcie_rockchip.h deleted file mode 100644 index 4b06110bfe..0000000000 --- a/drivers/pci/pcie_rockchip.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Rockchip PCIe Headers - * - * Copyright (c) 2016 Rockchip, Inc. - * Copyright (c) 2020 Amarula Solutions(India) - * Copyright (c) 2020 Jagan Teki - * Copyright (c) 2019 Patrick Wildt - * - */ - -#include - -#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) -#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val) - -#define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4) -#define PCIE_CLIENT_BASE 0x0 -#define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) -#define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) -#define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) -#define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) -#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) -#define PCIE_CLIENT_BASIC_STATUS1 0x0048 -#define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20) -#define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20) -#define PCIE_LINK_UP(x) \ - (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_RC_NORMAL_BASE 0x800000 -#define PCIE_LM_BASE 0x900000 -#define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) -#define PCIE_LM_VENDOR_ROCKCHIP 0x1d87 -#define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) -#define PCIE_LM_RCBARPIE BIT(19) -#define PCIE_LM_RCBARPIS BIT(20) -#define PCIE_RC_BASE 0xa00000 -#define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4) -#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 -#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 -#define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc) -#define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10) -#define PCIE_ATR_BASE 0xc00000 -#define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) -#define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) -#define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) -#define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) -#define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) -#define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) -#define PCIE_ATR_HDR_MEM 0x2 -#define PCIE_ATR_HDR_IO 0x6 -#define PCIE_ATR_HDR_CFG_TYPE0 0xa -#define PCIE_ATR_HDR_CFG_TYPE1 0xb -#define PCIE_ATR_HDR_RID BIT(23) - -#define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) -#define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) - -/* - * The higher 16-bit of this register is used for write protection - * only if BIT(x + 16) set to 1 the BIT(x) can be written. - */ -#define HIWORD_UPDATE_MASK(val, mask, shift) \ - ((val) << (shift) | (mask) << ((shift) + 16)) - -#define PHY_CFG_DATA_SHIFT 7 -#define PHY_CFG_ADDR_SHIFT 1 -#define PHY_CFG_DATA_MASK 0xf -#define PHY_CFG_ADDR_MASK 0x3f -#define PHY_CFG_RD_MASK 0x3ff -#define PHY_CFG_WR_ENABLE 1 -#define PHY_CFG_WR_DISABLE 1 -#define PHY_CFG_WR_SHIFT 0 -#define PHY_CFG_WR_MASK 1 -#define PHY_CFG_PLL_LOCK 0x10 -#define PHY_CFG_CLK_TEST 0x10 -#define PHY_CFG_CLK_SCC 0x12 -#define PHY_CFG_SEPE_RATE BIT(3) -#define PHY_CFG_PLL_100M BIT(3) -#define PHY_PLL_LOCKED BIT(9) -#define PHY_PLL_OUTPUT BIT(10) -#define PHY_LANE_IDLE_OFF 0x1 -#define PHY_LANE_IDLE_MASK 0x1 -#define PHY_LANE_IDLE_A_SHIFT 3 -#define PHY_LANE_IDLE_B_SHIFT 4 -#define PHY_LANE_IDLE_C_SHIFT 5 -#define PHY_LANE_IDLE_D_SHIFT 6 - -#define PCIE_PHY_CONF 0xe220 -#define PCIE_PHY_STATUS 0xe2a4 -#define PCIE_PHY_LANEOFF 0xe214 - -struct rockchip_pcie_phy { - void *reg_base; - struct clk refclk; - struct reset_ctl phy_rst; - struct rockchip_pcie_phy_ops *ops; -}; - -struct rockchip_pcie_phy_ops { - int (*init)(struct rockchip_pcie_phy *phy); - int (*exit)(struct rockchip_pcie_phy *phy); - int (*power_on)(struct rockchip_pcie_phy *phy); - int (*power_off)(struct rockchip_pcie_phy *phy); -}; - -struct rockchip_pcie { - fdt_addr_t axi_base; - fdt_addr_t apb_base; - int first_busno; - struct udevice *dev; - struct rockchip_pcie_phy rk_phy; - struct rockchip_pcie_phy *phy; - - /* resets */ - struct reset_ctl core_rst; - struct reset_ctl mgmt_rst; - struct reset_ctl mgmt_sticky_rst; - struct reset_ctl pipe_rst; - struct reset_ctl pm_rst; - struct reset_ctl pclk_rst; - struct reset_ctl aclk_rst; - - /* gpio */ - struct gpio_desc ep_gpio; - - /* vpcie regulators */ - struct udevice *vpcie12v; - struct udevice *vpcie3v3; - struct udevice *vpcie1v8; - struct udevice *vpcie0v9; - - /* phy */ - struct phy pcie_phy; -}; - -int rockchip_pcie_phy_get(struct udevice *dev); - -inline struct rockchip_pcie_phy *pcie_get_phy(struct rockchip_pcie *pcie) -{ - return pcie->phy; -} - -inline -struct rockchip_pcie_phy_ops *phy_get_ops(struct rockchip_pcie_phy *phy) -{ - return (struct rockchip_pcie_phy_ops *)phy->ops; -} diff --git a/drivers/pci/pcie_rockchip_phy.c b/drivers/pci/pcie_rockchip_phy.c deleted file mode 100644 index 47f5d6c7e3..0000000000 --- a/drivers/pci/pcie_rockchip_phy.c +++ /dev/null @@ -1,205 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Rockchip PCIe PHY driver - * - * Copyright (c) 2016 Rockchip, Inc. - * Copyright (c) 2020 Amarula Solutions(India) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pcie_rockchip.h" - -DECLARE_GLOBAL_DATA_PTR; - -static void phy_wr_cfg(struct rockchip_pcie_phy *phy, u32 addr, u32 data) -{ - u32 reg; - - reg = HIWORD_UPDATE_MASK(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT); - reg |= HIWORD_UPDATE_MASK(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_CONF); - - udelay(1); - - reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_ENABLE, - PHY_CFG_WR_MASK, - PHY_CFG_WR_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_CONF); - - udelay(1); - - reg = HIWORD_UPDATE_MASK(PHY_CFG_WR_DISABLE, - PHY_CFG_WR_MASK, - PHY_CFG_WR_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_CONF); -} - -static int rockchip_pcie_phy_power_on(struct rockchip_pcie_phy *phy) -{ - int ret = 0; - u32 reg, status; - - ret = reset_deassert(&phy->phy_rst); - if (ret) { - dev_err(dev, "failed to assert phy reset\n"); - return ret; - } - - reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, - PHY_CFG_ADDR_MASK, - PHY_CFG_ADDR_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_CONF); - - reg = HIWORD_UPDATE_MASK(!PHY_LANE_IDLE_OFF, - PHY_LANE_IDLE_MASK, - PHY_LANE_IDLE_A_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); - - ret = -EINVAL; - ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, - status, - status & PHY_PLL_LOCKED, - 20 * 1000, - 50); - if (ret) { - dev_err(&phy->dev, "pll lock timeout!\n"); - goto err_pll_lock; - } - - phy_wr_cfg(phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE); - phy_wr_cfg(phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M); - - ret = -ETIMEDOUT; - ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, - status, - !(status & PHY_PLL_OUTPUT), - 20 * 1000, - 50); - if (ret) { - dev_err(&phy->dev, "pll output enable timeout!\n"); - goto err_pll_lock; - } - - reg = HIWORD_UPDATE_MASK(PHY_CFG_PLL_LOCK, - PHY_CFG_ADDR_MASK, - PHY_CFG_ADDR_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_CONF); - - ret = -EINVAL; - ret = readl_poll_sleep_timeout(phy->reg_base + PCIE_PHY_STATUS, - status, - status & PHY_PLL_LOCKED, - 20 * 1000, - 50); - if (ret) { - dev_err(&phy->dev, "pll relock timeout!\n"); - goto err_pll_lock; - } - - return 0; - -err_pll_lock: - reset_assert(&phy->phy_rst); - return ret; -} - -static int rockchip_pcie_phy_power_off(struct rockchip_pcie_phy *phy) -{ - int ret; - u32 reg; - - reg = HIWORD_UPDATE_MASK(PHY_LANE_IDLE_OFF, - PHY_LANE_IDLE_MASK, - PHY_LANE_IDLE_A_SHIFT); - writel(reg, phy->reg_base + PCIE_PHY_LANEOFF); - - ret = reset_assert(&phy->phy_rst); - if (ret) { - dev_err(dev, "failed to assert phy reset\n"); - return ret; - } - - return 0; -} - -static int rockchip_pcie_phy_init(struct rockchip_pcie_phy *phy) -{ - int ret; - - ret = clk_enable(&phy->refclk); - if (ret) { - dev_err(dev, "failed to enable refclk clock\n"); - return ret; - } - - ret = reset_assert(&phy->phy_rst); - if (ret) { - dev_err(dev, "failed to assert phy reset\n"); - goto err_reset; - } - - return 0; - -err_reset: - clk_disable(&phy->refclk); - return ret; -} - -static int rockchip_pcie_phy_exit(struct rockchip_pcie_phy *phy) -{ - clk_disable(&phy->refclk); - - return 0; -} - -static struct rockchip_pcie_phy_ops pcie_phy_ops = { - .init = rockchip_pcie_phy_init, - .power_on = rockchip_pcie_phy_power_on, - .power_off = rockchip_pcie_phy_power_off, - .exit = rockchip_pcie_phy_exit, -}; - -int rockchip_pcie_phy_get(struct udevice *dev) -{ - struct rockchip_pcie *priv = dev_get_priv(dev); - struct rockchip_pcie_phy *phy_priv = &priv->rk_phy; - ofnode phy_node; - u32 phandle; - int ret; - - phandle = dev_read_u32_default(dev, "phys", 0); - phy_node = ofnode_get_by_phandle(phandle); - if (!ofnode_valid(phy_node)) { - dev_err(dev, "failed to found pcie-phy\n"); - return -ENODEV; - } - - phy_priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - - ret = clk_get_by_index_nodev(phy_node, 0, &phy_priv->refclk); - if (ret) { - dev_err(dev, "failed to get refclk clock phandle\n"); - return ret; - } - - ret = reset_get_by_index_nodev(phy_node, 0, &phy_priv->phy_rst); - if (ret) { - dev_err(dev, "failed to get phy reset phandle\n"); - return ret; - } - - phy_priv->ops = &pcie_phy_ops; - priv->phy = phy_priv; - - return 0; -}