From patchwork Mon May 4 06:34:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11525119 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C730492A for ; Mon, 4 May 2020 06:33:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A682C20746 for ; Mon, 4 May 2020 06:33:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="dSDzQDmh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727800AbgEDGde (ORCPT ); Mon, 4 May 2020 02:33:34 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:4148 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbgEDGde (ORCPT ); Mon, 4 May 2020 02:33:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 03 May 2020 23:33:21 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 03 May 2020 23:33:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 03 May 2020 23:33:33 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 4 May 2020 06:33:33 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 4 May 2020 06:33:33 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 03 May 2020 23:33:32 -0700 From: Nagarjuna Kristam To: , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V2 1/3] dt-bindings: usb: tegra-xudc: Add Tegra194 XUSB controller support Date: Mon, 4 May 2020 12:04:39 +0530 Message-ID: <1588574081-23160-2-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> References: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1588574001; bh=Mc5OAfI8+/1794bFfJqfKbAf+lykMUer/jaZaREQkMg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dSDzQDmhbZCa3bQ0fz7MWFSocUT2MMbo2dy5ljVWYJYqfboV8CwQfRY8XEyzTKaJu i6i6fmzryAUwKnk8NF9vt5Xbpziun0wsHRgHXMTsQjBBfo5qxch4Mf/I2h/TNOgSPR vhadA9Ch4f+yz5uvL5AoZXRSqf8WX2yuSiRrFAulheM78viaLao7bGRLmFUnet4yuI 06hHKhqY68QIWZEkYj0cSSBLC4Q7cixdAUynmmJr+hXd9qSp5aBjAEcCq9c3BEPtpd U0iClsD69b0kDeQoFE0wxgbQUzvf/ZJK/jcafq6RrUzwL9j+DcP+/06iFUq8ptdXgn 7IpRoNHSJgRHw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Extend the Tegra XUSB controller device tree binding with Tegra194 support. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding Acked-by: Rob Herring --- V2: - Added Acked-by updates to commit message. --- Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml index b84ed8e..75ea946 100644 --- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml @@ -21,6 +21,7 @@ properties: - enum: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 + - nvidia,tegra194-xudc # For Tegra194 reg: minItems: 2 @@ -144,6 +145,7 @@ allOf: contains: enum: - nvidia,tegra186-xudc + - nvidia,tegra194-xudc then: properties: reg: From patchwork Mon May 4 06:34:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11525121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29C6514B4 for ; Mon, 4 May 2020 06:33:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1266720746 for ; Mon, 4 May 2020 06:33:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="h1qhi0oT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727838AbgEDGdh (ORCPT ); Mon, 4 May 2020 02:33:37 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19627 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbgEDGdh (ORCPT ); Mon, 4 May 2020 02:33:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 03 May 2020 23:31:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 03 May 2020 23:33:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 03 May 2020 23:33:36 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 4 May 2020 06:33:36 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 4 May 2020 06:33:36 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 03 May 2020 23:33:35 -0700 From: Nagarjuna Kristam To: , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V2 2/3] usb: gadget: tegra-xudc: Add Tegra194 support Date: Mon, 4 May 2020 12:04:40 +0530 Message-ID: <1588574081-23160-3-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> References: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1588573889; bh=B/ZJ2skrpSXMvGZJlSiYl3vlRxjANNqiNcO1sk0Y1NY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=h1qhi0oTWOd5yKzgJeIgfCsb7GvnGBWGhN4FmIGV8K2+a2qGoeuyFRgpOPke7Ur1D EHDYmBC1H6R/BJPTGaVJ1TNCekvREuDGOhUgt88OBkk5+Ig9lRp7mYZ2gxlN663nZk gjvFb8451NVcnxdQalQ4dhJNEcH2gzSDiRQpu0xC5JzKaxu8dCjPmEYvA13XaVQOrp Boau1yt4k2GY48Y65tKZaq6sIfGT9rQJDUzWhN11TS67x2oHhd0iSJv56E5n3lU6Co KY15RFu9Bw10lVqIboXz0dj9eCLrgT2OrFPMLmde8FKz1jxIjbL3uApJYdsEiQMGX1 DATID44yy/10w== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This commit adds support for XUSB device mode controller support on Tegra194 SoC. This is very similar to the existing Tegra186 XUDC, with lpm support added in addition. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V2: - Added Acked-by updates to commit message. - Re-used T186 clock names for T194 SoC data. --- drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 52a6add..04c6a06 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3522,6 +3522,19 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra194_xudc_soc_data = { + .clock_names = tegra186_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3531,6 +3544,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra186-xudc", .data = &tegra186_xudc_soc_data }, + { + .compatible = "nvidia,tegra194-xudc", + .data = &tegra194_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match); From patchwork Mon May 4 06:34:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11525123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A46614B4 for ; Mon, 4 May 2020 06:33:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4AF9A20735 for ; Mon, 4 May 2020 06:33:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="qDoNlBQv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbgEDGdk (ORCPT ); Mon, 4 May 2020 02:33:40 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:5294 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbgEDGdk (ORCPT ); Mon, 4 May 2020 02:33:40 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 03 May 2020 23:32:30 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 03 May 2020 23:33:39 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 03 May 2020 23:33:39 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 4 May 2020 06:33:39 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 4 May 2020 06:33:39 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 03 May 2020 23:33:38 -0700 From: Nagarjuna Kristam To: , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V2 3/3] usb: gadget: tegra-xudc: add port_speed_quirk Date: Mon, 4 May 2020 12:04:41 +0530 Message-ID: <1588574081-23160-4-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> References: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1588573950; bh=4S4+7Q1v8T97/LJp/rVsk/6bGlUDNI4LPsIAgboFSW4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qDoNlBQvezAUQpRut45dNd8S9jGPRljoLdvzs5MyZDQgfl3XhCH2hXnTfNA+93iFa 4Dvz7e7HkV08Lb3gkab5q5BafjbPjeaPh/n1OS/c0dNONGwsGICOUWO4Hq+mDDquCO oZaKLQvWYTs0REqOCafWluci8S0rBgu2NZqaTe0WDUtGcXwANlK9Jr9/eIyJMOJw2j +4+/viBqLs+i3LwJU3dahQ3QeQ8MS/I7s70y1hU7pFRBOtFdAz6ERZm4KlgohNZB3d ZtZP6insLjvASX4+GSMQLOSWq/1T8MkLIXx2p74udEg31Wr/souEChjuw22fFyVwQz lx95Ey1Q6ctiA== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org OTG port on Tegra194 supports GEN1 speeds when in device mode and GEN2 speeds when in host mode. dd port_speed_quirk that configures port to GEN1/GEN2 speds, corresponding to the mode. Based on work by WayneChang Signed-off-by: Nagarjuna Kristam --- V2: - Updated commit message to explain on why this change is needed. - Fixed checkpatch errors. --- drivers/usb/gadget/udc/tegra-xudc.c | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 04c6a06..8111b32 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -158,6 +158,30 @@ #define SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK GENMASK(7, 0) #define SSPX_CORE_CNT32_POLL_TBURST_MAX(x) ((x) & \ SSPX_CORE_CNT32_POLL_TBURST_MAX_MASK) +#define SSPX_CORE_CNT56 0x6fc +#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(x) ((x) & \ + SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK) +#define SSPX_CORE_CNT57 0x700 +#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(x) ((x) & \ + SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK) +#define SSPX_CORE_CNT65 0x720 +#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK) +#define SSPX_CORE_CNT66 0x724 +#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK) +#define SSPX_CORE_CNT67 0x728 +#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(x) ((x) & \ + SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK) +#define SSPX_CORE_CNT72 0x73c +#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK GENMASK(19, 0) +#define SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(x) ((x) & \ + SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK) #define SSPX_CORE_PADCTL4 0x750 #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK GENMASK(19, 0) #define SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3(x) ((x) & \ @@ -530,6 +554,7 @@ struct tegra_xudc_soc { bool invalid_seq_num; bool pls_quirk; bool port_reset_quirk; + bool port_speed_quirk; bool has_ipfs; }; @@ -599,6 +624,78 @@ static inline void dump_trb(struct tegra_xudc *xudc, const char *type, trb->control); } +static void tegra_xudc_limit_port_speed(struct tegra_xudc *xudc) +{ + u32 val; + + /* limit port speed to gen 1 */ + val = xudc_readl(xudc, SSPX_CORE_CNT56); + val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x260); + xudc_writel(xudc, val, SSPX_CORE_CNT56); + + val = xudc_readl(xudc, SSPX_CORE_CNT57); + val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x6D6); + xudc_writel(xudc, val, SSPX_CORE_CNT57); + + val = xudc_readl(xudc, SSPX_CORE_CNT65); + val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); + val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT66); + val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); + val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT67); + val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); + val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x4B0); + xudc_writel(xudc, val, SSPX_CORE_CNT67); + + val = xudc_readl(xudc, SSPX_CORE_CNT72); + val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); + val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x10); + xudc_writel(xudc, val, SSPX_CORE_CNT72); +} + +static void tegra_xudc_restore_port_speed(struct tegra_xudc *xudc) +{ + u32 val; + + /* restore port speed to gen2 */ + val = xudc_readl(xudc, SSPX_CORE_CNT56); + val &= ~(SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT56_SCD_BIT0_TRPT_MAX(0x438); + xudc_writel(xudc, val, SSPX_CORE_CNT56); + + val = xudc_readl(xudc, SSPX_CORE_CNT57); + val &= ~(SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX_MASK); + val |= SSPX_CORE_CNT57_SCD_BIT1_TRPT_MAX(0x528); + xudc_writel(xudc, val, SSPX_CORE_CNT57); + + val = xudc_readl(xudc, SSPX_CORE_CNT65); + val &= ~(SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID_MASK); + val |= SSPX_CORE_CNT65_TX_SCD_END_TRPT_MID(0xE10); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT66); + val &= ~(SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID_MASK); + val |= SSPX_CORE_CNT66_TX_SCD_BIT0_TRPT_MID(0x348); + xudc_writel(xudc, val, SSPX_CORE_CNT66); + + val = xudc_readl(xudc, SSPX_CORE_CNT67); + val &= ~(SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID_MASK); + val |= SSPX_CORE_CNT67_TX_SCD_BIT1_TRPT_MID(0x5a0); + xudc_writel(xudc, val, SSPX_CORE_CNT67); + + val = xudc_readl(xudc, SSPX_CORE_CNT72); + val &= ~(SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT_MASK); + val |= SSPX_CORE_CNT72_SCD_LFPS_TIMEOUT(0x1c21); + xudc_writel(xudc, val, SSPX_CORE_CNT72); +} + static void tegra_xudc_device_mode_on(struct tegra_xudc *xudc) { int err; @@ -631,6 +728,9 @@ static void tegra_xudc_device_mode_off(struct tegra_xudc *xudc) reinit_completion(&xudc->disconnect_complete); + if (xudc->soc->port_speed_quirk) + tegra_xudc_restore_port_speed(xudc); + phy_set_mode_ext(xudc->curr_utmi_phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); pls = (xudc_readl(xudc, PORTSC) & PORTSC_PLS_MASK) >> @@ -3274,6 +3374,9 @@ static void tegra_xudc_device_params_init(struct tegra_xudc *xudc) xudc_writel(xudc, val, BLCG); } + if (xudc->soc->port_speed_quirk) + tegra_xudc_limit_port_speed(xudc); + /* Set a reasonable U3 exit timer value. */ val = xudc_readl(xudc, SSPX_CORE_PADCTL4); val &= ~(SSPX_CORE_PADCTL4_RXDAT_VLD_TIMEOUT_U3_MASK); @@ -3506,6 +3609,7 @@ static struct tegra_xudc_soc tegra210_xudc_soc_data = { .invalid_seq_num = true, .pls_quirk = true, .port_reset_quirk = true, + .port_speed_quirk = false, .has_ipfs = true, }; @@ -3519,6 +3623,7 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .invalid_seq_num = false, .pls_quirk = false, .port_reset_quirk = false, + .port_speed_quirk = false, .has_ipfs = false, }; @@ -3532,6 +3637,7 @@ static struct tegra_xudc_soc tegra194_xudc_soc_data = { .invalid_seq_num = false, .pls_quirk = false, .port_reset_quirk = false, + .port_speed_quirk = true, .has_ipfs = false, };