From patchwork Sat May 9 12:38:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 11538245 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DFE79139A for ; Sat, 9 May 2020 12:39:17 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BDEE3208CA for ; Sat, 9 May 2020 12:39:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zjLMX220" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BDEE3208CA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A0936E342; Sat, 9 May 2020 12:39:14 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5C9016E343 for ; Sat, 9 May 2020 12:39:13 +0000 (UTC) Received: by mail-pl1-x643.google.com with SMTP id t7so1916313plr.0 for ; Sat, 09 May 2020 05:39:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UBfVPrIAEP/brziXj/j+5AZneielsV7rQkY6yeq3xcM=; b=zjLMX220WnGuheyAsAr6KibTQcOAvAXjG1f0UDfBkZkZn5dioDKlD81SKRfYkH2zx4 NdnNKdC0rzFLBCpnnB+KLC/DKyORhVE5+Dl4rs9roSKBuo9ZpnmppFPYNlGl403aoRXG V5gkDgr6aWOVkA2Im5nwt+8UaCDU6T/iaHcII37R3zJN2wyGLWiQbiVfiV5t2IBcIkUJ z9PLy960yrmTSkhOY66jp6wvofov0iyMGttqrTtjqph5iP9/4zxMuU15pj11dE5TqnMC 1tJTrRXI/hDq0RtiMitPC0DQeooVsBICHZap3SGoguoUsn8iXxW5jWTgnpSdEOtW8Pze pQ3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UBfVPrIAEP/brziXj/j+5AZneielsV7rQkY6yeq3xcM=; b=YEb5fYNYYJWlC3AFVcSkzqnjk6hB3MGabxPZK+ZtetBfv/ZFDal6QeskFTCYOOdXwB b/vCdpMUn1KzUkbwuezC9Y8QBVQSwWldxLqRqONwrw6I4BElFDV5CvPU3GksrhJF/wrI FDloy+wiTN471VsvhRl3hoprcAJiqQL6NC3LLiqgMVVOYYm0CEtIzfJLIroWdPWu/6RW cefdlZ7I6/sYL8GjMVpL5Fmpr1Gr7yCr9OnaClBlGY0mh2AnTnnuavL2XsSUXLJdbiWl WinEBUA+0q2pCwwBtDHg9Fgolc2riAhtxOgXnbi8ao18pvanyxKprnk7IT+AebDAIpFi oZWA== X-Gm-Message-State: AGi0Pub4gyOEdNru+wp93nmqlY6t/lnnKyTSDtjB/tzGeNaRyz7I1r6t 1MlI/9UgJkVM+VRxillTYdemlg== X-Google-Smtp-Source: APiQypLceye+Wufp5TMuhvfgKKh6Ztq3ThomILv3leVPMCH9FNbt1JOgwbotVYVzXjYde2A2H2PtJA== X-Received: by 2002:a17:90a:fa3:: with SMTP id 32mr11550550pjz.224.1589027952992; Sat, 09 May 2020 05:39:12 -0700 (PDT) Received: from localhost.localdomain ([80.251.214.228]) by smtp.gmail.com with ESMTPSA id o6sm4447828pfp.172.2020.05.09.05.39.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2020 05:39:12 -0700 (PDT) From: Shawn Guo To: Rob Clark , Sean Paul , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/2] drm/msm/a4xx: add adreno a405 support Date: Sat, 9 May 2020 20:38:45 +0800 Message-Id: <20200509123846.27932-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200509123846.27932-1-shawn.guo@linaro.org> References: <20200509123846.27932-1-shawn.guo@linaro.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , Brian Masney MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" It adds support for adreno a405 found on MSM8939. The adreno_is_a430() check in adreno_submit() needs an extension to cover a405. The downstream driver suggests it should cover the whole a4xx generation. That's why it gets changed to adreno_is_a4xx(), while a420 is not tested though. Signed-off-by: Shawn Guo Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 29 +++++++++++++--------- drivers/gpu/drm/msm/adreno/adreno_device.c | 11 ++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 4 files changed, 34 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 253d8d85daad..70de59751188 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -66,19 +66,22 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) } } - for (i = 0; i < 4; i++) { - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i), - 0x00000922); - } + /* No CCU for A405 */ + if (!adreno_is_a405(adreno_gpu)) { + for (i = 0; i < 4; i++) { + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i), + 0x00000922); + } - for (i = 0; i < 4; i++) { - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i), - 0x00000000); - } + for (i = 0; i < 4; i++) { + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i), + 0x00000000); + } - for (i = 0; i < 4; i++) { - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i), - 0x00000001); + for (i = 0; i < 4; i++) { + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i), + 0x00000001); + } } gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222); @@ -137,7 +140,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu) uint32_t *ptr, len; int i, ret; - if (adreno_is_a420(adreno_gpu)) { + if (adreno_is_a405(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + } else if (adreno_is_a420(adreno_gpu)) { gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4); gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index cb3a6e597d76..b69757383965 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -92,6 +92,17 @@ static const struct adreno_info gpulist[] = { .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, + }, { + .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .revn = 405, + .name = "A405", + .fw = { + [ADRENO_FW_PM4] = "a420_pm4.fw", + [ADRENO_FW_PFP] = "a420_pfp.fw", + }, + .gmem = SZ_256K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), .revn = 420, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1d5c43c22269..3ddbf507941c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -459,7 +459,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, break; /* fall-thru */ case MSM_SUBMIT_CMD_BUF: - OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? + OUT_PKT3(ring, adreno_is_a4xx(adreno_gpu) ? CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); OUT_RING(ring, submit->cmd[i].size); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 9ff4e550e7bd..35f744834ea9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -202,6 +202,11 @@ static inline bool adreno_is_a4xx(struct adreno_gpu *gpu) return (gpu->revn >= 400) && (gpu->revn < 500); } +static inline int adreno_is_a405(struct adreno_gpu *gpu) +{ + return gpu->revn == 405; +} + static inline int adreno_is_a420(struct adreno_gpu *gpu) { return gpu->revn == 420; From patchwork Sat May 9 12:38:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 11538249 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C728139F for ; Sat, 9 May 2020 12:39:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2AE5521775 for ; Sat, 9 May 2020 12:39:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="MhpdoIXt" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AE5521775 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 507A46E347; Sat, 9 May 2020 12:39:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by gabe.freedesktop.org (Postfix) with ESMTPS id 218956E347 for ; Sat, 9 May 2020 12:39:17 +0000 (UTC) Received: by mail-pj1-x1044.google.com with SMTP id fu13so5487693pjb.5 for ; Sat, 09 May 2020 05:39:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/yCbEu8wYmRlZF9ujoXFy28Dup9bbLQcU0p7hOZmCyc=; b=MhpdoIXtW5dYBFtM5R0tE1kmldXbirdOFixtpedkfZT9ws7cUxUGweiVtFZ1OQB2sZ 0PTElqhI9WCoDctLBp0tn2Fz881IUaH44fClqBDmlqWNBffc8pkgn84KCyvZuZz2rToe NMTTdEHyxU+nttny3JdCfbav52xtMT+X7ObdwnrZSLBerJpPCQ3z/sy0eofBfXccPPFr NizNB22hHFe5WT6H2UI9qKFr7h1LqZG/7WkeGCH8x5DEhgCZMqPOb3OEpux026ruUztS cJBDNR7GhlA9QEWk7CAklQ7avwtj1LVGJpXDlcfVwiVNxJDXu0VKWfgimwBg+ZC3Bg/R PWyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/yCbEu8wYmRlZF9ujoXFy28Dup9bbLQcU0p7hOZmCyc=; b=nnzTRw9Q6Uq7ED2oTJuXuHFeKO13f2Bjk1XWPKVcdjhFQIQrBFWRFKd+5zrLKQLECE Lh+aPDgsxx7jmds9GjpBWJrstHlqaCfz8Q5gIc4qP6PmzKHGvt+kuL1M2j/GRYehhGPO UiG2LQwzSVwAFjvIysRAJ6CmBfQsi9tBQjLhXIiF823jMncQl/d4DUpYdDHlqzqw9vTF lIBZCUYUn4B8Hylk0G9CnUqnDd41qRYk8GDgYlZKuZmkXcvihJB8eSYR7jhaqdbqkSWw opmoT+dDKr4M+Qtgr4Yblt4Fe7zL+z0SxC/Nk1Tqbq1hKi/XKe04VMNCJggIlizHjNsr KX7Q== X-Gm-Message-State: AGi0PuZcQj3ma14L+nWivn2AY2Z9kq5OGey/nIJOft4EDfLJiLqDMy9y 0/DekrDOeZyGakCAu7H6sjqC9Q== X-Google-Smtp-Source: APiQypJsAkimGuvIxqYs4ksJw8I2XT/AxqkEqRuDmBp0tzBzvnjcLkCi2t5U3jYlgAFUd5xK041frw== X-Received: by 2002:a17:90a:d711:: with SMTP id y17mr11350092pju.11.1589027956790; Sat, 09 May 2020 05:39:16 -0700 (PDT) Received: from localhost.localdomain ([80.251.214.228]) by smtp.gmail.com with ESMTPSA id o6sm4447828pfp.172.2020.05.09.05.39.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2020 05:39:16 -0700 (PDT) From: Shawn Guo To: Rob Clark , Sean Paul , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/2] drm/msm/a4xx: add a405_registers for a405 device Date: Sat, 9 May 2020 20:38:46 +0800 Message-Id: <20200509123846.27932-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200509123846.27932-1-shawn.guo@linaro.org> References: <20200509123846.27932-1-shawn.guo@linaro.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Konrad Dybcio , Brian Masney MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" A405 device has a different set of registers than a4xx_registers. It has no VMIDMT or XPU registers, and VBIF registers are different. Let's add a405_registers for a405 device. As adreno_is_a405() works only after adreno_gpu_init() gets called, the assignments get moved down after adreno_gpu_init(). Signed-off-by: Shawn Guo Reviewed-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 53 +++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 70de59751188..9e244982974e 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -445,6 +445,52 @@ static const unsigned int a4xx_registers[] = { ~0 /* sentinel */ }; +static const unsigned int a405_registers[] = { + /* RBBM */ + 0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026, + 0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066, + 0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF, + /* CP */ + 0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B, + 0x0578, 0x058F, + /* VSC */ + 0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51, + /* GRAS */ + 0x0C80, 0x0C81, 0x0C88, 0x0C8F, + /* RB */ + 0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2, + /* PC */ + 0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23, + /* VFD */ + 0x0E40, 0x0E4A, + /* VPC */ + 0x0E60, 0x0E61, 0x0E63, 0x0E68, + /* UCHE */ + 0x0E80, 0x0E84, 0x0E88, 0x0E95, + /* GRAS CTX 0 */ + 0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E, + /* PC CTX 0 */ + 0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7, + /* VFD CTX 0 */ + 0x2200, 0x2204, 0x2208, 0x22A9, + /* GRAS CTX 1 */ + 0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E, + /* PC CTX 1 */ + 0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7, + /* VFD CTX 1 */ + 0x2600, 0x2604, 0x2608, 0x26A9, + /* VBIF version 0x20050000*/ + 0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036, + 0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049, + 0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D, + 0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098, + 0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0, + 0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108, + 0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125, + 0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410, + ~0 /* sentinel */ +}; + static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu) { struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL); @@ -568,13 +614,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) gpu->perfcntrs = NULL; gpu->num_perfcntrs = 0; - adreno_gpu->registers = a4xx_registers; - adreno_gpu->reg_offsets = a4xx_register_offsets; - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); if (ret) goto fail; + adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers : + a4xx_registers; + adreno_gpu->reg_offsets = a4xx_register_offsets; + /* if needed, allocate gmem: */ if (adreno_is_a4xx(adreno_gpu)) { ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,