From patchwork Sun May 10 01:42:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 11538607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B839A139F for ; Sun, 10 May 2020 01:42:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67C4420A8B for ; Sun, 10 May 2020 01:42:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67C4420A8B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jXayw-0005rL-Kr for patchwork-qemu-devel@patchwork.kernel.org; Sat, 09 May 2020 21:42:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay8-0003nO-8g for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:28 -0400 Received: from mga09.intel.com ([134.134.136.24]:59850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay6-0006hs-Im for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:27 -0400 IronPort-SDR: Jxyti4Q41eN8YU1ZXNwb067kdL9dLHNaOzd72/a1G/w1keHRVVUVkMpVl5v5YJRjE5vfIBK2g9 VKSZNJSJfLMg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2020 18:41:18 -0700 IronPort-SDR: AJS9Qroqc1PVnpajeL7JYlnbSd/7zEEZRNhBS4l+345dhhPihUI3Su0cl/c/i4dAoNbuoF5XS9 C+JNTKKDrEBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,373,1583222400"; d="scan'208";a="264783113" Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 09 May 2020 18:41:17 -0700 From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com Subject: [Qemu-devel][PATCH v5 1/4] x86/cpu: Add CET CPUID/XSAVES flags and data structures Date: Sun, 10 May 2020 09:42:47 +0800 Message-Id: <20200510014250.28111-2-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200510014250.28111-1-weijiang.yang@intel.com> References: <20200510014250.28111-1-weijiang.yang@intel.com> Received-SPF: pass client-ip=134.134.136.24; envelope-from=weijiang.yang@intel.com; helo=mga09.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/09 21:41:17 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" CET feature SHSTK and IBT are enumerated via CPUID(EAX=0x7,0):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS to support XSAVES/XRSTORS. CPUID(EAX=0xd, 1):ECX[bit 11] and ECX[bit 12] correspond to CET states in user and supervisor mode respectively. Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e818fc712a..ed03cd1760 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -489,6 +489,9 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_RESERVED_BIT 10 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -499,6 +502,19 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_RESERVED_MASK (1ULL << XSTATE_RESERVED_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) + +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_USER_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ + XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \ + XSTATE_ZMM_Hi256_MASK | \ + XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_KERNEL_MASK (XSTATE_CET_U_MASK) /* CPUID feature words */ typedef enum FeatureWord { @@ -536,6 +552,8 @@ typedef enum FeatureWord { FEAT_VMX_EPT_VPID_CAPS, FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, + FEAT_XSAVES_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ + FEAT_XSAVES_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ FEATURE_WORDS, } FeatureWord; @@ -743,6 +761,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -770,6 +790,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1260,6 +1282,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; From patchwork Sun May 10 01:42:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 11538613 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A75E181 for ; Sun, 10 May 2020 01:43:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82E59205ED for ; Sun, 10 May 2020 01:43:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82E59205ED Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:33584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jXb0B-0007r8-PO for patchwork-qemu-devel@patchwork.kernel.org; Sat, 09 May 2020 21:43:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay8-0003oI-PN for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:28 -0400 Received: from mga09.intel.com ([134.134.136.24]:59851) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay6-0006mD-Bn for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:28 -0400 IronPort-SDR: u9WOWGHsHwdbxLpeX7128y6TTjkPiUPtUdz8NNKI8Z/qep67Xj298Xto1djMiHe9/Q/buK0r2y 1tGPk/Bw4tPw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2020 18:41:19 -0700 IronPort-SDR: Y439t2SCK7z5nVebFQI8wGC3Ouft8BZAxbZdlyt06B3mjoCeVKTJlH6EgJTOnUrTFpaLP4N161 HyCuVEpuZsag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,373,1583222400"; d="scan'208";a="264783129" Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 09 May 2020 18:41:18 -0700 From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com Subject: [Qemu-devel][PATCH v5 2/4] x86/cpuid: Add XSAVES feature words and CET related state bits Date: Sun, 10 May 2020 09:42:48 +0800 Message-Id: <20200510014250.28111-3-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200510014250.28111-1-weijiang.yang@intel.com> References: <20200510014250.28111-1-weijiang.yang@intel.com> Received-SPF: pass client-ip=134.134.136.24; envelope-from=weijiang.yang@intel.com; helo=mga09.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/09 21:41:17 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" CET SHSTK/IBT MSRs can be saved/restored with XSAVES/XRSTORS, but currently the related feature words are not supported, so add the new entries. XSAVES/RSTORS always use compacted storage format, which means the supervisor states' offsets are always 0, ignore them while calculating stardard format storage size. Signed-off-by: Zhang Yi Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 90ffc5f3b1..3174e05482 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -965,7 +965,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = CPUID_FEATURE_WORD, .feat_names = { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -988,7 +988,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, NULL, + "ibt", NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, @@ -1069,6 +1069,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_XSAVE_FEATURES, }, + /* Below are xsaves feature words */ + [FEAT_XSAVES_LO] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0xD, + .needs_ecx = true, + .ecx = 1, + .reg = R_ECX, + }, + .migratable_flags = XSTATE_CET_U_MASK, + }, + [FEAT_XSAVES_HI] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0xD, + .needs_ecx = true, + .ecx = 1, + .reg = R_EDX + }, + }, [FEAT_6_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { @@ -1455,6 +1475,14 @@ static const ExtSaveArea x86_ext_save_areas[] = { { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, .offset = offsetof(X86XSaveArea, pkru_state), .size = sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] = { + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, + .offset = 0 /*supervisor mode component, offset = 0 */, + .size = sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] = { + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, + .offset = 0 /*supervisor mode component, offset = 0 */, + .size = sizeof(XSavesCETS) }, }; static uint32_t xsave_area_size(uint64_t mask) @@ -1465,6 +1493,9 @@ static uint32_t xsave_area_size(uint64_t mask) for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; if ((mask >> i) & 1) { + if (i >= 2 && !esa->offset) { + continue; + } ret = MAX(ret, esa->offset + esa->size); } } @@ -6008,6 +6039,9 @@ static void x86_cpu_reset(DeviceState *dev) } for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; + if (!esa->offset) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |= 1ull << i; } From patchwork Sun May 10 01:42:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yang, Weijiang" X-Patchwork-Id: 11538615 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ACAAE81 for ; Sun, 10 May 2020 01:44:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8959320801 for ; Sun, 10 May 2020 01:44:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8959320801 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jXb0z-0000JS-QW for patchwork-qemu-devel@patchwork.kernel.org; Sat, 09 May 2020 21:44:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXayA-0003rN-LW for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:31 -0400 Received: from mga09.intel.com ([134.134.136.24]:59850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jXay8-0006hs-IC for qemu-devel@nongnu.org; Sat, 09 May 2020 21:41:30 -0400 IronPort-SDR: 9EHYVJ1jEEVoCadK9dN91NZLlORhO99c1zQenOikJn+bgq0nIgKU5s8hk6HlUrAnrZigg5qVAE TE+bSMP1xmUA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2020 18:41:22 -0700 IronPort-SDR: 4vKevsnqgDQPWk+jAmYKdwa6wRzyRFbSAKMv8VhSoIE2bUuo5I8hK+E2YAV6jVTKrArRaLcljM 8lwpN2lJgu8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,373,1583222400"; d="scan'208";a="264783141" Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by orsmga006.jf.intel.com with ESMTP; 09 May 2020 18:41:21 -0700 From: Yang Weijiang To: qemu-devel@nongnu.org, pbonzini@redhat.com Subject: [Qemu-devel][PATCH v5 4/4] x86/cpu: Add user space access interface for CET MSRs Date: Sun, 10 May 2020 09:42:50 +0800 Message-Id: <20200510014250.28111-5-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20200510014250.28111-1-weijiang.yang@intel.com> References: <20200510014250.28111-1-weijiang.yang@intel.com> Received-SPF: pass client-ip=134.134.136.24; envelope-from=weijiang.yang@intel.com; helo=mga09.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/09 21:41:17 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Added interface for CET MSR_IA32_{U,S}_CET, MSR_IA32_PL{0,1,2,3}_SSP, MSR_IA32_INTR_SSP_TBL and MSR_KVM_GUEST_SSP save/restore. Check if corresponding CET features are available before access the MSRs. Signed-off-by: Yang Weijiang --- target/i386/cpu.h | 18 +++++ target/i386/kvm.c | 73 +++++++++++++++++++ target/i386/machine.c | 161 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ed03cd1760..51577a04ca 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -480,6 +480,15 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_U_CET 0x6a0 +#define MSR_IA32_S_CET 0x6a2 +#define MSR_IA32_PL0_SSP 0x6a4 +#define MSR_IA32_PL1_SSP 0x6a5 +#define MSR_IA32_PL2_SSP 0x6a6 +#define MSR_IA32_PL3_SSP 0x6a7 +#define MSR_IA32_SSP_TBL 0x6a8 +#define MSR_KVM_GUEST_SSP 0x4b564d06 + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -1567,6 +1576,15 @@ typedef struct CPUX86State { uintptr_t retaddr; + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; + uint64_t ssp_tbl; + uint64_t guest_ssp; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 4901c6dd74..0735981558 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2979,6 +2979,31 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVES_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + } + + if (env->features[FEAT_XSAVES_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, env->ssp_tbl); + } + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + } + } + + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVES_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, env->guest_ssp); + return kvm_buf_set_msrs(cpu); } @@ -3295,6 +3320,30 @@ static int kvm_get_msrs(X86CPU *cpu) } } + if (((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) || + (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT)) && + (env->features[FEAT_XSAVES_LO] & XSTATE_CET_U_MASK)) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + } + + if (env->features[FEAT_XSAVES_LO] & XSTATE_CET_S_MASK) { + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_SSP_TBL, 0); + } + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + } + } + if ((env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) && + (env->features[FEAT_XSAVES_LO] & (XSTATE_CET_U_MASK | + XSTATE_CET_S_MASK))) + kvm_msr_entry_add(cpu, MSR_KVM_GUEST_SSP, 0); + ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3578,6 +3627,30 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; break; + case MSR_IA32_U_CET: + env->u_cet = msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet = msrs[i].data; + break; + case MSR_IA32_PL0_SSP: + env->pl0_ssp = msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp = msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp = msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp = msrs[i].data; + break; + case MSR_IA32_SSP_TBL: + env->ssp_tbl = msrs[i].data; + break; + case MSR_KVM_GUEST_SSP: + env->guest_ssp = msrs[i].data; + break; } } diff --git a/target/i386/machine.c b/target/i386/machine.c index 0c96531a56..3e1d8b6eb9 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -962,6 +962,159 @@ static const VMStateDescription vmstate_umwait = { } }; +static bool u_cet_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->u_cet != 0; +} + +static const VMStateDescription vmstate_u_cet = { + .name = "cpu/u_cet", + .version_id = 1, + .minimum_version_id = 1, + .needed = u_cet_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.u_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool s_cet_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->s_cet != 0; +} + +static const VMStateDescription vmstate_s_cet = { + .name = "cpu/s_cet", + .version_id = 1, + .minimum_version_id = 1, + .needed = s_cet_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.s_cet, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl0_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->pl0_ssp != 0; +} + +static const VMStateDescription vmstate_pl0_ssp = { + .name = "cpu/pl0_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pl0_ssp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.pl0_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl1_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->pl1_ssp != 0; +} + +static const VMStateDescription vmstate_pl1_ssp = { + .name = "cpu/pl1_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pl1_ssp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.pl1_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool pl2_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->pl2_ssp != 0; +} + +static const VMStateDescription vmstate_pl2_ssp = { + .name = "cpu/pl2_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pl2_ssp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.pl2_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + + +static bool pl3_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->pl3_ssp != 0; +} + +static const VMStateDescription vmstate_pl3_ssp = { + .name = "cpu/pl3_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pl3_ssp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.pl3_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool ssp_tbl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->ssp_tbl != 0; +} + +static const VMStateDescription vmstate_ssp_tbl = { + .name = "cpu/ssp_tbl", + .version_id = 1, + .minimum_version_id = 1, + .needed = ssp_tbl_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.ssp_tbl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool guest_ssp_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->guest_ssp != 0; +} + +static const VMStateDescription vmstate_guest_ssp = { + .name = "cpu/guest_ssp", + .version_id = 1, + .minimum_version_id = 1, + .needed = guest_ssp_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.guest_ssp, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifdef TARGET_X86_64 static bool pkru_needed(void *opaque) { @@ -1447,6 +1600,14 @@ VMStateDescription vmstate_x86_cpu = { &vmstate_nested_state, #endif &vmstate_msr_tsx_ctrl, + &vmstate_u_cet, + &vmstate_s_cet, + &vmstate_pl0_ssp, + &vmstate_pl1_ssp, + &vmstate_pl2_ssp, + &vmstate_pl3_ssp, + &vmstate_ssp_tbl, + &vmstate_guest_ssp, NULL } };