From patchwork Wed May 13 13:08:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546067 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F11F81 for ; Wed, 13 May 2020 13:09:02 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 58C72206B7; Wed, 13 May 2020 13:09:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A02F20673; Wed, 13 May 2020 13:09:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="KtfiAULL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1A02F20673 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589375342; x=1620911342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ykGNljrOL3uL7TOqwtHYrU0bzI70hpjkW9oijaZnkD4=; b=KtfiAULLQbcvn6U0FW/C4zLxARwV1dZMCeL1LfdIGXhXNiy5oI16I9BY pprB7kOOvAD6iQBudCa+/k7xaoXF8E1yf8/kQFjzzycvy8qlYjx2DuPFE mRoL3IMQU/vv4mQQhtOeDdZ2FVbQbmpk5DCofJwyQWJJhYwJqhJTlPMnj tPjdeFN16U452Qp0EpNUd/n8F3OMWNokvAYdvtO+zczCme5f0jzevZueb mlMDdn/4I9Ah4gVW6j0dMASG6kmaC3pETJDlk5qzLrnzwa7hOI+3OhbUE Opblci67Ei/Dm31olum1GkjQZq4r4I8kOJqdBM+/fimRaaSZqGY3J7NEe A==; IronPort-SDR: pp4CAtxiOJ18bIMjqxiPSRdDrgZcaeMpLz8CbXkSO+KTloXEVNF1IHYP6QlO1fwOxxW5mRXd1s HgqbGO1XEwzb3Wn4qNWElxT+rKYtCLtm9QW9bJkcSHdWJ28KMwovk+0Bn5UoEp4pMb+NLdkoeW /LPDUWLUlLoSnARibPtUAA9QsYq9iWa5rWzlVyWIt/u0UpGjIYEaJcEVZj7mqz2cY0D0emTBQ5 JhBdFIkuo3ZrA0v7ONMMUJa1UpHO6N0OPGIBs3hCx7E1YqaLjsY85HTxEl6gcIbXEemXJk7Rgk CX0= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76497693" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:08:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:08:59 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:08:54 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team , Rob Herring CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 1/5] dt-bindings: reset: ocelot: Add Sparx5 support Date: Wed, 13 May 2020 15:08:38 +0200 Message-ID: <20200513130842.24847-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds the support for the Sparx5 SoC. Signed-off-by: Lars Povlsen --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++-- MAINTAINERS | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 1b4213eb34731..4d530d8154848 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -1,10 +1,13 @@ Microsemi Ocelot reset controller The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the -SoC MIPS core. +SoC core. + +The reset registers are both present in the MSCC vcoreiii MIPS and +microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" + - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { diff --git a/MAINTAINERS b/MAINTAINERS index 5aa28d6e39d4f..1db598723a1d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11230,6 +11230,7 @@ M: Microchip Linux Driver Support L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt +F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c From patchwork Wed May 13 13:08:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546071 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D66E5186E for ; Wed, 13 May 2020 13:09:02 +0000 (UTC) Received: by mail.kernel.org (Postfix) id CC6DD206D6; Wed, 13 May 2020 13:09:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6658D20673; Wed, 13 May 2020 13:09:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="QW/yR+a5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6658D20673 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589375342; x=1620911342; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EVZAXO1o0L53j6vhD0cm7z0bP8p6Ac07Mbyf5NtalMA=; b=QW/yR+a5iuXx4irYnN5PszvtcZQCLeIYyVSABjDOdYVPVvksdYcl/nzz BAsi1W0Yx+aE7hdtzu52mKEj7ZIWY5eDTPwwkly/quWPoDYLFKxU5faby l5kEcXY28ZahdQDfLcninNTiCI7LuNI2tyw22PcnYZedKENHZoDC8vwHv F+ZFY8naT97lLbGNogLyiAwhVna6VPPtdY9rUVpU6G8kekc9rf/4jF4Sd TfO/P6Wwm3RD1Fyr8lpeMSm4l8P/5CoKmeb6EvC3q+tt9pDk6k1SfAsYC Eq1feHM7qiYRHRpSrmRWwYXy03IWL/iKn3wrCRzi/YtNhylE+RO0h2YGy Q==; IronPort-SDR: Iaa2ZR9ylS9Tayj7EHHnyzAzRlCNlrf3R0bjVebGT6XxXfVlplPSISWXgmaRT4sdb0M2TJ7vUv ID/3pk3BOERFDrvkoykbBd092szXPaqF5KFfTewm2dNz/XQsUB/nw2Y2vuAwdTG7X/49K5ccg7 xfcsJeFp0/7BOglHqe+jJ1d+3AGSjeWxTz9h4tlANigLLFQafCknXMz6VK1qT7aYPCLLWwsaqc UYWfU5kine1EOq5MJpj83RDpP8ttjyIpRBK2D5zIqXSO4hHw1riKiRra9jbDw9qINq4LYBHPUg Qc4= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76497710" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:08:59 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:09:02 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:08:57 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 2/5] power: reset: ocelot: Add support for Sparx5 Date: Wed, 13 May 2020 15:08:39 +0200 Message-ID: <20200513130842.24847-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds reset support for Sparx5 in the ocelot-reset driver. Signed-off-by: Lars Povlsen --- drivers/power/reset/Kconfig | 3 +- drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++++++++++------- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 8903803020805..9ecafbf9e64a6 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -118,10 +118,9 @@ config POWER_RESET_QCOM_PON config POWER_RESET_OCELOT_RESET bool "Microsemi Ocelot reset driver" - depends on MSCC_OCELOT || COMPILE_TEST select MFD_SYSCON help - This driver supports restart for Microsemi Ocelot SoC. + This driver supports restart for Microsemi Ocelot SoC and similar. config POWER_RESET_PIIX4_POWEROFF tristate "Intel PIIX4 power-off driver" diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c index 419952c61fd01..f74e1dbb4ba36 100644 --- a/drivers/power/reset/ocelot-reset.c +++ b/drivers/power/reset/ocelot-reset.c @@ -15,15 +15,20 @@ #include #include +struct reset_props { + const char *syscon; + u32 protect_reg; + u32 vcore_protect; + u32 if_si_owner_bit; +}; + struct ocelot_reset_context { void __iomem *base; struct regmap *cpu_ctrl; + const struct reset_props *props; struct notifier_block restart_handler; }; -#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20 -#define CORE_RST_PROTECT BIT(2) - #define SOFT_CHIP_RST BIT(0) #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 @@ -31,7 +36,6 @@ struct ocelot_reset_context { #define IF_SI_OWNER_SISL 0 #define IF_SI_OWNER_SIBM 1 #define IF_SI_OWNER_SIMC 2 -#define IF_SI_OWNER_OFFSET 4 static int ocelot_restart_handle(struct notifier_block *this, unsigned long mode, void *cmd) @@ -39,15 +43,18 @@ static int ocelot_restart_handle(struct notifier_block *this, struct ocelot_reset_context *ctx = container_of(this, struct ocelot_reset_context, restart_handler); + u32 if_si_owner_bit = ctx->props->if_si_owner_bit; /* Make sure the core is not protected from reset */ - regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET, - CORE_RST_PROTECT, 0); + regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, + ctx->props->vcore_protect, 0); /* Make the SI back to boot mode */ regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, - IF_SI_OWNER_MASK << IF_SI_OWNER_OFFSET, - IF_SI_OWNER_SIBM << IF_SI_OWNER_OFFSET); + IF_SI_OWNER_MASK << if_si_owner_bit, + IF_SI_OWNER_SIBM << if_si_owner_bit); + + pr_emerg("Resetting SoC\n"); writel(SOFT_CHIP_RST, ctx->base); @@ -72,9 +79,13 @@ static int ocelot_reset_probe(struct platform_device *pdev) if (IS_ERR(ctx->base)) return PTR_ERR(ctx->base); - ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon"); - if (IS_ERR(ctx->cpu_ctrl)) + ctx->props = device_get_match_data(dev); + + ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon); + if (IS_ERR(ctx->cpu_ctrl)) { + dev_err(dev, "No syscon map: %s\n", ctx->props->syscon); return PTR_ERR(ctx->cpu_ctrl); + } ctx->restart_handler.notifier_call = ocelot_restart_handle; ctx->restart_handler.priority = 192; @@ -85,9 +96,29 @@ static int ocelot_reset_probe(struct platform_device *pdev) return err; } +static const struct reset_props reset_props_ocelot = { + .syscon = "mscc,ocelot-cpu-syscon", + .protect_reg = 0x20, + .vcore_protect = BIT(2), + .if_si_owner_bit = 4, +}; + +static const struct reset_props reset_props_sparx5 = { + .syscon = "microchip,sparx5-cpu-syscon", + .protect_reg = 0x84, + .vcore_protect = BIT(10), + .if_si_owner_bit = 6, +}; + static const struct of_device_id ocelot_reset_of_match[] = { - { .compatible = "mscc,ocelot-chip-reset" }, - {} + { + .compatible = "mscc,ocelot-chip-reset", + .data = &reset_props_ocelot + }, { + .compatible = "microchip,sparx5-chip-reset", + .data = &reset_props_sparx5 + }, + { /*sentinel*/ } }; static struct platform_driver ocelot_reset_driver = { From patchwork Wed May 13 13:08:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546069 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD4CC1668 for ; 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Wed, 13 May 2020 06:09:01 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:08:59 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team , Rob Herring CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 3/5] dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property Date: Wed, 13 May 2020 15:08:40 +0200 Message-ID: <20200513130842.24847-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This documents the 'microchip,reset-switch-core' property in the ocelot-reset driver. Signed-off-by: Lars Povlsen --- .../devicetree/bindings/power/reset/ocelot-reset.txt | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 4d530d8154848..20fff03753ad2 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -9,9 +9,15 @@ microchip Sparx5 armv8 SoC's. Required Properties: - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" +Optional properties: +- microchip,reset-switch-core : Perform a switch core reset at the + time of driver load. This is may be used to initialize the switch + core to a known state (before other drivers are loaded). + Example: reset@1070008 { compatible = "mscc,ocelot-chip-reset"; reg = <0x1070008 0x4>; + microchip,reset-switch-core; }; From patchwork Wed May 13 13:08:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546077 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 76FC090 for ; Wed, 13 May 2020 13:09:07 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 71069206E5; Wed, 13 May 2020 13:09:07 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 026C720673; Wed, 13 May 2020 13:09:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="D/1ildm5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 026C720673 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589375347; x=1620911347; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V1OANcDGi3Zb91vsck9iJpexMcTamnhCI2LiIcyTydQ=; b=D/1ildm50PF/rPVvySWQMOjkLsGTd+NKJ+yKdS4RzULRxaZz6eNooIV7 PElwPyWb7e9t/X5KAiJjfJjcBg3OK+u/DogrtlY2z2NVqSsncF7ER95fF oFHgItZw/LB9uKqyi4ydpCHUTqnxiuQT6BsCcfzcl5qJR8eHa6xRq2Pl5 ZtNF32JQJE0DOwPqJnakdEbZL84X0VY74XB25bog0D9vTwcgDAqx7dOuE Z8xXQWLlQcn/sfnrVm2QQCuu79SQLEe/tq412WtxEtIspWvEd3IhfxPsn s+9pZGLmyu/ZngcD5vg6O5nf73VnHMgNRtxWfWdMLOMjyl4GKahtOMo37 A==; IronPort-SDR: +6yZhiMfqJQ38vJrskCsDMyrAr18DNmhZ3317VdPR7QUzEaMe4qimJp20CkWP8Bj9mzJCC42Q3 CVr3uFHSqn/rfsSuhh/f7GADhQ7TNdN64qyaGiUp5diAs3V6ZmkLA3VGgxPMNRL57HPCxcPgHy AGXKL6ZD33hHcCI0zLk9MgkT9sM/sD7LJMTTa3sUNxa3PmGyn1X712gZao6FOAbRIwLTJhacxO d1fS7k0335S56Tan42EQEHuwZViwJJET6rY7jMwwSYWh/cMfPj1mLNUqIrmWPE9Xcktq/MWl9V jvs= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76497730" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:09:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:09:06 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:09:01 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 4/5] power: reset: ocelot: Add support for reset switch on load time Date: Wed, 13 May 2020 15:08:41 +0200 Message-ID: <20200513130842.24847-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This patch add support for resetting the networking switch core at reset driver load time. It is useful in order to bring the switch core in a known state after a reboot or after a bootloader may have been using the switch for network access. Signed-off-by: Lars Povlsen --- drivers/power/reset/ocelot-reset.c | 40 ++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c index f74e1dbb4ba36..a203c42e99d42 100644 --- a/drivers/power/reset/ocelot-reset.c +++ b/drivers/power/reset/ocelot-reset.c @@ -29,6 +29,7 @@ struct ocelot_reset_context { struct notifier_block restart_handler; }; +#define SOFT_SWC_RST BIT(1) #define SOFT_CHIP_RST BIT(0) #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 @@ -37,6 +38,32 @@ struct ocelot_reset_context { #define IF_SI_OWNER_SIBM 1 #define IF_SI_OWNER_SIMC 2 +static int ocelot_switch_core_reset(const struct ocelot_reset_context *ctx) +{ + + const char *driver = "ocelot-reset"; + int timeout; + + pr_notice("%s: Resetting Switch Core\n", driver); + + /* Make sure the core is PROTECTED from reset */ + regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, + ctx->props->vcore_protect, + ctx->props->vcore_protect); + + writel(SOFT_SWC_RST, ctx->base); + for (timeout = 0; timeout < 100; timeout++) { + if ((readl(ctx->base) & SOFT_SWC_RST) == 0) { + pr_debug("%s: Switch Core Reset complete.\n", driver); + return 0; + } + udelay(1); + } + + pr_warn("%s: Switch Core Reset timeout!\n", driver); + return -ENXIO; +} + static int ocelot_restart_handle(struct notifier_block *this, unsigned long mode, void *cmd) { @@ -66,7 +93,6 @@ static int ocelot_reset_probe(struct platform_device *pdev) { struct ocelot_reset_context *ctx; struct resource *res; - struct device *dev = &pdev->dev; int err; @@ -87,6 +113,11 @@ static int ocelot_reset_probe(struct platform_device *pdev) return PTR_ERR(ctx->cpu_ctrl); } + /* Optionally, call switch reset function */ + if (of_property_read_bool(pdev->dev.of_node, + "microchip,reset-switch-core")) + ocelot_switch_core_reset(ctx); + ctx->restart_handler.notifier_call = ocelot_restart_handle; ctx->restart_handler.priority = 192; err = register_restart_handler(&ctx->restart_handler); @@ -128,4 +159,9 @@ static struct platform_driver ocelot_reset_driver = { .of_match_table = ocelot_reset_of_match, }, }; -builtin_platform_driver(ocelot_reset_driver); + +static int __init reset_init(void) +{ + return platform_driver_register(&ocelot_reset_driver); +} +postcore_initcall(reset_init); From patchwork Wed May 13 13:08:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546075 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72DCE81 for ; Wed, 13 May 2020 13:09:07 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6CEBC206CC; Wed, 13 May 2020 13:09:07 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa2.microchip.iphmx.com (esa2.microchip.iphmx.com [68.232.149.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 114C3206B7; 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IronPort-SDR: ImLEDdl7AMnyivYjeyLG78XOm3QyPYMEALDQBIoV+dGm4URpVcSdVUf1Di9smzsXclhJWybcZt hyHSlC0YFvP7ByXUfKY3xCO49Kqm4ofDJtsn5FeIE5mgVz4zEiZxHL6GhtE6A2rnI9eT2L+g+F A2A9TEE60W4trAvOZYGBRV0hoCzrAcRsY4rnuN9mZMgRsSdM6/8fzl4J7aarXou6YVWs5jNzLS wNa027v3HdODTTeZMgL/4aE1iA4fm+RoxOjiHQlLmL7j5SZ8xJzJUDsvZH2HRTNaexnh5cFqVs MYs= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75134448" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:09:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:09:06 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:09:04 -0700 From: Lars Povlsen List-Id: To: Sebastian Reichel , SoC Team CC: Lars Povlsen , Alexandre Belloni , Microchip Linux Driver Support , , , , Subject: [PATCH 5/5] arm64: dts: sparx5: Add reset support Date: Wed, 13 May 2020 15:08:42 +0200 Message-ID: <20200513130842.24847-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com> References: <20200513130842.24847-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds reset support to the Sparx5 SoC Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index b5cb3d8dc876b..3e94ac9e7dd51 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -106,6 +106,17 @@ gic: interrupt-controller@600300000 { interrupts = ; }; + cpu_ctrl: syscon@600000000 { + compatible = "microchip,sparx5-cpu-syscon", "syscon"; + reg = <0x6 0x00000000 0xd0>; + }; + + reset@611010008 { + compatible = "microchip,sparx5-chip-reset"; + reg = <0x6 0x11010008 0x4>; + microchip,reset-switch-core; + }; + uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default";