From patchwork Wed May 13 13:41:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546299 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BCC6459D for ; Wed, 13 May 2020 13:41:48 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 00DCC2065D; Wed, 13 May 2020 13:41:50 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C147B204EF; Wed, 13 May 2020 13:41:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="K13d63Um" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C147B204EF Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589377310; x=1620913310; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qlFyZReVo2pHOVk2iDuspF2CVGNtSezC+5qbLU9vpWA=; b=K13d63UmH//ZG/kFwYbMKQ80Y0GuFIXdquLFowkJNAUO2DRIfu6FoNDn 2BM0bYZDnq3CstM0LwTon3mu788KRSpUKiNvEwK373+Bjo3r2OckQmTsk iRYtpPVxHGyh3bf/ck3OF73OOEjhZq1QwKyWWLnh9Vy8n15XIKmG52Dyd z1XhFnXEpUsiWLqkvE3o+3ipEfszUhpc+Upet1+0ggEVN7cEqwIHvlD0v xbTn3zneC8jJfLbTIVlCElX0Zdud8vXytSOULUK+N0bR7PiSqMIZ4LqVN /5d5fP/6QaV3l9bD5EHyV+k9QQqboiCEZ2zOPZVKKlEHV4tKhJg2EwNMG Q==; IronPort-SDR: 3n7GItFr3OrwIchwpxNLWuuQkrXHfun+GhFttMmeaLVJMnOp9ZBHwobBZCyag9KxKTqnTiaiFS M0gd+bu2OZ5ln49vNO8xvQqP3xKN2++LVxFjwqq1JkiRPZOSL2gHjhU5+vlQbWT1XRy+Vz5nF4 9N8LfTNwynF3unssGanacMGljwKV+F6t6eM045FIaFselBxXGR+VdUDuF88JBFiXSO2U9w3mw8 4YT0Vqy+GGcknlv8ZIHBXeZXAsfWYrMUGJkJHipIU1/ya8X4I9JUrjBhEPJzAveapCDwfdSNjt Tro= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="79444211" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:41:50 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:41:52 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:41:50 -0700 From: Lars Povlsen List-Id: To: Guenter Roeck , SoC Team , Rob Herring CC: Lars Povlsen , Jean Delvare , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 1/3] dt-bindings: hwmon: Add Sparx5 temperature sensor Date: Wed, 13 May 2020 15:41:38 +0200 Message-ID: <20200513134140.25357-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513134140.25357-1-lars.povlsen@microchip.com> References: <20200513134140.25357-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add the DT binding specification for the Sparx5 temperature sensor. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/hwmon/microchip,sparx5-temp.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/microchip,sparx5-temp.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/hwmon/microchip,sparx5-temp.yaml b/Documentation/devicetree/bindings/hwmon/microchip,sparx5-temp.yaml new file mode 100644 index 0000000000000..0df4813fd7b24 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,sparx5-temp.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,sparx5-temp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 Temperature Monitor + +maintainers: + - Lars Povlsen + +description: | + Microchip Sparx5 embedded temperature monitor + +properties: + compatible: + enum: + - microchip,sparx5-temp + + reg: + maxItems: 1 + + '#thermal-sensor-cells': + const: 0 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + tmon0: tmon@610508110 { + compatible = "microchip,sparx5-temp"; + reg = <0x10508110 0xc>; + #thermal-sensor-cells = <0>; + }; + From patchwork Wed May 13 13:41:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2BAE90 for ; Wed, 13 May 2020 13:42:28 +0000 (UTC) Received: by mail.kernel.org (Postfix) id DA55820657; Wed, 13 May 2020 13:42:29 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 98342204EF for ; Wed, 13 May 2020 13:42:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="xsUR00wg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 98342204EF Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589377351; x=1620913351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PV07J/wAT10xDYr9kx06zNqja/xgCGRaYSoB57UP5EA=; b=xsUR00wgiYPKZwHX8VDkx4Lsd2Khp2/qLniLVmrSvoejRO7iP7xXqak/ UE7Ib/MfA7jM5AKv+EE0SHWnOr3Ka9E/frBGZXcgKG3VQxRefk+JchcZo S/3hbNAj2b9C5q4TXglbWzxT1cCqr/qYVsW1Zz48wQq5WHIbbp7QCiQsL zgS1Jir82++Gvc2yb/9a6bRZr0GPHrvCh05nl7HJWA5ixfENHD+2awTun AsB0xiv+3IdVegPZhvO/+99pVCdCcJ7ymHHHaZw/N0H6bI2QlEHEU/Uz+ wiTx8hudb9YggQTeosecKLMv55Ha6gqWr1xj0eOeiMnxB2s2Y+p5o6hYL Q==; IronPort-SDR: G9KdmkzZxo6j5xx25DGIDDmDefKyX/w0bsG8CdPIn9a7RBFlaLp2vc0dkyZa4XLPoBOrBXuZGg CY87CN9ml9fv7a9axPhgMkERYAcnXBh2MAKZlDARR7BdY7lcK3qBYJvsYXyhUybUomFPjFzLBe Tw1O5C+jE5+AO4u5VEYTBhKteWPbnnr91XKTO91NfAHrwxMbTxtOs8IPJ887vLcal9YVO13RZ/ fqZvORksXotyjqiGYNIzioj1uG4UvI0XXMJpqnIhcnJy2G8msgEoU+gEysh2QMhaovgs5A7rRs GL0= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="75771963" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:41:54 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:41:55 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:41:53 -0700 From: Lars Povlsen List-Id: To: Guenter Roeck , SoC Team CC: Lars Povlsen , Jean Delvare , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 2/3] arm64: dts: sparx5: Add hwmon temperature sensor Date: Wed, 13 May 2020 15:41:39 +0200 Message-ID: <20200513134140.25357-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513134140.25357-1-lars.povlsen@microchip.com> References: <20200513134140.25357-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds a hwmon temperature node sensor to the Sparx5 SoC. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index f09a49c41ce19..b5f2d088af30e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -233,5 +233,11 @@ i2c1: i2c@600103000 { clock-frequency = <100000>; clocks = <&ahb_clk>; }; + + tmon0: tmon@610508110 { + compatible = "microchip,sparx5-temp"; + reg = <0x6 0x10508110 0xc>; + #thermal-sensor-cells = <0>; + }; }; }; From patchwork Wed May 13 13:41:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546305 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03B2090 for ; Wed, 13 May 2020 13:41:54 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 3B9B320657; Wed, 13 May 2020 13:41:55 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D55F2065D for ; Wed, 13 May 2020 13:41:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="jXs7M1Rg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D55F2065D Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589377315; x=1620913315; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lw1dDpuogFHf2FXc0xqaRt0YHXMCAsmOeJxn562Quvk=; b=jXs7M1Rgn2fmcuNFTr4KSh5Yu1EFdexNS16vELgi/+8WXHNZTl6d6DvP 8LCfB61PwBZvwv1VJMes5VGD1o6HcKSHbrPQnI16ktPPVhidyDvyrELkT ERBHpu7g+HCAaPTZweh9TlS+EdKcs9ZO7IgZJwdIllvQZiM6jf4kH37K/ OqNCSe4voGqJSaCVjfDvlAyWG0nAU95UZm3zHgnblk2nrHnsHg4MRvSD7 zqrhByEs5OWAbdPo3THB7s5WV7c5M9Wtwcq6UOF6CJ9sBG4Db53ZAyb4h hg9CKfp93TCviSei55eI5HYnQXA+DD4MyvI1Ru2jVFNDbGpjy+gmdYTPJ w==; IronPort-SDR: yV4k+9QFy+k3Ts5oaxqE0ZeJXVWPqYeCqITv4qiO/sKLQjDV8C8FekeimAIb7pq/UgsNARE/+w jAj/8HpzRQeQgEfCD4QPCzOu7xodxTNBWCIfvahTdonlIEUqlLVpE+diJcTwsWVLqrmEMnREWi 0yxD4+DXHLSeN7elWznfDOYzmv8arizYyTYgOcTd2fo7NDebHYoFO6WAB/LFD6kKaYfFSM4siS iECgI32e8fN7RoDQ1dnfW3ZZajEEZ96J1bpvRmt/qTraaumP41LpgLST9ci9zPJUYB8ufOCAvi oFo= X-IronPort-AV: E=Sophos;i="5.73,387,1583218800"; d="scan'208";a="76504510" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 06:41:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 06:41:55 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 06:41:55 -0700 From: Lars Povlsen List-Id: To: Guenter Roeck , SoC Team CC: Lars Povlsen , Jean Delvare , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 3/3] hwmon: sparx5: Add Sparx5 SoC temperature driver Date: Wed, 13 May 2020 15:41:40 +0200 Message-ID: <20200513134140.25357-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513134140.25357-1-lars.povlsen@microchip.com> References: <20200513134140.25357-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This patch adds a temperature sensor driver to the Sparx5 SoC. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/hwmon/Kconfig | 10 +++ drivers/hwmon/Makefile | 2 +- drivers/hwmon/sparx5-temp.c | 154 ++++++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 1 deletion(-) create mode 100644 drivers/hwmon/sparx5-temp.c -- 2.26.2 diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 4c62f900bf7e8..130cb1f1748ff 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -480,6 +480,16 @@ config SENSORS_I5K_AMB This driver can also be built as a module. If so, the module will be called i5k_amb. +config SENSORS_SPARX5 + tristate "Sparx5 SoC temperature sensor" + depends on ARCH_SPARX5 + help + If you say yes here you get support for temperature monitoring + with the Microchip Sparx5 SoC. + + This driver can also be built as a module. If so, the module + will be called sparx5-temp. + config SENSORS_F71805F tristate "Fintek F71805F/FG, F71806F/FG and F71872F/FG" depends on !PPC diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index b0b9c8e571762..28a09986b7a62 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SENSORS_DS1621) += ds1621.o obj-$(CONFIG_SENSORS_EMC1403) += emc1403.o obj-$(CONFIG_SENSORS_EMC2103) += emc2103.o obj-$(CONFIG_SENSORS_EMC6W201) += emc6w201.o +obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o obj-$(CONFIG_SENSORS_F71805F) += f71805f.o obj-$(CONFIG_SENSORS_F71882FG) += f71882fg.o obj-$(CONFIG_SENSORS_F75375S) += f75375s.o @@ -190,4 +191,3 @@ obj-$(CONFIG_SENSORS_OCC) += occ/ obj-$(CONFIG_PMBUS) += pmbus/ ccflags-$(CONFIG_HWMON_DEBUG_CHIP) := -DDEBUG - diff --git a/drivers/hwmon/sparx5-temp.c b/drivers/hwmon/sparx5-temp.c new file mode 100644 index 0000000000000..bf9dd102a9825 --- /dev/null +++ b/drivers/hwmon/sparx5-temp.c @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Sparx5 SoC temperature sensor driver + * + * Copyright (C) 2020 Lars Povlsen + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TEMP_CTRL 0 +#define TEMP_CFG 4 +#define TEMP_CFG_CYCLES GENMASK(24, 15) +#define TEMP_CFG_CYCLES_OFF 15 +#define TEMP_CFG_ENA BIT(0) +#define TEMP_STAT 8 +#define TEMP_STAT_VALID BIT(12) +#define TEMP_STAT_TEMP GENMASK(11, 0) + +struct s5_hwmon { + void __iomem *base; +}; + +static void s5_temp_enable(struct s5_hwmon *hwmon) +{ + u32 val = readl(hwmon->base + TEMP_CFG); + u32 clk = 250; + + val &= ~TEMP_CFG_CYCLES; + val |= (clk << TEMP_CFG_CYCLES_OFF); + val |= TEMP_CFG_ENA; + + writel(val, hwmon->base + TEMP_CFG); +} + +static void s5_temp_disable(void *data) +{ + struct s5_hwmon *hwmon = data; + u32 val = readl(hwmon->base + TEMP_CFG); + + val &= ~TEMP_CFG_ENA; + + writel(val, hwmon->base + TEMP_CFG); +} + +static int s5_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *temp) +{ + struct s5_hwmon *hwmon = dev_get_drvdata(dev); + int rc = 0, value; + u32 stat; + + switch (attr) { + case hwmon_temp_input: + stat = readl_relaxed(hwmon->base + TEMP_STAT); + if (stat & TEMP_STAT_VALID) { + value = (stat & TEMP_STAT_TEMP); + value = DIV_ROUND_CLOSEST(value * 3522, 4096) - 1094; + value *= 100; + *temp = value; + } else + rc = -EINVAL; + break; + default: + rc = -EOPNOTSUPP; + } + + return rc; +} + +static umode_t s5_is_visible(const void *_data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + if (type != hwmon_temp) + return 0; + + switch (attr) { + case hwmon_temp_input: + return 0444; + default: + return 0; + } +} + +static const struct hwmon_channel_info *s5_info[] = { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT), + NULL +}; + +static const struct hwmon_ops s5_hwmon_ops = { + .is_visible = s5_is_visible, + .read = s5_read, +}; + +static const struct hwmon_chip_info s5_chip_info = { + .ops = &s5_hwmon_ops, + .info = s5_info, +}; + +static int s5_temp_probe(struct platform_device *pdev) +{ + struct device *hwmon_dev; + struct s5_hwmon *hwmon; + int err = 0; + + hwmon = devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL); + if (!hwmon) + return -ENOMEM; + + hwmon->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(hwmon->base)) + return PTR_ERR(hwmon->base); + + err = devm_add_action(&pdev->dev, s5_temp_disable, hwmon); + if (err) + return err; + + s5_temp_enable(hwmon); + + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + "s5_temp", + hwmon, + &s5_chip_info, + NULL); + + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +const struct of_device_id s5_temp_match[] = { + { .compatible = "microchip,sparx5-temp" }, + {}, +}; +MODULE_DEVICE_TABLE(of, s5_temp_match); + +static struct platform_driver s5_temp_driver = { + .probe = s5_temp_probe, + .driver = { + .name = "sparx5-temp", + .of_match_table = s5_temp_match, + }, +}; + +module_platform_driver(s5_temp_driver); + +MODULE_AUTHOR("Lars Povlsen "); +MODULE_DESCRIPTION("Sparx5 SoC temperature sensor driver"); +MODULE_LICENSE("GPL");