From patchwork Wed May 13 14:00:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4B22E90 for ; Wed, 13 May 2020 14:00:44 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 65D6720693; Wed, 13 May 2020 14:00:45 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BBB920690; Wed, 13 May 2020 14:00:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="B83NU+8L" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3BBB920690 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378445; x=1620914445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E2LeTrXG5USlLqv6CmJsbBQmCdfRXDqsQ0KDLdpn/wA=; b=B83NU+8L4KbKDvFaQGXqcpKSEda4db5ppRK0bKpxPvsx4RQrgrGPN5xw /epOB2i+E4Roey71huKDOb8+6U9a/16yqNPo5bUAFeR0wjS4d0p+qkzR+ f8oqJDcCLGNzqsj/0f//71Bjl84Zm4Ed4hb2TWVYSEmMn8h6/TLh5c5w3 cn5+w40AzYUxAWVKwhYAI6TSi+gF4EfVkX84nA3ZnCSAz/aPFtAT+khnU 8l8taRxWVMi2gwFZojqUNVCs7jZeEksMIpI6HI0k9KwoJ8OMYx/zQKp0g jAyHeQQgwqEgF9S/92xBk1Ly4RIwyzT/oKkv63zwmysYnWIwOaBrLG7xW Q==; IronPort-SDR: fnwxvPcGQmcXFxqzx53KJMTcVAUAw6CucJ/tFsnpig2jxsTO5+7WvUQWlnhFHUS/c2LTWCinxk Ccy0u6/nP64oHUmfXqSWqSqMeCVJGnUEo1dEh0BbjPWAtZeAXcEivImlBrGMGRS/HnEqtji1Jp yPRZuRc3ai+OFB6qQ7jEW7rwfSKDZpSS2eP7pbq72WEPmGcU4YTAc/cfO3pRaYbNvpzVW5uX9N /zCcOHOQr0mcR2Y26nPKaysX8AVwbrTX04V0gKn4mWzdreHR4Qs9EI9W+0R7kOtzeOo4Bo2Zzd PXg= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="79447442" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:46 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:41 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 01/10] spi: dw: Add support for polled operation via no IRQ specified in DT Date: Wed, 13 May 2020 16:00:22 +0200 Message-ID: <20200513140031.25633-2-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 With this change a SPI controller can be added without having a IRQ associated, and causing all transfers to be polled. For SPI controllers without DMA, this can significantly improve performance by less interrupt handling overhead. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/spi/spi-dw.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) -- 2.26.2 diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 31e3f866d11a7..e572eb34a3c1a 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -19,6 +19,8 @@ #include #endif +#define VALID_IRQ(i) (i >= 0) + /* Slave spi_dev related */ struct chip_data { u8 tmode; /* TR/TO/RO/EEPROM */ @@ -359,7 +361,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_enable_chip(dws, 1); return ret; } - } else if (!chip->poll_mode) { + } else if (!chip->poll_mode && VALID_IRQ(dws->irq)) { txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); dw_writel(dws, DW_SPI_TXFLTR, txlevel); @@ -379,7 +381,7 @@ static int dw_spi_transfer_one(struct spi_controller *master, return ret; } - if (chip->poll_mode) + if (chip->poll_mode || !VALID_IRQ(dws->irq)) return poll_transfer(dws); return 1; @@ -487,11 +489,13 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) spi_controller_set_devdata(master, dws); - ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev), - master); - if (ret < 0) { - dev_err(dev, "can not get IRQ\n"); - goto err_free_master; + if (VALID_IRQ(dws->irq)) { + ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, + dev_name(dev), master); + if (ret < 0) { + dev_err(dev, "can not get IRQ\n"); + goto err_free_master; + } } master->use_gpio_descriptors = true; @@ -539,7 +543,8 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) if (dws->dma_ops && dws->dma_ops->dma_exit) dws->dma_ops->dma_exit(dws); spi_enable_chip(dws, 0); - free_irq(dws->irq, master); + if (VALID_IRQ(dws->irq)) + free_irq(dws->irq, master); err_free_master: spi_controller_put(master); return ret; From patchwork Wed May 13 14:00:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546423 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1451890 for ; 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Wed, 13 May 2020 07:00:48 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:43 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 02/10] spi: dw: Add support for RX sample delay register Date: Wed, 13 May 2020 16:00:23 +0200 Message-ID: <20200513140031.25633-3-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add support for the RX_SAMPLE_DLY register. If enabled in the Designware IP, it allows tuning of the rx data signal by means of an internal rx sample fifo. The register is located at offset 0xf0, and if the option is not enabled in the IP, changing the register will have no effect. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/spi/spi-dw.c | 7 +++++++ drivers/spi/spi-dw.h | 2 ++ 2 files changed, 9 insertions(+) -- 2.26.2 diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index e572eb34a3c1a..32997f28fa5bb 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -81,6 +81,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf, "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR)); + len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, + "RX_SAMPLE_DLY: \t0x%08x\n", + dw_readl(dws, DW_SPI_RX_SAMPLE_DLY)); len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len, "=================================\n"); @@ -315,6 +318,10 @@ static int dw_spi_transfer_one(struct spi_controller *master, spi_set_clk(dws, chip->clk_div); } + /* Apply RX sample delay, iff requested (nonzero) */ + if (dws->rx_sample_dly) + dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, dws->rx_sample_dly); + dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE); diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 1bf5713e047d3..ed6e47b3f50da 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -31,6 +31,7 @@ #define DW_SPI_IDR 0x58 #define DW_SPI_VERSION 0x5c #define DW_SPI_DR 0x60 +#define DW_SPI_RX_SAMPLE_DLY 0xf0 #define DW_SPI_CS_OVERRIDE 0xf4 /* Bit fields in CTRLR0 */ @@ -111,6 +112,7 @@ struct dw_spi { int cs_override; u32 reg_io_width; /* DR I/O width in bytes */ + u8 rx_sample_dly; /* RX fifo tuning (option) */ u16 bus_num; u16 num_cs; /* supported slave numbers */ void (*set_cs)(struct spi_device *spi, bool enable); From patchwork Wed May 13 14:00:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546427 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6AB560D for ; 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Wed, 13 May 2020 07:00:50 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:46 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 03/10] spi: dw: Add support for client driver memory operations Date: Wed, 13 May 2020 16:00:24 +0200 Message-ID: <20200513140031.25633-4-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This minor change allow dw-spi drivers to register spi_controller_mem_ops memory operations if the platform supports it. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/spi/spi-dw.c | 3 +++ drivers/spi/spi-dw.h | 2 ++ 2 files changed, 5 insertions(+) -- 2.26.2 diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 32997f28fa5bb..d0c611c42421e 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -527,6 +527,9 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) /* Basic HW init */ spi_hw_init(dev, dws); + /* Memory ops? */ + master->mem_ops = dws->mem_ops; + if (dws->dma_ops && dws->dma_ops->dma_init) { ret = dws->dma_ops->dma_init(dws); if (ret) { diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index ed6e47b3f50da..8ecccbde10a20 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -3,6 +3,7 @@ #define DW_SPI_HEADER_H #include +#include #include /* Register offsets */ @@ -116,6 +117,7 @@ struct dw_spi { u16 bus_num; u16 num_cs; /* supported slave numbers */ void (*set_cs)(struct spi_device *spi, bool enable); + const struct spi_controller_mem_ops *mem_ops; /* Current message transfer state info */ size_t len; From patchwork Wed May 13 14:00:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546429 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B479A90 for ; Wed, 13 May 2020 14:00:50 +0000 (UTC) Received: by mail.kernel.org (Postfix) id CCC4B2065D; Wed, 13 May 2020 14:00:51 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9891F2064E; Wed, 13 May 2020 14:00:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DBqhI4Yh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9891F2064E Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378451; x=1620914451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ake5spHoiYj8zomwaQaU2aZPFaP8CHv+djGRK18gQcA=; b=DBqhI4YhKZaLAYB5tBOy+6hOd4Yp72PgZl4kSenGUTzMD+ayJAbbeX91 4Y20ju3gVKJC7EygEvR9tpvEJ6tG/5DJDe8tzsbpFbmKnhezgHtOoeg/v U7EOfbNpbhznatRgrVSpv/II4pAV4otjRTfpHkJnaXkUO8D7j64eDkMFT DVmugMdW4ye8YaLx0BPAkhikB2zLWQVT7DojnRRuVOpquD5PyUdLUO3jq ktLIyaTPLFrnpjNwIoeFSDmwmfsryJYQkF4Ael3/9OXcYIMzGOlhiH7OE nmgCekgwyGCT/U5jF6ZwWGh+Kqp+BqSHMNmIio1oyZ/dGbk86YnxxsYb0 Q==; IronPort-SDR: yS2yVnStK38NBPJvBBGdydOanJyfTZ0yQmVW5C6k6BAWGYsW5t9Pm5owVgmjbePA5G5h//Fm1u txcwS6dlzIamC4M7QCR5jXWFyr83dZFPke6/pRNZ7U5kDBKyGn1fScqLRuUG3MTi+BTPuFJ3+D zfR74OuncT4bG0m+YYOPVvl5Qxdw79xZPywhCBr6a1TK5ov0Iyc0SFDYXXIjYPNPrESHif5m0W lfxNN2NKVkyedH4BVVOexzVMFPMhLBTsKXtUU9EhNpSjgSchA7R82cAimJ/s1Gd/nako5WeL/K pSU= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="79447496" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:53 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:48 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team , Rob Herring CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 04/10] dt-bindings: spi: Add bindings for spi-dw-mchp Date: Wed, 13 May 2020 16:00:25 +0200 Message-ID: <20200513140031.25633-5-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add DT bindings for the Microsemi/Microchip SPI controller used in various SoC's. It describes the "mscc,ocelot-spi" and "mscc,jaguar2-spi" bindings. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/spi/mscc,ocelot-spi.yaml | 60 +++++++++++++++++++ .../bindings/spi/snps,dw-apb-ssi.txt | 7 +-- MAINTAINERS | 1 + 3 files changed, 63 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml new file mode 100644 index 0000000000000..a3ac0fa576553 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/spi/mscc,ocelot-spi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microsemi Vcore-III SPI Communication Controller + +maintainers: + - Alexandre Belloni + - Lars Povlsen + +allOf: + - $ref: "spi-controller.yaml#" + +description: | + The Microsemi Vcore-III SPI controller is a general purpose SPI + controller based upon the Designware SPI controller. It uses an 8 + byte rx/tx fifo. + +properties: + compatible: + enum: + - mscc,ocelot-spi + - mscc,jaguar2-spi + + interrupts: + maxItems: 1 + + reg: + minItems: 2 + items: + - description: Designware SPI registers + - description: CS override registers + + clocks: + maxItems: 1 + + reg-io-width: + description: | + The I/O register width (in bytes) implemented by this device. + items: + enum: [ 2, 4 ] + maxItems: 1 + +required: + - compatible + - reg + - clocks + +examples: + - | + spi0: spi@101000 { + compatible = "mscc,ocelot-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x101000 0x100>, <0x3c 0x18>; + interrupts = <9>; + clocks = <&ahb_clk>; + }; diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index 3ed08ee9feba4..5e1849be7bae5 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt @@ -1,10 +1,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. Required properties: -- compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi" -- reg : The register base for the controller. For "mscc,-spi", a second - register set is required (named ICPU_CFG:SPI_MST) +- compatible : "snps,dw-apb-ssi" or "amazon,alpine-dw-apb-ssi" +- reg : The register base for the controller. - interrupts : One interrupt, used by the controller. - #address-cells : <1>, as required by generic SPI binding. - #size-cells : <0>, also as required by generic SPI binding. @@ -38,4 +36,3 @@ Example: cs-gpios = <&gpio0 13 0>, <&gpio0 14 0>; }; - diff --git a/MAINTAINERS b/MAINTAINERS index 1db598723a1d8..6472240b8391b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11231,6 +11231,7 @@ L: linux-mips@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/mips/mscc.txt F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +F: Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml F: arch/mips/boot/dts/mscc/ F: arch/mips/configs/generic/board-ocelot.config F: arch/mips/generic/board-ocelot.c From patchwork Wed May 13 14:00:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546431 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BE0F90 for ; Wed, 13 May 2020 14:00:52 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 6620220659; Wed, 13 May 2020 14:00:53 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 30FF82064E; Wed, 13 May 2020 14:00:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Dxl45Evr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 30FF82064E Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378453; x=1620914453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1swg6ZG2UCq1p1EBnUde+FEZzUoK/J9xFuajuCGuPtw=; b=Dxl45EvrnIPEu6VLyGxm/45m/wV/UB0XgRqwMpf+a3FC0Yts95sc8OjV BWXASJ3DywrdS1/JkWK1NCxtLi2tGZI7Hyt4shNNh1Jr/DKYqClKl9ntJ Q0pyCGAkq5bZSyQZVQ5zRt2sCqyL4Nk3V7zbAWZ4hMpr0eiXMvywDuzPf cXBkO6fPM0KrQZcADY6MQWUj/5HMU2w8KSKJ15mZ5CsVexJT6gfOP13et Ku08MZHL5VCLn0N+5GP4wDSbtYp9xb4pegA2D7vIugSqfA1x5qNZh9Kw0 BirJ2v+nGrtIi8F89EDHKQGR1kZE+BCJX3twkmXTER+zvC0cMTnQ0Tl3Z A==; IronPort-SDR: cfxKyDHaPM5pbLKPaM4eSj2A/fLEAob5zF3xUMvB+oyrM67FDp5QWyy1mGMn7Z3wyBqz2UHzHT prsMO4DLfhymivk3sqL/LcM0O2eslS4Nw9WW5+KsZ9amLETCcaYw/4PXYHWq+7Tc4bCChQogy8 oPXaPlMr8GZpcyOPfswKc28CJ22UyNPRJWjsUIKP9D5BxFjah3XBmQuZD34nET1pOJI4vYeDtN YjHVZN4Uo/hMYAHUVxcVZuZBk7ExZKqegjNnDXOY01Yfg2x8C3ZP5vYZ02cuSHo+dQNl3F8Dic RGY= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="76507930" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:00:52 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:50 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 05/10] spi: spi-dw-mmio: Spin off MSCC platforms into spi-dw-mchp Date: Wed, 13 May 2020 16:00:26 +0200 Message-ID: <20200513140031.25633-6-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This patch spins off the MSCC platforms into a separate driver, as adding new platforms from the MSCC/Microchip product lines will further complicate (clutter) the original driver. The new 'spi-dw-mchp' driver still builds on the dw-spi foundation. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- MAINTAINERS | 1 + arch/mips/configs/generic/board-ocelot.config | 2 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-dw-mchp.c | 232 ++++++++++++++++++ drivers/spi/spi-dw-mmio.c | 93 ------- 6 files changed, 242 insertions(+), 94 deletions(-) create mode 100644 drivers/spi/spi-dw-mchp.c -- 2.26.2 diff --git a/MAINTAINERS b/MAINTAINERS index 6472240b8391b..de64fd4548697 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2085,6 +2085,7 @@ M: Steen Hegelund M: Microchip Linux Driver Support L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) F: arch/arm64/boot/dts/microchip/ +F: drivers/spi/spi-dw-mchp.c N: sparx5 S: Supported diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config index 7626f2a75b03f..6dbae76268a49 100644 --- a/arch/mips/configs/generic/board-ocelot.config +++ b/arch/mips/configs/generic/board-ocelot.config @@ -38,7 +38,7 @@ CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_BITBANG=y CONFIG_SPI_DESIGNWARE=y -CONFIG_SPI_DW_MMIO=y +CONFIG_SPI_DW_MCHP=y CONFIG_SPI_SPIDEV=y CONFIG_PINCTRL=y diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 741b9140992a8..77eb580b9f51f 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -238,6 +238,13 @@ config SPI_DW_MMIO tristate "Memory-mapped io interface driver for DW SPI core" depends on SPI_DESIGNWARE +config SPI_DW_MCHP + tristate "Memory-mapped io interface driver using DW SPI core of MSCC SoCs" + default y if ARCH_SPARX5 + default y if SOC_VCOREIII + select SPI_DESIGNWARE + select SPI_DW_MMIO + config SPI_DLN2 tristate "Diolan DLN-2 USB SPI adapter" depends on MFD_DLN2 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 28f601327f8c7..be8a52d90721b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o obj-$(CONFIG_SPI_DLN2) += spi-dln2.o obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o +obj-$(CONFIG_SPI_DW_MCHP) += spi-dw-mchp.o obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o obj-$(CONFIG_SPI_EFM32) += spi-efm32.o diff --git a/drivers/spi/spi-dw-mchp.c b/drivers/spi/spi-dw-mchp.c new file mode 100644 index 0000000000000..0828a7616d9ab --- /dev/null +++ b/drivers/spi/spi-dw-mchp.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Memory-mapped interface driver for MSCC SoCs + * + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "spi-dw.h" + +#define DRIVER_NAME "dw_spi_mchp" + +#define MAX_CS 4 + +#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 +#define OCELOT_IF_SI_OWNER_OFFSET 4 +#define JAGUAR2_IF_SI_OWNER_OFFSET 6 +#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0) +#define MSCC_IF_SI_OWNER_SISL 0 +#define MSCC_IF_SI_OWNER_SIBM 1 +#define MSCC_IF_SI_OWNER_SIMC 2 + +#define MSCC_SPI_MST_SW_MODE 0x14 +#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) +#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) + +struct dw_spi_mchp_props { + const char *syscon_name; + u32 si_owner_bit; +}; + +struct dw_spi_mchp { + struct dw_spi dws; + struct clk *clk; + void __iomem *read_map; + struct regmap *syscon; + void __iomem *spi_mst; + const struct dw_spi_mchp_props *props; + u32 gen_owner; +}; + +static const struct dw_spi_mchp_props dw_spi_mchp_props_ocelot = { + .syscon_name = "mscc,ocelot-cpu-syscon", + .si_owner_bit = 4, +}; + +static const struct dw_spi_mchp_props dw_spi_mchp_props_jaguar2 = { + .syscon_name = "mscc,ocelot-cpu-syscon", + .si_owner_bit = 6, +}; + +/* + * The Designware SPI controller (referred to as master in the documentation) + * automatically deasserts chip select when the tx fifo is empty. The chip + * selects then needs to be either driven as GPIOs or, for the first 4 using the + * the SPI boot controller registers. the final chip select is an OR gate + * between the Designware SPI controller and the SPI boot controller. + */ +static void dw_spi_mchp_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mchp *dwsmchp = container_of(dws, struct dw_spi_mchp, + dws); + u32 cs = spi->chip_select; + + if (cs < 4) { + u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; + + if (!enable) + sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); + + writel(sw_mode, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE); + } + + dw_spi_set_cs(spi, enable); +} + +static int dw_spi_mchp_init(struct platform_device *pdev, + struct dw_spi *dws, + struct dw_spi_mchp *dwsmchp, + const struct dw_spi_mchp_props *props) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res && resource_size(res) > 0) { + dwsmchp->spi_mst = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dwsmchp->spi_mst)) { + dev_err(&pdev->dev, "SPI_MST region map failed\n"); + return PTR_ERR(dwsmchp->spi_mst); + } + } + + dwsmchp->syscon = + syscon_regmap_lookup_by_compatible(props->syscon_name); + if (IS_ERR(dwsmchp->syscon)) { + dev_err(&pdev->dev, "No syscon map %s\n", props->syscon_name); + return PTR_ERR(dwsmchp->syscon); + } + dwsmchp->props = props; + + /* Deassert all CS */ + if (dwsmchp->spi_mst) + writel(0, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE); + + /* Select the owner of the SI interface */ + regmap_update_bits(dwsmchp->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, + MSCC_IF_SI_OWNER_MASK << props->si_owner_bit, + MSCC_IF_SI_OWNER_SIMC << props->si_owner_bit); + + dwsmchp->dws.set_cs = dw_spi_mchp_set_cs; + + return 0; +} + +static int dw_spi_mchp_probe(struct platform_device *pdev) +{ + const struct dw_spi_mchp_props *props; + struct dw_spi_mchp *dwsmchp; + struct dw_spi *dws; + int ret; + int num_cs, rx_sample_dly; + + dwsmchp = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mchp), + GFP_KERNEL); + if (!dwsmchp) + return -ENOMEM; + + dws = &dwsmchp->dws; + + /* Get basic io resource and map it */ + dws->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dws->regs)) { + dev_err(&pdev->dev, "SPI region map failed\n"); + return PTR_ERR(dws->regs); + } + + dws->irq = of_irq_get(pdev->dev.of_node, 0); + if (dws->irq < 0) + dev_info(&pdev->dev, "no irq, using polled mode\n"); + + dwsmchp->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(dwsmchp->clk)) + return PTR_ERR(dwsmchp->clk); + ret = clk_prepare_enable(dwsmchp->clk); + if (ret) + return ret; + + dws->bus_num = pdev->id; + + dws->max_freq = clk_get_rate(dwsmchp->clk); + + device_property_read_u32(&pdev->dev, "reg-io-width", + &dws->reg_io_width); + + num_cs = MAX_CS; + + device_property_read_u32(&pdev->dev, "num-cs", &num_cs); + + dws->num_cs = num_cs; + + rx_sample_dly = 0; + device_property_read_u32(&pdev->dev, "spi-rx-delay-us", &rx_sample_dly); + dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly, + (dws->max_freq / 1000000)); + + props = device_get_match_data(&pdev->dev); + if (props) + ret = dw_spi_mchp_init(pdev, dws, dwsmchp, props); + else + ret = -EINVAL; + if (ret) + goto out; + + ret = dw_spi_add_host(&pdev->dev, dws); + if (ret) + goto out; + + platform_set_drvdata(pdev, dwsmchp); + return 0; + +out: + clk_disable_unprepare(dwsmchp->clk); + return ret; +} + +static int dw_spi_mchp_remove(struct platform_device *pdev) +{ + struct dw_spi_mchp *dwsmchp = platform_get_drvdata(pdev); + + dw_spi_remove_host(&dwsmchp->dws); + clk_disable_unprepare(dwsmchp->clk); + + return 0; +} + +static const struct of_device_id dw_spi_mchp_of_match[] = { + { .compatible = "mscc,ocelot-spi", .data = &dw_spi_mchp_props_ocelot}, + { .compatible = "mscc,jaguar2-spi", .data = &dw_spi_mchp_props_jaguar2}, + { /* end of table */} +}; +MODULE_DEVICE_TABLE(of, dw_spi_mchp_of_match); + +static struct platform_driver dw_spi_mchp_driver = { + .probe = dw_spi_mchp_probe, + .remove = dw_spi_mchp_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = dw_spi_mchp_of_match, + }, +}; +module_platform_driver(dw_spi_mchp_driver); + +MODULE_AUTHOR("Lars Povlsen "); +MODULE_DESCRIPTION("Memory-mapped I/O interface DW SPI driver for MSCC SoCs"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 384a3ab6dc2d0..dc5db548fbcbc 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -32,97 +32,6 @@ struct dw_spi_mmio { void *priv; }; -#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 -#define OCELOT_IF_SI_OWNER_OFFSET 4 -#define JAGUAR2_IF_SI_OWNER_OFFSET 6 -#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0) -#define MSCC_IF_SI_OWNER_SISL 0 -#define MSCC_IF_SI_OWNER_SIBM 1 -#define MSCC_IF_SI_OWNER_SIMC 2 - -#define MSCC_SPI_MST_SW_MODE 0x14 -#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) -#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) - -struct dw_spi_mscc { - struct regmap *syscon; - void __iomem *spi_mst; -}; - -/* - * The Designware SPI controller (referred to as master in the documentation) - * automatically deasserts chip select when the tx fifo is empty. The chip - * selects then needs to be either driven as GPIOs or, for the first 4 using the - * the SPI boot controller registers. the final chip select is an OR gate - * between the Designware SPI controller and the SPI boot controller. - */ -static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) -{ - struct dw_spi *dws = spi_master_get_devdata(spi->master); - struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); - struct dw_spi_mscc *dwsmscc = dwsmmio->priv; - u32 cs = spi->chip_select; - - if (cs < 4) { - u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; - - if (!enable) - sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); - - writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); - } - - dw_spi_set_cs(spi, enable); -} - -static int dw_spi_mscc_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio, - const char *cpu_syscon, u32 if_si_owner_offset) -{ - struct dw_spi_mscc *dwsmscc; - - dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL); - if (!dwsmscc) - return -ENOMEM; - - dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(dwsmscc->spi_mst)) { - dev_err(&pdev->dev, "SPI_MST region map failed\n"); - return PTR_ERR(dwsmscc->spi_mst); - } - - dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon); - if (IS_ERR(dwsmscc->syscon)) - return PTR_ERR(dwsmscc->syscon); - - /* Deassert all CS */ - writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE); - - /* Select the owner of the SI interface */ - regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, - MSCC_IF_SI_OWNER_MASK << if_si_owner_offset, - MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset); - - dwsmmio->dws.set_cs = dw_spi_mscc_set_cs; - dwsmmio->priv = dwsmscc; - - return 0; -} - -static int dw_spi_mscc_ocelot_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio) -{ - return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon", - OCELOT_IF_SI_OWNER_OFFSET); -} - -static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev, - struct dw_spi_mmio *dwsmmio) -{ - return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon", - JAGUAR2_IF_SI_OWNER_OFFSET); -} - static int dw_spi_alpine_init(struct platform_device *pdev, struct dw_spi_mmio *dwsmmio) { @@ -225,8 +134,6 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "snps,dw-apb-ssi", }, - { .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init}, - { .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init}, { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init}, { .compatible = "renesas,rzn1-spi", }, { /* end of table */} From patchwork Wed May 13 14:00:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546435 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8BC390 for ; Wed, 13 May 2020 14:00:55 +0000 (UTC) Received: by mail.kernel.org (Postfix) id E32C120690; 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Wed, 13 May 2020 07:00:57 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:52 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team , Rob Herring CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 06/10] dt-bindings: spi: spi-dw-mchp: Add Sparx5 support Date: Wed, 13 May 2020 16:00:27 +0200 Message-ID: <20200513140031.25633-7-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add DT bindings for the Sparx5 SPI driver. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- .../bindings/spi/mscc,ocelot-spi.yaml | 49 +++++++++++++++---- 1 file changed, 39 insertions(+), 10 deletions(-) -- 2.26.2 diff --git a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml index a3ac0fa576553..8beecde4b0880 100644 --- a/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml +++ b/Documentation/devicetree/bindings/spi/mscc,ocelot-spi.yaml @@ -23,15 +23,23 @@ properties: enum: - mscc,ocelot-spi - mscc,jaguar2-spi + - microchip,sparx5-spi interrupts: maxItems: 1 reg: minItems: 2 - items: - - description: Designware SPI registers - - description: CS override registers + maxItems: 3 + oneOf: + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - items: + - description: Designware SPI registers + - description: CS override registers (Not sparx5). + - description: Direct mapped SPI read area. If provided, the + driver will register spi_mem_op's to take advantage of it. clocks: maxItems: 1 @@ -43,6 +51,23 @@ properties: enum: [ 2, 4 ] maxItems: 1 + spi-rx-delay-us: + description: | + The delay (in usec) of the RX signal sample position. This can + be used to tne the RX timing in order to acheive higher + speeds. This is used for all devices on the bus. + default: 0 + maxItems: 1 + + interface-mapping-mask: + description: | + On the Sparx5 variant, two different busses are connected to the + controller. This property is a mask per chip-select, indicating + whether the CS should go to one or the other interface. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + maxItems: 1 + required: - compatible - reg @@ -50,11 +75,15 @@ required: examples: - | - spi0: spi@101000 { - compatible = "mscc,ocelot-spi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x101000 0x100>, <0x3c 0x18>; - interrupts = <9>; - clocks = <&ahb_clk>; + #include + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x00104000 0x40>, <0 0>, <0x3000000 0x4000000>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; }; From patchwork Wed May 13 14:00:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546437 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7A55390 for ; Wed, 13 May 2020 14:00:57 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 93D6820708; Wed, 13 May 2020 14:00:58 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa1.microchip.iphmx.com (esa1.microchip.iphmx.com [68.232.147.91]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D1B220659; Wed, 13 May 2020 14:00:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="AEP4/mP4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D1B220659 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=Lars.Povlsen@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1589378458; x=1620914458; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DD4LaygJ0MQ0zaaJOlyQ+qY2g/ubHGxZEC346Rx98Bw=; b=AEP4/mP4HbTp4RqhFC7cIa+vVRb5hVpdkLzIG1Cn1E2ynRdqJ0A18v8v pmee+I/n9uPXII4Ixo1hr+V0DhcIMx4PshAIMjcS7VDZUPhm5BoOPQW6q kbd7EZKjuDBHB/uak3Y+rZTAqOmODAhbPzZpb3rbbkmBlDb1ZLfu4S3iq 3hgDIUbojqoa4QLEqjz4iD4GLvU5mOZ7A1x9/KCt5KviBH3loK6DzaGGH i/nBdf+MMwMvUBO2s+73vrEbX/XvlrfI0NCsue2mZAkpy0gfC6q5dA6BE LZN63mFv11+h3KrHYm+3borLUcCKOjjjuLb34CPNMtv+qYfHfhwyO2gE4 w==; IronPort-SDR: Gdiuw+xCaXFKEgjuCPbTKtA4QIfkMfKZcyb5vkMlHX1E1wru1WWewHF6r2LSZdNZOpQhM/EiP5 RkLef45i8bUb9KJBnRkJd4nrZF9zsSEoYlN8OyWv6F3OI+/NdfHxmKWHKrQyZAFS1ul4k0sNgp fDU6dbf2vhUdMp927ZQwUd3PMHEGImVv1JIy52OeZZMfIOtt9Pcy+E1/UQD94ddmtVszhvgf6J ILIbRL6ZUK5lGmu7kOfrv+ZjI8VgYXfVBuP9ugc47KKhLbErXlyBRh2hkr/WGM2hJ38uNcrFIZ mtA= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="79447574" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:00:58 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:00 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:55 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 07/10] spi: spi-dw-mchp: Add Sparx5 support Date: Wed, 13 May 2020 16:00:28 +0200 Message-ID: <20200513140031.25633-8-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds support for the Sparx5 SoC in the spi-dw-mchp SPI controller. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- drivers/spi/spi-dw-mchp.c | 211 ++++++++++++++++++++++++++++++++++---- 1 file changed, 189 insertions(+), 22 deletions(-) -- 2.26.2 diff --git a/drivers/spi/spi-dw-mchp.c b/drivers/spi/spi-dw-mchp.c index 0828a7616d9ab..3abdd44a550ea 100644 --- a/drivers/spi/spi-dw-mchp.c +++ b/drivers/spi/spi-dw-mchp.c @@ -28,21 +28,22 @@ #define MAX_CS 4 -#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 -#define OCELOT_IF_SI_OWNER_OFFSET 4 -#define JAGUAR2_IF_SI_OWNER_OFFSET 6 #define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0) #define MSCC_IF_SI_OWNER_SISL 0 #define MSCC_IF_SI_OWNER_SIBM 1 #define MSCC_IF_SI_OWNER_SIMC 2 #define MSCC_SPI_MST_SW_MODE 0x14 -#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13) -#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5) struct dw_spi_mchp_props { const char *syscon_name; - u32 si_owner_bit; + u32 general_ctrl_off; + u32 si_owner_bit, si_owner2_bit; + u32 pinctrl_bit_off; + u32 cs_bit_off; + u32 ss_force_ena_off; + u32 ss_force_val_off; + u32 bootmaster_cs; }; struct dw_spi_mchp { @@ -53,44 +54,176 @@ struct dw_spi_mchp { void __iomem *spi_mst; const struct dw_spi_mchp_props *props; u32 gen_owner; + u32 if2mask; }; static const struct dw_spi_mchp_props dw_spi_mchp_props_ocelot = { .syscon_name = "mscc,ocelot-cpu-syscon", + .general_ctrl_off = 0x24, .si_owner_bit = 4, + .pinctrl_bit_off = 13, + .cs_bit_off = 5, + .bootmaster_cs = 0, }; static const struct dw_spi_mchp_props dw_spi_mchp_props_jaguar2 = { .syscon_name = "mscc,ocelot-cpu-syscon", + .general_ctrl_off = 0x24, .si_owner_bit = 6, + .pinctrl_bit_off = 13, + .cs_bit_off = 5, + .bootmaster_cs = 0, +}; + +static const struct dw_spi_mchp_props dw_spi_mchp_props_sparx5 = { + .syscon_name = "microchip,sparx5-cpu-syscon", + .general_ctrl_off = 0x88, + .si_owner_bit = 6, + .si_owner2_bit = 4, + .ss_force_ena_off = 0xa4, + .ss_force_val_off = 0xa8, + .bootmaster_cs = 0, }; /* - * The Designware SPI controller (referred to as master in the documentation) - * automatically deasserts chip select when the tx fifo is empty. The chip - * selects then needs to be either driven as GPIOs or, for the first 4 using the - * the SPI boot controller registers. the final chip select is an OR gate - * between the Designware SPI controller and the SPI boot controller. + * Set the owner of the SPI interface */ -static void dw_spi_mchp_set_cs(struct spi_device *spi, bool enable) +static void dw_spi_mchp_set_owner(struct dw_spi_mchp *dwsmchp, + const struct dw_spi_mchp_props *props, + u8 owner, u8 owner2) +{ + u32 val, msk; + + val = (owner << props->si_owner_bit); + msk = (MSCC_IF_SI_OWNER_MASK << props->si_owner_bit); + if (props->si_owner2_bit) { + val |= owner2 << props->si_owner2_bit; + msk |= (MSCC_IF_SI_OWNER_MASK << props->si_owner2_bit); + } + if (dwsmchp->gen_owner != val) { + regmap_update_bits(dwsmchp->syscon, props->general_ctrl_off, + msk, val); + dwsmchp->gen_owner = val; + } +} + +static void dw_spi_mchp_set_cs_owner(struct dw_spi_mchp *dwsmchp, + const struct dw_spi_mchp_props *props, + u8 cs, u8 owner) { + u8 dummy = (owner == MSCC_IF_SI_OWNER_SIBM ? + MSCC_IF_SI_OWNER_SIMC : MSCC_IF_SI_OWNER_SIBM); + if (props->si_owner2_bit && (dwsmchp->if2mask & BIT(cs))) { + /* SPI2 */ + dw_spi_mchp_set_owner(dwsmchp, props, dummy, owner); + } else { + /* SPI1 */ + dw_spi_mchp_set_owner(dwsmchp, props, owner, dummy); + } +} + +/* + * The Designware SPI controller (referred to as master in the + * documentation) automatically deasserts chip select when the tx fifo + * is empty. The chip selects then needs to be either driven as GPIOs + * or, for the first 4 using the the SPI boot controller + * registers. the final chip select is an OR gate between the + * Designware SPI controller and the SPI boot controller. nselect is + * an active low signal + */ +static void dw_spi_mchp_set_cs(struct spi_device *spi, bool nEnable) +{ + bool enable = !nEnable; /* This keeps changing in the API... */ struct dw_spi *dws = spi_master_get_devdata(spi->master); struct dw_spi_mchp *dwsmchp = container_of(dws, struct dw_spi_mchp, dws); - u32 cs = spi->chip_select; + const struct dw_spi_mchp_props *props = dwsmchp->props; + u8 cs = spi->chip_select; - if (cs < 4) { - u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE; + if (enable) + dw_spi_mchp_set_cs_owner(dwsmchp, props, cs, + MSCC_IF_SI_OWNER_SIMC); - if (!enable) - sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs)); + if (dwsmchp->spi_mst && (cs < MAX_CS)) { + u32 sw_mode; + if (enable) + sw_mode = BIT(props->pinctrl_bit_off) | + (BIT(cs) << props->cs_bit_off); + else + sw_mode = 0; writel(sw_mode, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE); + } else if (props->ss_force_ena_off) { + if (enable) { + /* Ensure CS toggles, so start off all disabled */ + regmap_write(dwsmchp->syscon, props->ss_force_val_off, + ~0); + /* CS override drive enable */ + regmap_write(dwsmchp->syscon, props->ss_force_ena_off, + 1); + /* Allow settle */ + udelay(1); + /* Now set CSx enabled */ + regmap_write(dwsmchp->syscon, props->ss_force_val_off, + ~BIT(cs)); + } else { + /* CS value */ + regmap_write(dwsmchp->syscon, props->ss_force_val_off, + ~0); + /* CS override drive disable */ + regmap_write(dwsmchp->syscon, props->ss_force_ena_off, + 0); + } } - dw_spi_set_cs(spi, enable); + dw_spi_set_cs(spi, nEnable); +} + +static int dw_mchp_bootmaster_exec_mem_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct spi_device *spi = mem->spi; + int ret = -ENOTSUPP; + + /* Only reads, addrsize 1..4 */ + if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 || + op->data.dir != SPI_MEM_DATA_IN) + return ret; + + /* Only handle (normal+fast) 3/4 bytes read */ + if (op->cmd.opcode != SPINOR_OP_READ && + op->cmd.opcode != SPINOR_OP_READ_FAST && + op->cmd.opcode != SPINOR_OP_READ_4B && + op->cmd.opcode != SPINOR_OP_READ_FAST_4B) + return ret; + + /* CS0..3, only 16M reach */ + if ((spi->chip_select < MAX_CS) && + (op->addr.val + op->data.nbytes) < SZ_16M) { + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mchp *dwsmchp = container_of(dws, + struct dw_spi_mchp, + dws); + const struct dw_spi_mchp_props *props = dwsmchp->props; + u8 __iomem *src = dwsmchp->read_map + + (spi->chip_select * SZ_16M) + op->addr.val; + + if (props->bootmaster_cs != spi->chip_select) + return ret; + + /* Make boot master owner of SI interface */ + dw_spi_mchp_set_cs_owner(dwsmchp, props, spi->chip_select, + MSCC_IF_SI_OWNER_SIBM); + memcpy(op->data.buf.in, src, op->data.nbytes); + ret = op->data.nbytes; + } + return ret; } +static const struct spi_controller_mem_ops dw_mchp_bootmaster_mem_ops = { + .exec_op = dw_mchp_bootmaster_exec_mem_op, +}; + static int dw_spi_mchp_init(struct platform_device *pdev, struct dw_spi *dws, struct dw_spi_mchp *dwsmchp, @@ -107,6 +240,18 @@ static int dw_spi_mchp_init(struct platform_device *pdev, } } + /* See if we have a direct read window */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (res && resource_size(res) >= (SZ_16M*MAX_CS)) { + void __iomem *ptr = devm_ioremap_resource(&pdev->dev, res); + + if (!IS_ERR(ptr)) { + dwsmchp->read_map = ptr; + dws->mem_ops = &dw_mchp_bootmaster_mem_ops; + dev_info(&pdev->dev, "Enabling fast memory operations\n"); + } + } + dwsmchp->syscon = syscon_regmap_lookup_by_compatible(props->syscon_name); if (IS_ERR(dwsmchp->syscon)) { @@ -119,10 +264,9 @@ static int dw_spi_mchp_init(struct platform_device *pdev, if (dwsmchp->spi_mst) writel(0, dwsmchp->spi_mst + MSCC_SPI_MST_SW_MODE); - /* Select the owner of the SI interface */ - regmap_update_bits(dwsmchp->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL, - MSCC_IF_SI_OWNER_MASK << props->si_owner_bit, - MSCC_IF_SI_OWNER_SIMC << props->si_owner_bit); + /* SPI2 mapping bitmask */ + device_property_read_u32(&pdev->dev, "interface-mapping-mask", + &dwsmchp->if2mask); dwsmchp->dws.set_cs = dw_spi_mchp_set_cs; @@ -180,6 +324,27 @@ static int dw_spi_mchp_probe(struct platform_device *pdev) dws->rx_sample_dly = DIV_ROUND_UP(rx_sample_dly, (dws->max_freq / 1000000)); + if (pdev->dev.of_node) { + int i; + + for (i = 0; i < dws->num_cs; i++) { + int cs_gpio = of_get_named_gpio(pdev->dev.of_node, + "cs-gpios", i); + + if (cs_gpio == -EPROBE_DEFER) { + ret = cs_gpio; + goto out; + } + + if (gpio_is_valid(cs_gpio)) { + ret = devm_gpio_request(&pdev->dev, cs_gpio, + dev_name(&pdev->dev)); + if (ret) + goto out; + } + } + } + props = device_get_match_data(&pdev->dev); if (props) ret = dw_spi_mchp_init(pdev, dws, dwsmchp, props); @@ -213,6 +378,8 @@ static int dw_spi_mchp_remove(struct platform_device *pdev) static const struct of_device_id dw_spi_mchp_of_match[] = { { .compatible = "mscc,ocelot-spi", .data = &dw_spi_mchp_props_ocelot}, { .compatible = "mscc,jaguar2-spi", .data = &dw_spi_mchp_props_jaguar2}, + { .compatible = "microchip,sparx5-spi", + .data = &dw_spi_mchp_props_sparx5}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mchp_of_match); From patchwork Wed May 13 14:00:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546439 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22C9290 for ; Wed, 13 May 2020 14:01:00 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 3CF9D20671; Wed, 13 May 2020 14:01:01 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa5.microchip.iphmx.com (esa5.microchip.iphmx.com [216.71.150.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 053CD2065D; Wed, 13 May 2020 14:01:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="17H8mw1A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 053CD2065D Authentication-Results: mail.kernel.org; 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d="scan'208";a="75774926" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:01:00 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:02 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:57 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 08/10] arm64: dts: sparx5: Add SPI controller Date: Wed, 13 May 2020 16:00:29 +0200 Message-ID: <20200513140031.25633-9-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This adds a SPI controller to the Microchip Sparx5 SoC Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index b5f2d088af30e..daa216978887d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -14,6 +14,7 @@ / { #size-cells = <1>; aliases { + spi0 = &spi0; serial0 = &uart0; serial1 = &uart1; }; @@ -144,6 +145,21 @@ uart1: serial@600102000 { status = "disabled"; }; + spi0: spi@600104000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-spi"; + reg = <0x6 0x00104000 0x40>, <0 0 0>, + <0x3 0x0 0x4000000>; + num-cs = <16>; + reg-io-width = <4>; + reg-shift = <2>; + clocks = <&ahb_clk>; + interrupts = ; + + status = "disabled"; + }; + timer1: timer@600105000 { compatible = "snps,dw-apb-timer"; reg = <0x6 0x00105000 0x1000>; From patchwork Wed May 13 14:00:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546441 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B772660D for ; Wed, 13 May 2020 14:01:01 +0000 (UTC) Received: by mail.kernel.org (Postfix) id D156920690; Wed, 13 May 2020 14:01:02 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 906DE2065D; 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IronPort-SDR: rJGSY8q8PbCBR7XcB8/siK/Ft2wQh8SFJgTIYblb9ci/I5wfzXdWBC78Jm/Ve7XQKMhDlIbST9 PD7KOxcdgKauy9aexCg2LsfVU5x6IQA8pvNlIzcHBFDY39UQitL9AMbrHfagYhu8MzJWKtoRcq SsVJTwAy13eWseriiCmCbYjFl5SHrWYlKKIiIXhtq35zn6kF9zF9XX3lQZ5J8FDKchWx2UiXur IeFUqBeNMTvYXKvBBeeLIoyLc4qomECTkTOVpg2xL03Ya+WaZH8ONXc2xAgLFcikFQNIvHnfCh wNA= X-IronPort-AV: E=Sophos;i="5.73,388,1583218800"; d="scan'208";a="73314076" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:01:02 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:01 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:00:59 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 09/10] arm64: dts: sparx5: Add spi-nor support Date: Wed, 13 May 2020 16:00:30 +0200 Message-ID: <20200513140031.25633-10-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This add spi-nor device nodes to the Sparx5 reference boards. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++-- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 9 +++++++++ arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 9 +++++++++ 4 files changed, 30 insertions(+), 2 deletions(-) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index daa216978887d..330fd8b096d4c 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -155,8 +155,9 @@ spi0: spi@600104000 { reg-io-width = <4>; reg-shift = <2>; clocks = <&ahb_clk>; - interrupts = ; - + /* NB: Polled mode - next line commented out + * interrupts = ; + */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 573309fe45823..d8b5d23abfab0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -39,6 +39,15 @@ &sdhci0 { microchip,clock-delay = <10>; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; /* input clock */ + reg = <0>; /* CS0 */ + }; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 18a535a043686..628a05d3f57ce 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -38,6 +38,15 @@ gpio-restart { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index d71f11a10b3d2..fb0bc3b241204 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -51,6 +51,15 @@ i2cmux_s32: i2cmux-3 { }; }; +&spi0 { + status = "okay"; + spi-flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <8000000>; + reg = <0>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; From patchwork Wed May 13 14:00:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lars Povlsen X-Patchwork-Id: 11546445 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF05990 for ; Wed, 13 May 2020 14:01:03 +0000 (UTC) Received: by mail.kernel.org (Postfix) id C78EE2065D; Wed, 13 May 2020 14:01:04 +0000 (UTC) Delivered-To: soc@kernel.org Received: from esa4.microchip.iphmx.com (esa4.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 72CC8207C3; Wed, 13 May 2020 14:01:04 +0000 (UTC) Authentication-Results: mail.kernel.org; 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d="scan'208";a="73314086" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 May 2020 07:01:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 13 May 2020 07:01:04 -0700 Received: from soft-dev15.microsemi.net (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Wed, 13 May 2020 07:01:02 -0700 From: Lars Povlsen List-Id: To: Mark Brown , SoC Team CC: Lars Povlsen , Microchip Linux Driver Support , , , , , Alexandre Belloni Subject: [PATCH 10/10] arm64: dts: sparx5: Add spi-nand devices Date: Wed, 13 May 2020 16:00:31 +0200 Message-ID: <20200513140031.25633-11-lars.povlsen@microchip.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200513140031.25633-1-lars.povlsen@microchip.com> References: <20200513140031.25633-1-lars.povlsen@microchip.com> MIME-Version: 1.0 This patch add spi-nand DT nodes to the applicable Sparx5 boards. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++++ .../boot/dts/microchip/sparx5_pcb134.dts | 22 ++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135.dts | 23 +++++++++++++++++++ 4 files changed, 72 insertions(+) -- 2.26.2 diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 330fd8b096d4c..60629861a5157 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -193,6 +193,26 @@ gpio: pinctrl@6110101e0 { interrupts = ; #interrupt-cells = <2>; + cs1_pins: cs1-pins { + pins = "GPIO_16"; + function = "si"; + }; + + cs2_pins: cs2-pins { + pins = "GPIO_17"; + function = "si"; + }; + + cs3_pins: cs3-pins { + pins = "GPIO_18"; + function = "si"; + }; + + si2_pins: si2-pins { + pins = "GPIO_39", "GPIO_40", "GPIO_41"; + function = "si2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index d8b5d23abfab0..94c4c3fd5a786 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -46,6 +46,13 @@ spi-flash@0 { spi-max-frequency = <8000000>; /* input clock */ reg = <0>; /* CS0 */ }; + spi-flash@1 { + compatible = "spi-nand"; + pinctrl-0 = <&cs1_pins>; + pinctrl-names = "default"; + spi-max-frequency = <8000000>; + reg = <1>; /* CS1 */ + }; }; &i2c1 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts index feee4e99ff57c..9e8dc725a954a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts @@ -15,3 +15,25 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */ + spi-rx-delay-us = <500>; /* Tune for speed */ + /* Dedicated SPI2 interface */ + spi-flash@e { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + spi-max-frequency = <42000000>; + reg = <14>; + }; +}; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts index 20e409a9be196..a31e10911dbaf 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts @@ -15,3 +15,26 @@ memory@0 { reg = <0x00000000 0x00000000 0x10000000>; }; }; + +&gpio { + cs14_pins: cs14-pins { + pins = "GPIO_44"; + function = "si"; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&si2_pins>; + pinctrl-names = "default"; + interface-mapping-mask = <0x4000>; /* NAND CS14 = SPI2 */ + spi-rx-delay-us = <500>; /* Tune for speed */ + /* Dedicated SPI2 interface */ + spi-flash@e { + compatible = "spi-nand"; + pinctrl-0 = <&cs14_pins>; + pinctrl-names = "default"; + spi-max-frequency = <42000000>; + reg = <14>; + }; +};