From patchwork Sun May 17 16:21:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11554185 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3F19E913 for ; Sun, 17 May 2020 16:22:35 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 165AC2070A for ; Sun, 17 May 2020 16:22:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="pRVwVT/U" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 165AC2070A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:56152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jaM3e-0007fu-8B for patchwork-qemu-devel@patchwork.kernel.org; Sun, 17 May 2020 12:22:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jaM2r-000623-JO for qemu-devel@nongnu.org; Sun, 17 May 2020 12:21:45 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:40548) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jaM2q-0006kI-Hu for qemu-devel@nongnu.org; Sun, 17 May 2020 12:21:45 -0400 Received: by mail-pj1-x1043.google.com with SMTP id ci23so295576pjb.5 for ; Sun, 17 May 2020 09:21:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IKqSsLhQC2QhDVU4F5SnGseXmbR5yG/zUVktutymlAA=; b=pRVwVT/UIu66NLNKgJ1Uc8pOmlU3Jva7b6yje6lRz4QraVwOuCbMFzixR1NundotIo 1QxdPB1ACr5ANxZdpbx5ilbnJUKsH1rhDokltV+JrxCKuALCgiissD0YZxpG1YhehePc tGETJndJHJUjdEKf6iWOosVB3yVF8N8JprgA+rFQraB+Nv4R3A7kI7JMu9QxRjkg//N0 8NIJ/EC08bTUBt4vYeawQhWQ9oNovxBcF63gpjd+9T6t7J4Ii/Z5fJQc/sDJ6PieyLjV Fv2EtlKAJMrdOTs8KVBtTEuKN85IPvOFRNA3JVsRy8X9+ZO4FwOY/vFC5YaRiVUk6B7F DYmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=IKqSsLhQC2QhDVU4F5SnGseXmbR5yG/zUVktutymlAA=; b=Y6D66jVIJUzvepW37XD0GIlL9fFNqEgTTuWhdUPZEW7hDIOYcf+4wgpgwDghVKpeh6 KmUIEzlA+l/vjqNqRX6+x9YPUOQQ4LrFPZpR7KzaiiRxgmjQYU8zcsJpgFh/l/y3zKJK pTsLXs5w/lJgkZP8DWXH1/2ZJewupR7mrkxxdVFNR88N7JXqqb9iNpbnMj71ajaJ34t2 Qiarbd9sDUfSHm8Ve+CDRVcRODBw9YFvN7RZeFadBoOmRMppC4AHWOcJZ2J0F8+8cjUE Dwm8bsCH+zCeNWWwQDaTaO+ojWXEPUV9MVAdyuYSsTd27N2rmtPdEbvtKlk4eyHmPiws Wr4Q== X-Gm-Message-State: AOAM5315NUownrbJN+LpHF3R1dlqRQ+5m/jGEZSXVx5PWeCPr88HDObD uIQtlhQJ3o7lSJQ02ntTeGA= X-Google-Smtp-Source: ABdhPJxpInwON3cuq1M1xsmqbVKCruLFL/9C4Lh759yg1fzt5SjDmBpjEbYODtuQuZX6XtSaVDXCdg== X-Received: by 2002:a17:902:930c:: with SMTP id bc12mr12637537plb.255.1589732503248; Sun, 17 May 2020 09:21:43 -0700 (PDT) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id h3sm577799pjk.10.2020.05.17.09.21.42 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 May 2020 09:21:42 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 1/8] hw: Move i.MX watchdog driver to hw/watchdog Date: Sun, 17 May 2020 09:21:28 -0700 Message-Id: <20200517162135.110364-2-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=groeck7@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In preparation for a full implementation, move i.MX watchdog driver from hw/misc to hw/watchdog. While at it, add the watchdog files to MAINTAINERS. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck --- v3: No change v2: Instead of auto-selecting WDT_IMX2 if IMX is enabled, select it explicitly for each emulation using it. In Makefile, fix CONFIG_WDT_IMX -> CONFIG_WDT_IMX2 Added Philippe's Reviewed-by: tag MAINTAINERS | 2 ++ hw/arm/Kconfig | 3 +++ hw/misc/Makefile.objs | 1 - hw/watchdog/Kconfig | 3 +++ hw/watchdog/Makefile.objs | 1 + hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} | 2 +- include/hw/arm/fsl-imx6.h | 2 +- include/hw/arm/fsl-imx6ul.h | 2 +- include/hw/arm/fsl-imx7.h | 2 +- include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} | 0 10 files changed, 13 insertions(+), 5 deletions(-) rename hw/{misc/imx2_wdt.c => watchdog/wdt_imx2.c} (98%) rename include/hw/{misc/imx2_wdt.h => watchdog/wdt_imx2.h} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 8aa8efaf1d..998eb5053c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -631,8 +631,10 @@ S: Odd Fixes F: hw/arm/fsl-imx25.c F: hw/arm/imx25_pdk.c F: hw/misc/imx25_ccm.c +F: hw/watchdog/wdt_imx2.c F: include/hw/arm/fsl-imx25.h F: include/hw/misc/imx25_ccm.h +F: include/hw/watchdog/wdt_imx2.h i.MX31 (kzm) M: Peter Chubb diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 188419dc1e..adf401e827 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -374,6 +374,7 @@ config FSL_IMX6 select IMX_FEC select IMX_I2C select IMX_USBPHY + select WDT_IMX2 select SDHCI config ASPEED_SOC @@ -411,6 +412,7 @@ config FSL_IMX7 select IMX select IMX_FEC select IMX_I2C + select WDT_IMX2 select PCI_EXPRESS_DESIGNWARE select SDHCI select UNIMP @@ -424,6 +426,7 @@ config FSL_IMX6UL select IMX select IMX_FEC select IMX_I2C + select WDT_IMX2 select SDHCI select UNIMP diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 68aae2eabb..b25181b711 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -44,7 +44,6 @@ common-obj-$(CONFIG_IMX) += imx6_ccm.o common-obj-$(CONFIG_IMX) += imx6ul_ccm.o obj-$(CONFIG_IMX) += imx6_src.o common-obj-$(CONFIG_IMX) += imx7_ccm.o -common-obj-$(CONFIG_IMX) += imx2_wdt.o common-obj-$(CONFIG_IMX) += imx7_snvs.o common-obj-$(CONFIG_IMX) += imx7_gpr.o common-obj-$(CONFIG_IMX) += imx_rngc.o diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig index 2118d897c9..293209b291 100644 --- a/hw/watchdog/Kconfig +++ b/hw/watchdog/Kconfig @@ -14,3 +14,6 @@ config WDT_IB700 config WDT_DIAG288 bool + +config WDT_IMX2 + bool diff --git a/hw/watchdog/Makefile.objs b/hw/watchdog/Makefile.objs index 3f536d1cad..631b711d86 100644 --- a/hw/watchdog/Makefile.objs +++ b/hw/watchdog/Makefile.objs @@ -4,3 +4,4 @@ common-obj-$(CONFIG_WDT_IB6300ESB) += wdt_i6300esb.o common-obj-$(CONFIG_WDT_IB700) += wdt_ib700.o common-obj-$(CONFIG_WDT_DIAG288) += wdt_diag288.o common-obj-$(CONFIG_ASPEED_SOC) += wdt_aspeed.o +common-obj-$(CONFIG_WDT_IMX2) += wdt_imx2.o diff --git a/hw/misc/imx2_wdt.c b/hw/watchdog/wdt_imx2.c similarity index 98% rename from hw/misc/imx2_wdt.c rename to hw/watchdog/wdt_imx2.c index 2aedfe803a..ad1ef02e9e 100644 --- a/hw/misc/imx2_wdt.c +++ b/hw/watchdog/wdt_imx2.c @@ -14,7 +14,7 @@ #include "qemu/module.h" #include "sysemu/watchdog.h" -#include "hw/misc/imx2_wdt.h" +#include "hw/watchdog/wdt_imx2.h" #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 973bcb72f7..1ebd751324 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -21,7 +21,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" -#include "hw/misc/imx2_wdt.h" +#include "hw/watchdog/wdt_imx2.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 1a0bab8daa..37c89cc5f9 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -24,7 +24,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" #include "hw/intc/imx_gpcv2.h" -#include "hw/misc/imx2_wdt.h" +#include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 706aef2e7e..3a0041c4c2 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -26,7 +26,7 @@ #include "hw/misc/imx7_snvs.h" #include "hw/misc/imx7_gpr.h" #include "hw/misc/imx6_src.h" -#include "hw/misc/imx2_wdt.h" +#include "hw/watchdog/wdt_imx2.h" #include "hw/gpio/imx_gpio.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" diff --git a/include/hw/misc/imx2_wdt.h b/include/hw/watchdog/wdt_imx2.h similarity index 100% rename from include/hw/misc/imx2_wdt.h rename to include/hw/watchdog/wdt_imx2.h From patchwork Sun May 17 16:21:29 2020 Content-Type: text/plain; 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Sun, 17 May 2020 09:21:44 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 2/8] hw/watchdog: Implement full i.MX watchdog support Date: Sun, 17 May 2020 09:21:29 -0700 Message-Id: <20200517162135.110364-3-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=groeck7@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Implement full support for the watchdog in i.MX systems. Pretimeout support is optional because the watchdog hardware on i.MX31 does not support pretimeouts. Signed-off-by: Guenter Roeck --- v3: Improve handling of write-once registers and bits Stop timers in reset function Use explicit policy for timers v2: Fixup of CONFIG_WDT_IMX -> CONFIG_WDT_IMX2 moved to patch 1/8 hw/watchdog/wdt_imx2.c | 237 +++++++++++++++++++++++++++++++-- include/hw/watchdog/wdt_imx2.h | 61 ++++++++- 2 files changed, 284 insertions(+), 14 deletions(-) diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c index ad1ef02e9e..855b51768a 100644 --- a/hw/watchdog/wdt_imx2.c +++ b/hw/watchdog/wdt_imx2.c @@ -13,24 +13,189 @@ #include "qemu/bitops.h" #include "qemu/module.h" #include "sysemu/watchdog.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" #include "hw/watchdog/wdt_imx2.h" -#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ -#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ +static void imx2_wdt_interrupt(void *opaque) +{ + IMX2WdtState *s = IMX2_WDT(opaque); + + s->wicr |= IMX2_WDT_WICR_WTIS; + qemu_set_irq(s->irq, 1); +} + +static void imx2_wdt_expired(void *opaque) +{ + IMX2WdtState *s = IMX2_WDT(opaque); + + s->wrsr = IMX2_WDT_WRSR_TOUT; + + /* Perform watchdog action if watchdog is enabled */ + if (s->wcr & IMX2_WDT_WCR_WDE) { + s->wrsr = IMX2_WDT_WRSR_TOUT; + watchdog_perform_action(); + } +} + +static void imx2_wdt_reset(DeviceState *dev) +{ + IMX2WdtState *s = IMX2_WDT(dev); + + ptimer_transaction_begin(s->timer); + ptimer_stop(s->timer); + ptimer_transaction_commit(s->timer); + + if (s->pretimeout_support) { + ptimer_transaction_begin(s->itimer); + ptimer_stop(s->itimer); + ptimer_transaction_commit(s->itimer); + } + + s->wicr_locked = false; + s->wcr_locked = false; + s->wcr_wde_locked = false; + + s->wcr = IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS; + s->wsr = 0; + s->wrsr &= ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW); + s->wicr = IMX2_WDT_WICR_WICT_DEF; + s->wmcr = IMX2_WDT_WMCR_PDE; +} -static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size) { + IMX2WdtState *s = IMX2_WDT(opaque); + + switch (addr) { + case IMX2_WDT_WCR: + return s->wcr; + case IMX2_WDT_WSR: + return s->wsr; + case IMX2_WDT_WRSR: + return s->wrsr; + case IMX2_WDT_WICR: + return s->wicr; + case IMX2_WDT_WMCR: + return s->wmcr; + } return 0; } +static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start) +{ + bool running = (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT); + bool enabled = s->wicr & IMX2_WDT_WICR_WIE; + + ptimer_transaction_begin(s->itimer); + if (start || !enabled) { + ptimer_stop(s->itimer); + } + if (running && enabled) { + int count = ptimer_get_count(s->timer); + int pretimeout = s->wicr & IMX2_WDT_WICR_WICT; + + /* + * Only (re-)start pretimeout timer if its counter value is larger + * than 0. Otherwise it will fire right away and we'll get an + * interrupt loop. + */ + if (count > pretimeout) { + ptimer_set_count(s->itimer, count - pretimeout); + if (start) { + ptimer_run(s->itimer, 1); + } + } + } + ptimer_transaction_commit(s->itimer); +} + +static void imx_wdt2_update_timer(IMX2WdtState *s, bool start) +{ + ptimer_transaction_begin(s->timer); + if (start) { + ptimer_stop(s->timer); + } + if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) { + int count = (s->wcr & IMX2_WDT_WCR_WT) >> 8; + + /* A value of 0 reflects one period (0.5s). */ + ptimer_set_count(s->timer, count + 1); + if (start) { + ptimer_run(s->timer, 1); + } + } + ptimer_transaction_commit(s->timer); + if (s->pretimeout_support) { + imx_wdt2_update_itimer(s, start); + } +} + static void imx2_wdt_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { - if (addr == IMX2_WDT_WCR && - (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) { - watchdog_perform_action(); + IMX2WdtState *s = IMX2_WDT(opaque); + + switch (addr) { + case IMX2_WDT_WCR: + if (s->wcr_locked) { + value &= ~IMX2_WDT_WCR_LOCK_MASK; + value |= (s->wicr & IMX2_WDT_WCR_LOCK_MASK); + } + s->wcr_locked = true; + if (s->wcr_wde_locked) { + value &= ~IMX2_WDT_WCR_WDE; + value |= (s->wicr & ~IMX2_WDT_WCR_WDE); + } else if (value & IMX2_WDT_WCR_WDE) { + s->wcr_wde_locked = true; + } + if (s->wcr_wdt_locked) { + value &= ~IMX2_WDT_WCR_WDT; + value |= (s->wicr & ~IMX2_WDT_WCR_WDT); + } else if (value & IMX2_WDT_WCR_WDT) { + s->wcr_wdt_locked = true; + } + + s->wcr = value; + if (!(value & IMX2_WDT_WCR_SRS)) { + s->wrsr = IMX2_WDT_WRSR_SFTW; + } + if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) || + (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) { + watchdog_perform_action(); + } + s->wcr |= IMX2_WDT_WCR_SRS; + imx_wdt2_update_timer(s, true); + break; + case IMX2_WDT_WSR: + if (s->wsr == IMX2_WDT_SEQ1 && value == IMX2_WDT_SEQ2) { + imx_wdt2_update_timer(s, false); + } + s->wsr = value; + break; + case IMX2_WDT_WRSR: + break; + case IMX2_WDT_WICR: + if (!s->pretimeout_support) { + return; + } + value &= IMX2_WDT_WICR_LOCK_MASK | IMX2_WDT_WICR_WTIS; + if (s->wicr_locked) { + value &= IMX2_WDT_WICR_WTIS; + value |= (s->wicr & IMX2_WDT_WICR_LOCK_MASK); + } + s->wicr = value | (s->wicr & IMX2_WDT_WICR_WTIS); + if (value & IMX2_WDT_WICR_WTIS) { + s->wicr &= ~IMX2_WDT_WICR_WTIS; + qemu_set_irq(s->irq, 0); + } + imx_wdt2_update_itimer(s, true); + s->wicr_locked = true; + break; + case IMX2_WDT_WMCR: + s->wmcr = value & IMX2_WDT_WMCR_PDE; + break; } } @@ -45,28 +210,76 @@ static const MemoryRegionOps imx2_wdt_ops = { * real device but in practice there is no reason for a guest * to access this device unaligned. */ - .min_access_size = 4, - .max_access_size = 4, + .min_access_size = 2, + .max_access_size = 2, .unaligned = false, }, }; +static const VMStateDescription vmstate_imx2_wdt = { + .name = "imx2.wdt", + .fields = (VMStateField[]) { + VMSTATE_PTIMER(timer, IMX2WdtState), + VMSTATE_PTIMER(itimer, IMX2WdtState), + VMSTATE_BOOL(wicr_locked, IMX2WdtState), + VMSTATE_BOOL(wcr_locked, IMX2WdtState), + VMSTATE_BOOL(wcr_wde_locked, IMX2WdtState), + VMSTATE_BOOL(wcr_wdt_locked, IMX2WdtState), + VMSTATE_UINT16(wcr, IMX2WdtState), + VMSTATE_UINT16(wsr, IMX2WdtState), + VMSTATE_UINT16(wrsr, IMX2WdtState), + VMSTATE_UINT16(wmcr, IMX2WdtState), + VMSTATE_UINT16(wicr, IMX2WdtState), + VMSTATE_END_OF_LIST() + } +}; + static void imx2_wdt_realize(DeviceState *dev, Error **errp) { IMX2WdtState *s = IMX2_WDT(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); memory_region_init_io(&s->mmio, OBJECT(dev), &imx2_wdt_ops, s, - TYPE_IMX2_WDT".mmio", - IMX2_WDT_REG_NUM * sizeof(uint16_t)); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + TYPE_IMX2_WDT, + IMX2_WDT_MMIO_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); + + s->timer = ptimer_init(imx2_wdt_expired, s, + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + ptimer_transaction_begin(s->timer); + ptimer_set_freq(s->timer, 2); + ptimer_set_limit(s->timer, 0xff, 1); + ptimer_transaction_commit(s->timer); + if (s->pretimeout_support) { + s->itimer = ptimer_init(imx2_wdt_interrupt, s, + PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN); + ptimer_transaction_begin(s->itimer); + ptimer_set_freq(s->itimer, 2); + ptimer_set_limit(s->itimer, 0xff, 1); + ptimer_transaction_commit(s->itimer); + } } +static Property imx2_wdt_properties[] = { + DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support, + false), +}; + static void imx2_wdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + device_class_set_props(dc, imx2_wdt_properties); dc->realize = imx2_wdt_realize; + dc->reset = imx2_wdt_reset; + dc->vmsd = &vmstate_imx2_wdt; + dc->desc = "i.MX watchdog timer"; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h index b91b002528..f9af6be4b6 100644 --- a/include/hw/watchdog/wdt_imx2.h +++ b/include/hw/watchdog/wdt_imx2.h @@ -12,22 +12,79 @@ #ifndef IMX2_WDT_H #define IMX2_WDT_H +#include "qemu/bitops.h" #include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/ptimer.h" #define TYPE_IMX2_WDT "imx2.wdt" #define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT) enum IMX2WdtRegisters { - IMX2_WDT_WCR = 0x0000, - IMX2_WDT_REG_NUM = 0x0008 / sizeof(uint16_t) + 1, + IMX2_WDT_WCR = 0x0000, /* Control Register */ + IMX2_WDT_WSR = 0x0002, /* Service Register */ + IMX2_WDT_WRSR = 0x0004, /* Reset Status Register */ + IMX2_WDT_WICR = 0x0006, /* Interrupt Control Register */ + IMX2_WDT_WMCR = 0x0008, /* Misc Register */ }; +#define IMX2_WDT_MMIO_SIZE 0x000a + +/* Control Register definitions */ +#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */ +#define IMX2_WDT_WCR_WDW BIT(7) /* WDOG Disable for Wait */ +#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */ +#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */ +#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */ +#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */ +#define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */ +#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */ + +#define IMX2_WDT_WCR_LOCK_MASK (IMX2_WDT_WCR_WDZST | IMX2_WDT_WCR_WDBG \ + | IMX2_WDT_WCR_WDW) + +/* Service Register definitions */ +#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */ +#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */ + +/* Reset Status Register definitions */ +#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */ +#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to software reset */ + +/* Interrupt Control Register definitions */ +#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */ +#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */ +#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */ +#define IMX2_WDT_WICR_WICT_DEF 0x04 /* Default interrupt timeout (2s) */ + +#define IMX2_WDT_WICR_LOCK_MASK (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT) + +/* Misc Control Register definitions */ +#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */ typedef struct IMX2WdtState { /* */ SysBusDevice parent_obj; + /*< public >*/ MemoryRegion mmio; + qemu_irq irq; + + struct ptimer_state *timer; + struct ptimer_state *itimer; + + bool pretimeout_support; + bool wicr_locked; + + uint16_t wcr; + uint16_t wsr; + uint16_t wrsr; + uint16_t wicr; + uint16_t wmcr; + + bool wcr_locked; /* affects WDZST, WDBG, and WDW */ + bool wcr_wde_locked; /* affects WDE */ + bool wcr_wdt_locked; /* affects WDT (never cleared) */ } IMX2WdtState; #endif /* IMX2_WDT_H */ From patchwork Sun May 17 16:21:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11554183 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DD681739 for ; Sun, 17 May 2020 16:22:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3E402070A for ; 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Sun, 17 May 2020 09:21:45 -0700 (PDT) Received: from localhost ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id q25sm6553653pfh.94.2020.05.17.09.21.45 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 17 May 2020 09:21:45 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 3/8] hw/arm/fsl-imx25: Wire up watchdog Date: Sun, 17 May 2020 09:21:30 -0700 Message-Id: <20200517162135.110364-4-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=groeck7@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" With this commit, the watchdog on imx25-pdk is fully operational, including pretimeout support. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck --- v3: No change v2: Select WDT_IMX2 explicitly Added Philippe's Reviewed-by: tag hw/arm/Kconfig | 1 + hw/arm/fsl-imx25.c | 10 ++++++++++ include/hw/arm/fsl-imx25.h | 5 +++++ 3 files changed, 16 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index adf401e827..54a49aeabd 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -358,6 +358,7 @@ config FSL_IMX25 select IMX select IMX_FEC select IMX_I2C + select WDT_IMX2 select DS1338 config FSL_IMX31 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 6f1a82ce3d..cdaa79c26b 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -87,6 +87,7 @@ static void fsl_imx25_init(Object *obj) TYPE_CHIPIDEA); } + sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT); } static void fsl_imx25_realize(DeviceState *dev, Error **errp) @@ -302,6 +303,15 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) usb_table[i].irq)); } + /* Watchdog */ + object_property_set_bool(OBJECT(&s->wdt), true, "pretimeout-support", + &error_abort); + object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX25_WDT_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt), 0, + qdev_get_gpio_in(DEVICE(&s->avic), + FSL_IMX25_WDT_IRQ)); + /* initialize 2 x 16 KB ROM */ memory_region_init_rom(&s->rom[0], OBJECT(dev), "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err); diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h index 5e196bbf05..9e228dacea 100644 --- a/include/hw/arm/fsl-imx25.h +++ b/include/hw/arm/fsl-imx25.h @@ -29,6 +29,7 @@ #include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/usb/chipidea.h" +#include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" #include "target/arm/cpu.h" @@ -60,6 +61,7 @@ typedef struct FslIMX25State { IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS]; SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS]; ChipideaState usb[FSL_IMX25_NUM_USBS]; + IMX2WdtState wdt; MemoryRegion rom[2]; MemoryRegion iram; MemoryRegion iram_alias; @@ -229,6 +231,8 @@ typedef struct FslIMX25State { #define FSL_IMX25_GPIO1_SIZE 0x4000 #define FSL_IMX25_GPIO2_ADDR 0x53FD0000 #define FSL_IMX25_GPIO2_SIZE 0x4000 +#define FSL_IMX25_WDT_ADDR 0x53FDC000 +#define FSL_IMX25_WDT_SIZE 0x4000 #define FSL_IMX25_USB1_ADDR 0x53FF4000 #define FSL_IMX25_USB1_SIZE 0x0200 #define FSL_IMX25_USB2_ADDR 0x53FF4400 @@ -268,5 +272,6 @@ typedef struct FslIMX25State { #define FSL_IMX25_ESDHC2_IRQ 8 #define FSL_IMX25_USB1_IRQ 37 #define FSL_IMX25_USB2_IRQ 35 +#define FSL_IMX25_WDT_IRQ 55 #endif /* FSL_IMX25_H */ From patchwork Sun May 17 16:21:31 2020 Content-Type: text/plain; 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Sun, 17 May 2020 09:21:46 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 4/8] hw/arm/fsl-imx31: Wire up watchdog Date: Sun, 17 May 2020 09:21:31 -0700 Message-Id: <20200517162135.110364-5-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=groeck7@gmail.com; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" With this patch, the watchdog on i.MX31 emulations is fully operational. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck --- v3: No change v2: Select WDT_IMX2 explicitly Added Philippe's Reviewed-by: tag hw/arm/Kconfig | 1 + hw/arm/fsl-imx31.c | 6 ++++++ include/hw/arm/fsl-imx31.h | 4 ++++ 3 files changed, 11 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 54a49aeabd..9c77f4cbb4 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -366,6 +366,7 @@ config FSL_IMX31 select SERIAL select IMX select IMX_I2C + select WDT_IMX2 select LAN9118 config FSL_IMX6 diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 8472d2e911..1e7959863d 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -63,6 +63,8 @@ static void fsl_imx31_init(Object *obj) sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); } + + sysbus_init_child_obj(obj, "wdt", &s->wdt, sizeof(s->wdt), TYPE_IMX2_WDT); } static void fsl_imx31_realize(DeviceState *dev, Error **errp) @@ -205,6 +207,10 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) gpio_table[i].irq)); } + /* Watchdog */ + object_property_set_bool(OBJECT(&s->wdt), true, "realized", &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, FSL_IMX31_WDT_ADDR); + /* On a real system, the first 16k is a `secure boot rom' */ memory_region_init_rom(&s->secure_rom, OBJECT(dev), "imx31.secure_rom", FSL_IMX31_SECURE_ROM_SIZE, &err); diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h index ac5ca9826a..dd8561b309 100644 --- a/include/hw/arm/fsl-imx31.h +++ b/include/hw/arm/fsl-imx31.h @@ -25,6 +25,7 @@ #include "hw/timer/imx_epit.h" #include "hw/i2c/imx_i2c.h" #include "hw/gpio/imx_gpio.h" +#include "hw/watchdog/wdt_imx2.h" #include "exec/memory.h" #include "target/arm/cpu.h" @@ -49,6 +50,7 @@ typedef struct FslIMX31State { IMXEPITState epit[FSL_IMX31_NUM_EPITS]; IMXI2CState i2c[FSL_IMX31_NUM_I2CS]; IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS]; + IMX2WdtState wdt; MemoryRegion secure_rom; MemoryRegion rom; MemoryRegion iram; @@ -87,6 +89,8 @@ typedef struct FslIMX31State { #define FSL_IMX31_GPIO1_SIZE 0x4000 #define FSL_IMX31_GPIO2_ADDR 0x53FD0000 #define FSL_IMX31_GPIO2_SIZE 0x4000 +#define FSL_IMX31_WDT_ADDR 0x53FDC000 +#define FSL_IMX31_WDT_SIZE 0x4000 #define FSL_IMX31_AVIC_ADDR 0x68000000 #define FSL_IMX31_AVIC_SIZE 0x100 #define FSL_IMX31_SDRAM0_ADDR 0x80000000 From patchwork Sun May 17 16:21:32 2020 Content-Type: text/plain; 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Sun, 17 May 2020 09:21:48 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 5/8] hw/arm/fsl-imx6: Connect watchdog interrupts Date: Sun, 17 May 2020 09:21:32 -0700 Message-Id: <20200517162135.110364-6-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=groeck7@gmail.com; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" With this patch applied, the watchdog in the sabrelite emulation is fully operational, including pretimeout support. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck --- v3: Added Philippe's Reviewed-by: tag v2: No change hw/arm/fsl-imx6.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 13f1bf23a6..f58c85aa8c 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -433,11 +433,20 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) FSL_IMX6_WDOG1_ADDR, FSL_IMX6_WDOG2_ADDR, }; + static const int FSL_IMX6_WDOGn_IRQ[FSL_IMX6_NUM_WDTS] = { + FSL_IMX6_WDOG1_IRQ, + FSL_IMX6_WDOG2_IRQ, + }; + object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", + &error_abort); object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a9mpcore), + FSL_IMX6_WDOGn_IRQ[i])); } /* ROM memory */ From patchwork Sun May 17 16:21:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11554195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77E4B739 for ; Sun, 17 May 2020 16:25:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D89620643 for ; Sun, 17 May 2020 16:25:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JvsdHi6I" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D89620643 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:39944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jaM6N-0004JG-GV for patchwork-qemu-devel@patchwork.kernel.org; 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Sun, 17 May 2020 09:21:49 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 6/8] hw/arm/fsl-imx6ul: Connect watchdog interrupts Date: Sun, 17 May 2020 09:21:33 -0700 Message-Id: <20200517162135.110364-7-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=groeck7@gmail.com; helo=mail-pl1-x642.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" With this commit, the watchdog on mcimx6ul-evk is fully operational, including pretimeout support. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck --- v3: Added Philippe's Reviewed-by: tag v2: No change hw/arm/fsl-imx6ul.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 56dfd7cecc..3ecb212da6 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -531,12 +531,22 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) FSL_IMX6UL_WDOG2_ADDR, FSL_IMX6UL_WDOG3_ADDR, }; + static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { + FSL_IMX6UL_WDOG1_IRQ, + FSL_IMX6UL_WDOG2_IRQ, + FSL_IMX6UL_WDOG3_IRQ, + }; + object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", + &error_abort); object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6UL_WDOGn_ADDR[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX6UL_WDOGn_IRQ[i])); } /* From patchwork Sun May 17 16:21:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 11554187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6FAEE739 for ; Sun, 17 May 2020 16:22:39 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 471A82070A for ; Sun, 17 May 2020 16:22:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="t1iI/dXh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 471A82070A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:56606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jaM3i-0007qz-EH for patchwork-qemu-devel@patchwork.kernel.org; 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Sun, 17 May 2020 09:21:50 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 7/8] hw/arm/fsl-imx7: Instantiate various unimplemented devices Date: Sun, 17 May 2020 09:21:34 -0700 Message-Id: <20200517162135.110364-8-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=groeck7@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Instantiating PWM, CAN, CAAM, and OCOTP devices is necessary to avoid crashes when booting mainline Linux. Reviewed-by: Peter Maydell Signed-off-by: Guenter Roeck --- v3: Added Peter's Reviewed-by: tag v2: "octop" -> "ocotp" hw/arm/fsl-imx7.c | 24 ++++++++++++++++++++++++ include/hw/arm/fsl-imx7.h | 16 ++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 119b281a50..d6cf7c48ce 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -459,6 +459,30 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) */ create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE); + /* + * CAAM + */ + create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); + + /* + * PWM + */ + create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); + create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); + create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); + create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); + + /* + * CAN + */ + create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); + create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); + + /* + * OCOTP + */ + create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, + FSL_IMX7_OCOTP_SIZE); object_property_set_bool(OBJECT(&s->gpr), true, "realized", &error_abort); diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 3a0041c4c2..47826da2b7 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -113,6 +113,9 @@ enum FslIMX7MemoryMap { FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, FSL_IMX7_IOMUXCn_SIZE = 0x1000, + FSL_IMX7_OCOTP_ADDR = 0x30350000, + FSL_IMX7_OCOTP_SIZE = 0x10000, + FSL_IMX7_ANALOG_ADDR = 0x30360000, FSL_IMX7_SNVS_ADDR = 0x30370000, FSL_IMX7_CCM_ADDR = 0x30380000, @@ -124,11 +127,24 @@ enum FslIMX7MemoryMap { FSL_IMX7_ADC2_ADDR = 0x30620000, FSL_IMX7_ADCn_SIZE = 0x1000, + FSL_IMX7_PWM1_ADDR = 0x30660000, + FSL_IMX7_PWM2_ADDR = 0x30670000, + FSL_IMX7_PWM3_ADDR = 0x30680000, + FSL_IMX7_PWM4_ADDR = 0x30690000, + FSL_IMX7_PWMn_SIZE = 0x10000, + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, FSL_IMX7_PCIE_PHY_SIZE = 0x10000, FSL_IMX7_GPC_ADDR = 0x303A0000, + FSL_IMX7_CAAM_ADDR = 0x30900000, + FSL_IMX7_CAAM_SIZE = 0x40000, + + FSL_IMX7_CAN1_ADDR = 0x30A00000, + FSL_IMX7_CAN2_ADDR = 0x30A10000, + FSL_IMX7_CANn_SIZE = 0x10000, + FSL_IMX7_I2C1_ADDR = 0x30A20000, FSL_IMX7_I2C2_ADDR = 0x30A30000, FSL_IMX7_I2C3_ADDR = 0x30A40000, From patchwork Sun May 17 16:21:35 2020 Content-Type: text/plain; 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Sun, 17 May 2020 09:21:52 -0700 (PDT) From: Guenter Roeck To: Peter Maydell Subject: [PATCH v3 8/8] hw/arm/fsl-imx7: Connect watchdog interrupts Date: Sun, 17 May 2020 09:21:35 -0700 Message-Id: <20200517162135.110364-9-linux@roeck-us.net> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200517162135.110364-1-linux@roeck-us.net> References: <20200517162135.110364-1-linux@roeck-us.net> Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=groeck7@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , Peter Chubb , qemu-devel@nongnu.org, Guenter Roeck , Jean-Christophe Dubois Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" i.MX7 supports watchdog pretimeout interupts. With this commit, the watchdog in mcimx7d-sabre is fully operational, including pretimeout support. Reviewed-by: Peter Maydell Signed-off-by: Guenter Roeck --- v3: Added Peter's Reviewed-by: tag v2: No change hw/arm/fsl-imx7.c | 11 +++++++++++ include/hw/arm/fsl-imx7.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index d6cf7c48ce..89c3b64c06 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -447,11 +447,22 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) FSL_IMX7_WDOG3_ADDR, FSL_IMX7_WDOG4_ADDR, }; + static const int FSL_IMX7_WDOGn_IRQ[FSL_IMX7_NUM_WDTS] = { + FSL_IMX7_WDOG1_IRQ, + FSL_IMX7_WDOG2_IRQ, + FSL_IMX7_WDOG3_IRQ, + FSL_IMX7_WDOG4_IRQ, + }; + object_property_set_bool(OBJECT(&s->wdt[i]), true, "pretimeout-support", + &error_abort); object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(DEVICE(&s->a7mpcore), + FSL_IMX7_WDOGn_IRQ[i])); } /* diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 47826da2b7..da977f9ffb 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -228,6 +228,11 @@ enum FslIMX7IRQs { FSL_IMX7_USB2_IRQ = 42, FSL_IMX7_USB3_IRQ = 40, + FSL_IMX7_WDOG1_IRQ = 78, + FSL_IMX7_WDOG2_IRQ = 79, + FSL_IMX7_WDOG3_IRQ = 10, + FSL_IMX7_WDOG4_IRQ = 109, + FSL_IMX7_PCI_INTA_IRQ = 125, FSL_IMX7_PCI_INTB_IRQ = 124, FSL_IMX7_PCI_INTC_IRQ = 123,