From patchwork Wed Oct 10 23:50:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 10635455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BD8A14DB for ; Wed, 10 Oct 2018 23:54:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C5CB291F4 for ; Wed, 10 Oct 2018 23:54:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5031D2A56C; Wed, 10 Oct 2018 23:54:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DCFEF291F4 for ; Wed, 10 Oct 2018 23:54:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D6566E365; Wed, 10 Oct 2018 23:54:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6E536E363; Wed, 10 Oct 2018 23:54:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2018 16:54:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,366,1534834800"; d="scan'208";a="77086405" Received: from mdroper-desk.fm.intel.com ([10.105.128.10]) by fmsmga007.fm.intel.com with ESMTP; 10 Oct 2018 16:51:46 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Subject: [PATCH 1/2] drm: Add CRTC background color property Date: Wed, 10 Oct 2018 16:50:50 -0700 Message-Id: <20181010235051.16693-2-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181010235051.16693-1-matthew.d.roper@intel.com> References: <20181010235051.16693-1-matthew.d.roper@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei.c.li@intel.com, dri-devel@lists.freedesktop.org, harish.krupo.kps@intel.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some display controllers can be programmed to present non-black colors for pixels not covered by any plane (or pixels covered by the transparent regions of higher planes). Compositors that want a UI with a solid color background can potentially save memory bandwidth by setting the CRTC background property and using smaller planes to display the rest of the content. To avoid confusion between different ways of encoding RGB data, we define a standard 64-bit format that should be used for this property's value. Helper functions and macros are provided to generate and dissect values in this standard format with varying component precision values. Cc: dri-devel@lists.freedesktop.org Cc: wei.c.li@intel.com Cc: harish.krupo.kps@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/drm_atomic_state_helper.c | 1 + drivers/gpu/drm/drm_atomic_uapi.c | 5 +++++ drivers/gpu/drm/drm_mode_config.c | 6 ++++++ include/drm/drm_crtc.h | 17 +++++++++++++++++ include/drm/drm_mode_config.h | 5 +++++ include/uapi/drm/drm_mode.h | 26 ++++++++++++++++++++++++++ 6 files changed, 60 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c index 3ba996069d69..2f8c55668089 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -101,6 +101,7 @@ void __drm_atomic_helper_crtc_duplicate_state(struct drm_crtc *crtc, state->planes_changed = false; state->connectors_changed = false; state->color_mgmt_changed = false; + state->bgcolor_changed = false; state->zpos_changed = false; state->commit = NULL; state->event = NULL; diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index d5b7f315098c..399f0ead5370 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -467,6 +467,9 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, return -EFAULT; set_out_fence_for_crtc(state->state, crtc, fence_ptr); + } else if (property == config->bgcolor_property) { + state->background_color = val; + state->bgcolor_changed = true; } else if (crtc->funcs->atomic_set_property) { return crtc->funcs->atomic_set_property(crtc, state, property, val); } else { @@ -499,6 +502,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; else if (property == config->prop_out_fence_ptr) *val = 0; + else if (property == config->bgcolor_property) + *val = state->background_color; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else diff --git a/drivers/gpu/drm/drm_mode_config.c b/drivers/gpu/drm/drm_mode_config.c index ee80788f2c40..75e376755176 100644 --- a/drivers/gpu/drm/drm_mode_config.c +++ b/drivers/gpu/drm/drm_mode_config.c @@ -352,6 +352,12 @@ static int drm_mode_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.modifiers_property = prop; + prop = drm_property_create_range(dev, 0, "BACKGROUND_COLOR", + 0, GENMASK_ULL(63, 0)); + if (!prop) + return -ENOMEM; + dev->mode_config.bgcolor_property = prop; + return 0; } diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index b21437bc95bf..ddfdad9ccecb 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -168,6 +168,11 @@ struct drm_crtc_state { * drivers to steer the atomic commit control flow. */ bool color_mgmt_changed : 1; + /** + * @bgcolor_changed: Background color value has changed. Used by + * drivers to steer the atomic commit control flow. + */ + bool bgcolor_changed : 1; /** * @no_vblank: @@ -274,6 +279,18 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; + /** + * @background_color: + * + * RGB value representing the pipe's background color. The background + * color (aka "canvas color") of a pipe is the color that will be used + * for pixels not covered by a plane, or covered by transparent pixels + * of a plane. The value here should be built via drm_rgba(); + * individual color components can be extracted with desired precision + * via the DRM_RGBA_*() macros. + */ + u64 background_color; + /** * @target_vblank: * diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 928e4172a0bb..c3f57a9e5b31 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -807,6 +807,11 @@ struct drm_mode_config { */ struct drm_property *writeback_out_fence_ptr_property; + /** + * @bgcolor_property: RGBA background color for CRTC. + */ + struct drm_property *bgcolor_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow; bool quirk_addfb_prefer_xbgr_30bpp; diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index d3e0fe31efc5..66e2e2c2630e 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -888,6 +888,32 @@ struct drm_mode_revoke_lease { __u32 lessee_id; }; +/* + * Put RGBA values into a standard 64-bit representation that can be used + * for ioctl parameters, inter-driver commmunication, etc. If the component + * values being provided contain less than 16 bits of precision, they'll + * be shifted into the most significant bits. + */ +static inline __u64 +drm_rgba(__u8 bpc, __u16 red, __u16 green, __u16 blue, __u16 alpha) +{ + int msb_shift = 16 - bpc; + + return (__u64)alpha << msb_shift << 48 | + (__u64)blue << msb_shift << 32 | + (__u64)green << msb_shift << 16 | + (__u64)red << msb_shift; +} + +/* + * Extract the specified number of bits of a specific color component from a + * standard 64-bit RGBA value. + */ +#define DRM_RGBA_RED(c, numbits) (__u16)((c & 0xFFFFull) >> (16-numbits)) +#define DRM_RGBA_GREEN(c, numbits) (__u16)((c & 0xFFFFull<<16) >> (32-numbits)) +#define DRM_RGBA_BLUE(c, numbits) (__u16)((c & 0xFFFFull<<32) >> (48-numbits)) +#define DRM_RGBA_ALPHA(c, numbits) (__u16)((c & 0xFFFFull<<48) >> (64-numbits)) + #if defined(__cplusplus) } #endif From patchwork Wed Oct 10 23:50:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 10635459 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7105114DB for ; Wed, 10 Oct 2018 23:54:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5348A291F4 for ; Wed, 10 Oct 2018 23:54:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4724D2A56C; Wed, 10 Oct 2018 23:54:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E4FEB291F4 for ; Wed, 10 Oct 2018 23:54:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8E046E367; Wed, 10 Oct 2018 23:54:32 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 16CA36E365; Wed, 10 Oct 2018 23:54:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Oct 2018 16:54:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,366,1534834800"; d="scan'208";a="77086409" Received: from mdroper-desk.fm.intel.com ([10.105.128.10]) by fmsmga007.fm.intel.com with ESMTP; 10 Oct 2018 16:51:54 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Subject: [PATCH 2/2] drm/i915/gen9+: Add support for pipe background color Date: Wed, 10 Oct 2018 16:50:51 -0700 Message-Id: <20181010235051.16693-3-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20181010235051.16693-1-matthew.d.roper@intel.com> References: <20181010235051.16693-1-matthew.d.roper@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei.c.li@intel.com, dri-devel@lists.freedesktop.org, harish.krupo.kps@intel.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors. Cc: dri-devel@lists.freedesktop.org Cc: wei.c.li@intel.com Cc: harish.krupo.kps@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4565eda29c87..cc423f7f3e62 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void *unused) intel_plane_info(m, crtc); } + if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { + uint64_t background = pipe_config->base.background_color; + + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", + DRM_RGBA_RED(background, 10), + DRM_RGBA_GREEN(background, 10), + DRM_RGBA_BLUE(background, 10)); + } + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", yesno(!crtc->cpu_fifo_underrun_disabled), yesno(!crtc->pch_fifo_underrun_disabled)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 20785417953d..988183870f6e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5661,6 +5661,12 @@ enum { #define PIPEMISC_DITHER_TYPE_SP (0 << 2) #define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A) +/* Skylake+ pipe bottom (background) color */ +#define _PIPE_BOTTOM_COLOR_A 0x70034 +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31) +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30) +#define PIPE_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _PIPE_BOTTOM_COLOR_A) + #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028) #define PIPEB_LINE_COMPARE_INT_EN (1 << 29) #define PIPEB_HLINE_INT_EN (1 << 28) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a145efba9157..2ee402a98e70 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3853,6 +3853,28 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } +static void skl_update_background_color(const struct intel_crtc_state *cstate) +{ + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + uint64_t propval = cstate->base.background_color; + uint32_t hwval; + + /* Hardware is programmed with 10 bits of precision */ + hwval = DRM_RGBA_RED(propval, 10) << 20 + | DRM_RGBA_GREEN(propval, 10) << 10 + | DRM_RGBA_BLUE(propval, 10); + + /* + * Set CSC and gamma for bottom color to ensure background pixels + * receive the same color transformations as plane content. + */ + hwval |= PIPE_BOTTOM_CSC_ENABLE; + hwval |= PIPE_BOTTOM_GAMMA_ENABLE; + + I915_WRITE_FW(PIPE_BOTTOM_COLOR(crtc->pipe), hwval); +} + static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -3887,6 +3909,9 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta else if (old_crtc_state->pch_pfit.enabled) ironlake_pfit_disable(old_crtc_state); } + + if (new_crtc_state->base.bgcolor_changed) + skl_update_background_color(new_crtc_state); } static void intel_fdi_normal_train(struct intel_crtc *crtc) @@ -10791,6 +10816,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, crtc_state->planes_changed = true; } + if (crtc_state->bgcolor_changed) + pipe_config->update_pipe = true; + ret = 0; if (dev_priv->display.compute_pipe_wm) { ret = dev_priv->display.compute_pipe_wm(pipe_config); @@ -13831,6 +13859,7 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) { + struct drm_mode_config *mode_config = &dev_priv->drm.mode_config; struct intel_crtc *intel_crtc; struct intel_crtc_state *crtc_state = NULL; struct intel_plane *primary = NULL; @@ -13905,6 +13934,11 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); + if (INTEL_GEN(dev_priv) >= 9) + drm_object_attach_property(&intel_crtc->base.base, + mode_config->bgcolor_property, + drm_rgba(16, 0, 0, 0, 0xffff)); + return 0; fail: