From patchwork Tue May 26 14:02:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6F21E14B7 for ; Tue, 26 May 2020 14:03:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61620208DB for ; Tue, 26 May 2020 14:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731858AbgEZODC (ORCPT ); Tue, 26 May 2020 10:03:02 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:57906 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731846AbgEZODB (ORCPT ); Tue, 26 May 2020 10:03:01 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 9E531803086D; Tue, 26 May 2020 14:02:58 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eLOR7vdUy706; Tue, 26 May 2020 17:02:57 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Paul Burton , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH 1/6] dt-bindings: power: Convert mti,mips-cpc to DT schema Date: Tue, 26 May 2020 17:02:38 +0300 Message-ID: <20200526140243.21946-2-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog prev: - Reword the changelog summary - use shorter version. - Lowercase the example hex'es. --- .../bindings/power/mti,mips-cpc.txt | 8 ----- .../bindings/power/mti,mips-cpc.yaml | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.txt create mode 100644 Documentation/devicetree/bindings/power/mti,mips-cpc.yaml diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt b/Documentation/devicetree/bindings/power/mti,mips-cpc.txt deleted file mode 100644 index c6b82511ae8a..000000000000 --- a/Documentation/devicetree/bindings/power/mti,mips-cpc.txt +++ /dev/null @@ -1,8 +0,0 @@ -Binding for MIPS Cluster Power Controller (CPC). - -This binding allows a system to specify where the CPC registers are -located. - -Required properties: -compatible : Should be "mti,mips-cpc". -regs: Should describe the address & size of the CPC register region. diff --git a/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml new file mode 100644 index 000000000000..9cd92a57130c --- /dev/null +++ b/Documentation/devicetree/bindings/power/mti,mips-cpc.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Cluster Power Controller + +description: | + Defines a location of the MIPS Cluster Power Controller registers. + +maintainers: + - Paul Burton + +properties: + compatible: + const: mti,mips-cpc + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CPC registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cpc@1bde0000 { + compatible = "mti,mips-cpc"; + reg = <0 0x1bde0000 0 0x8000>; + }; +... From patchwork Tue May 26 14:02:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570605 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97E57159A for ; Tue, 26 May 2020 14:03:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 845AC208C7 for ; Tue, 26 May 2020 14:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731923AbgEZODE (ORCPT ); Tue, 26 May 2020 10:03:04 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:57930 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731854AbgEZODE (ORCPT ); Tue, 26 May 2020 10:03:04 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 2A51D803086E; Tue, 26 May 2020 14:03:00 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PEgJ92I8j3nR; Tue, 26 May 2020 17:02:59 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Jason Cooper , Marc Zyngier , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH 2/6] dt-bindings: interrupt-controller: Convert mti,gic to DT schema Date: Tue, 26 May 2020 17:02:39 +0300 Message-ID: <20200526140243.21946-3-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- I don't really know who is the corresponding driver maintainer, so I added Paul to the maintainers property since he used to be looking for the MIPS arch and Thomas looking after it now. Any idea what email should be specified there instead? Changelog prev: - Since timer sub-node has no unit-address, the node shouldn't be named with one. So alter the MIPS GIC bindings to have a pure "timer" sub-node. - Discard allOf: [ $ref: /schemas/interrupt-controller.yaml# ]. - Since it's a conversion patch use GPL-2.0-only SPDX header. --- .../interrupt-controller/mips-gic.txt | 67 -------- .../interrupt-controller/mti,gic.yaml | 148 ++++++++++++++++++ 2 files changed, 148 insertions(+), 67 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt deleted file mode 100644 index 173595305e26..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt +++ /dev/null @@ -1,67 +0,0 @@ -MIPS Global Interrupt Controller (GIC) - -The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. -It also supports local (per-processor) interrupts and software-generated -interrupts which can be used as IPIs. The GIC also includes a free-running -global timer, per-CPU count/compare timers, and a watchdog. - -Required properties: -- compatible : Should be "mti,gic". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt specifier. Should be 3. - - The first cell is the type of interrupt, local or shared. - See . - - The second cell is the GIC interrupt number. - - The third cell encodes the interrupt flags. - See for a list of valid - flags. - -Optional properties: -- reg : Base address and length of the GIC registers. If not present, - the base address reported by the hardware GCR_GIC_BASE will be used. -- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors - to which the GIC may not route interrupts. Valid values are 2 - 7. - This property is ignored if the CPU is started in EIC mode. -- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are - reserved for IPIs. - It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size - of the reserved range. - If not specified, the driver will allocate the last 2 * number of VPEs in the - system. - -Required properties for timer sub-node: -- compatible : Should be "mti,gic-timer". -- interrupts : Interrupt for the GIC local timer. - -Optional properties for timer sub-node: -- clocks : GIC timer operating clock. -- clock-frequency : Clock frequency at which the GIC timers operate. - -Note that one of clocks or clock-frequency must be specified. - -Example: - - gic: interrupt-controller@1bdc0000 { - compatible = "mti,gic"; - reg = <0x1bdc0000 0x20000>; - - interrupt-controller; - #interrupt-cells = <3>; - - mti,reserved-cpu-vectors = <7>; - mti,reserved-ipi-vectors = <40 8>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clock-frequency = <50000000>; - }; - }; - - uart@18101400 { - ... - interrupt-parent = <&gic>; - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml new file mode 100644 index 000000000000..9f0eb3addac4 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Global Interrupt Controller + +maintainers: + - Paul Burton + - Thomas Bogendoerfer + +description: | + The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. + It also supports local (per-processor) interrupts and software-generated + interrupts which can be used as IPIs. The GIC also includes a free-running + global timer, per-CPU count/compare timers, and a watchdog. + +properties: + compatible: + const: mti,gic + + "#interrupt-cells": + const: 3 + description: | + The 1st cell is the type of interrupt: local or shared defined in the + file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the + GIC interrupt number. The 3d cell encodes the interrupt flags setting up + the IRQ trigger modes, which are defined in the file + 'dt-bindings/interrupt-controller/irq.h'. + + reg: + description: | + Base address and length of the GIC registers space. If not present, + the base address reported by the hardware GCR_GIC_BASE will be used. + maxItems: 1 + + interrupt-controller: true + + mti,reserved-cpu-vectors: + description: | + Specifies the list of CPU interrupt vectors to which the GIC may not + route interrupts. This property is ignored if the CPU is started in EIC + mode. + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - minItems: 1 + maxItems: 6 + uniqueItems: true + items: + minimum: 2 + maximum: 7 + + mti,reserved-ipi-vectors: + description: | + Specifies the range of GIC interrupts that are reserved for IPIs. + It accepts two values: the 1st is the starting interrupt and the 2nd is + the size of the reserved range. If not specified, the driver will + allocate the last (2 * number of VPEs in the system). + allOf: + - $ref: /schemas/types.yaml#definitions/uint32-array + - items: + - minimum: 0 + maximum: 254 + - minimum: 2 + maximum: 254 + + timer: + type: object + description: | + MIPS GIC includes a free-running global timer, per-CPU count/compare + timers, and a watchdog. Currently only the GIC Timer is supported. + properties: + compatible: + const: mti,gic-timer + + interrupts: + description: | + Interrupt for the GIC local timer, so normally it's suppose to be of + format. + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: true + + required: + - compatible + - interrupts + + oneOf: + - required: + - clocks + - required: + - clock-frequency + + additionalProperties: false + +unevaluatedProperties: false + +required: + - compatible + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + mti,reserved-cpu-vectors = <7>; + mti,reserved-ipi-vectors = <40 8>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clock-frequency = <50000000>; + }; + }; + - | + #include + #include + + interrupt-controller@1bdc0000 { + compatible = "mti,gic"; + reg = <0x1bdc0000 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&cpu_pll>; + }; + }; + - | + interrupt-controller { + compatible = "mti,gic"; + interrupt-controller; + #interrupt-cells = <3>; + }; +... From patchwork Tue May 26 14:02:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570603 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6374D739 for ; Tue, 26 May 2020 14:03:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 54A8820C09 for ; Tue, 26 May 2020 14:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731920AbgEZODE (ORCPT ); Tue, 26 May 2020 10:03:04 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:57966 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731856AbgEZODD (ORCPT ); Tue, 26 May 2020 10:03:03 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id A91568030870; Tue, 26 May 2020 14:03:00 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pDQHqZJiOjRx; Tue, 26 May 2020 17:02:59 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Rob Herring CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , , Rob Herring Subject: [PATCH 3/6] dt-bindings: bus: Add MIPS CDMM controller Date: Tue, 26 May 2020 17:02:40 +0300 Message-ID: <20200526140243.21946-4-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin Reviewed-by: Rob Herring --- Changelog prev: - Lowercase the example hex'es. --- .../bindings/bus/mti,mips-cdmm.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml diff --git a/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml new file mode 100644 index 000000000000..b3ba98515cbe --- /dev/null +++ b/Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Common Device Memory Map + +description: | + Defines a location of the MIPS Common Device Memory Map registers. + +maintainers: + - James Hogan + +properties: + compatible: + const: mti,mips-cdmm + + reg: + description: | + Base address and size of an unoccupied memory region, which will be + used to map the MIPS CDMM registers block. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + cdmm@1bde8000 { + compatible = "mti,mips-cdmm"; + reg = <0 0x1bde8000 0 0x8000>; + }; +... From patchwork Tue May 26 14:02:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570611 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2B02914B7 for ; Tue, 26 May 2020 14:03:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1D873208B6 for ; Tue, 26 May 2020 14:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731993AbgEZODT (ORCPT ); Tue, 26 May 2020 10:03:19 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:57990 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731857AbgEZODD (ORCPT ); Tue, 26 May 2020 10:03:03 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id EC7298030869; Tue, 26 May 2020 14:03:00 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qzvqWvySs0VA; Tue, 26 May 2020 17:03:00 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman , Serge Semin CC: Serge Semin , Alexey Malahov , Paul Burton , Rob Herring , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , Subject: [PATCH 4/6] mips: cdmm: Add mti,mips-cdmm dtb node support Date: Tue, 26 May 2020 17:02:41 +0300 Message-ID: <20200526140243.21946-5-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Since having and mapping the CDMM block is platform specific, then instead of just returning a zero-address, lets make the default CDMM base address search method (mips_cdmm_phys_base()) to do something useful. For instance to find the address in a dedicated dtb-node in order to support of-based platforms by default. Signed-off-by: Serge Semin --- Changelog prev: - Use alphabetical order for the include pre-processor operator. --- drivers/bus/mips_cdmm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/bus/mips_cdmm.c b/drivers/bus/mips_cdmm.c index 1b14256376d2..9f7ed1fcd428 100644 --- a/drivers/bus/mips_cdmm.c +++ b/drivers/bus/mips_cdmm.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -337,9 +339,22 @@ static phys_addr_t mips_cdmm_cur_base(void) * Picking a suitable physical address at which to map the CDMM region is * platform specific, so this weak function can be overridden by platform * code to pick a suitable value if none is configured by the bootloader. + * By default this method tries to find a CDMM-specific node in the system + * dtb. Note that this won't work for early serial console. */ phys_addr_t __weak mips_cdmm_phys_base(void) { + struct device_node *np; + struct resource res; + int err; + + np = of_find_compatible_node(NULL, NULL, "mti,mips-cdmm"); + if (np) { + err = of_address_to_resource(np, 0, &res); + if (!err) + return res.start; + } + return 0; } From patchwork Tue May 26 14:02:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570607 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EF14739 for ; Tue, 26 May 2020 14:03:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 605562087D for ; Tue, 26 May 2020 14:03:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731934AbgEZODF (ORCPT ); Tue, 26 May 2020 10:03:05 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:58016 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731846AbgEZODE (ORCPT ); Tue, 26 May 2020 10:03:04 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 857098030875; Tue, 26 May 2020 14:03:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E62VF2Uq7rJr; Tue, 26 May 2020 17:03:01 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Rob Herring , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , Subject: [PATCH 5/6] bus: cdmm: Add MIPS R5 arch support Date: Tue, 26 May 2020 17:02:42 +0300 Message-ID: <20200526140243.21946-6-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being supported for that MIPS arch too. Signed-off-by: Serge Semin Reviewed-by: Thomas Bogendoerfer --- drivers/bus/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 6d4e4497b59b..971c07bc92d4 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -58,7 +58,7 @@ config IMX_WEIM config MIPS_CDMM bool "MIPS Common Device Memory Map (CDMM) Driver" - depends on CPU_MIPSR2 + depends on CPU_MIPSR2 || CPU_MIPSR5 help Driver needed for the MIPS Common Device Memory Map bus in MIPS cores. This bus is for per-CPU tightly coupled devices such as the From patchwork Tue May 26 14:02:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 11570609 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97300739 for ; Tue, 26 May 2020 14:03:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 840FE208DB for ; Tue, 26 May 2020 14:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731978AbgEZODP (ORCPT ); Tue, 26 May 2020 10:03:15 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:58024 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731887AbgEZODE (ORCPT ); Tue, 26 May 2020 10:03:04 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id 262E8803086C; Tue, 26 May 2020 14:03:02 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sv-Ah8IKs_Cd; Tue, 26 May 2020 17:03:01 +0300 (MSK) From: Serge Semin To: Thomas Bogendoerfer , Thomas Gleixner , Greg Kroah-Hartman CC: Serge Semin , Serge Semin , Alexey Malahov , Paul Burton , Rob Herring , Arnd Bergmann , Jason Cooper , Marc Zyngier , "Rafael J. Wysocki" , Daniel Lezcano , James Hogan , , , Subject: [PATCH 6/6] MAINTAINERS: Add maintainers for MIPS core drivers Date: Tue, 26 May 2020 17:02:43 +0300 Message-ID: <20200526140243.21946-7-Sergey.Semin@baikalelectronics.ru> In-Reply-To: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> References: <20200526140243.21946-1-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add myself as a maintainer of MIPS CPU and GIC IRQchip, MIPS GIC timer and MIPS CPS CPUidle drivers. Signed-off-by: Serge Semin --- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2926327e4976..f21e51c4a0d5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11278,6 +11278,16 @@ F: arch/mips/configs/generic/board-boston.config F: drivers/clk/imgtec/clk-boston.c F: include/dt-bindings/clock/boston-clock.h +MIPS CORE DRIVERS +M: Serge Semin +L: linux-mips@vger.kernel.org +S: Supported +F: drivers/bus/mips_cdmm.c +F: drivers/irqchip/irq-mips-cpu.c +F: drivers/irqchip/irq-mips-gic.c +F: drivers/clocksource/mips-gic-timer.c +F: drivers/cpuidle/cpuidle-cps.c + MIPS GENERIC PLATFORM M: Paul Burton L: linux-mips@vger.kernel.org