From patchwork Wed May 27 20:21:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11573895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 96491913 for ; Wed, 27 May 2020 20:22:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FBB920B80 for ; Wed, 27 May 2020 20:22:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="vT3U+cM4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728450AbgE0UWp (ORCPT ); Wed, 27 May 2020 16:22:45 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:42206 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728481AbgE0UWo (ORCPT ); Wed, 27 May 2020 16:22:44 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1590610964; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=Y8r0vejj7AAxjfIGnYZNa+fR6ffFzxlWascR8sqXLkM=; b=vT3U+cM4o1/a1wfJYup8w7GG87XIbXRTrUeLfmT+reGio9ael99SKp0LY777yhfv3Bl3BGAq rvgPnlgItlZotF1NWHA4qXiJiAm7XRZ0OlIRJYTDFNPy8nRP/WxS8PsYdRgOYtFU5em03bhx 872UOwqey5P9+wKIGU3qt+4fr+A= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 5ececc0137a454afcbe3f52f (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 27 May 2020 20:22:25 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 6CB29C433AF; Wed, 27 May 2020 20:22:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 52CBEC43395; Wed, 27 May 2020 20:22:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 52CBEC43395 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v5 1/5] cpufreq: blacklist SDM845 in cpufreq-dt-platdev Date: Thu, 28 May 2020 01:51:49 +0530 Message-Id: <20200527202153.11659-2-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200527202153.11659-1-sibis@codeaurora.org> References: <20200527202153.11659-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SDM845 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver. Reviewed-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Signed-off-by: Sibi Sankar --- v5: * Picked up R-b from Amit v4: * Updated commit message [Matthias] * Picked up R-b from Matthias drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index e8e20fef400b0..be85eb494a6b3 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -132,6 +132,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,apq8096", }, { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, + { .compatible = "qcom,sdm845", }, { .compatible = "st,stih407", }, { .compatible = "st,stih410", }, From patchwork Wed May 27 20:21:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11573893 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1FEBA14B7 for ; Wed, 27 May 2020 20:22:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 079A721475 for ; Wed, 27 May 2020 20:22:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="Wee5K58B" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728458AbgE0UWi (ORCPT ); Wed, 27 May 2020 16:22:38 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:42206 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728473AbgE0UWi (ORCPT ); Wed, 27 May 2020 16:22:38 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1590610957; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=asihdyvMpllnyYwbtDMtg5pmz3DDPo5UV3bMnDNkvAg=; b=Wee5K58BjGXoOInl419nV7DtgWmsf7zFcqENkPpHEn59g5ECSgk7wXfcUhmhxpCetBfqRdj4 jfATmwpXmfgtMinX+mbzKKaDvJuNpR2ZXAehVSJf+FYmPXpHifkdTtY27qouo2krhVHZgTDs IkS+C7TonQGWDxFsldeB9DPZosk= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 5ececc07c28b2cdd98fd3f7d (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 27 May 2020 20:22:31 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 394A5C43395; Wed, 27 May 2020 20:22:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 43EEFC43391; Wed, 27 May 2020 20:22:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 43EEFC43391 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v5 2/5] cpufreq: blacklist SC7180 in cpufreq-dt-platdev Date: Thu, 28 May 2020 01:51:50 +0530 Message-Id: <20200527202153.11659-3-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200527202153.11659-1-sibis@codeaurora.org> References: <20200527202153.11659-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add SC7180 to cpufreq-dt-platdev blacklist since the actual scaling is handled by the 'qcom-cpufreq-hw' driver. Reviewed-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Signed-off-by: Sibi Sankar --- v5: * Picked up R-b from Amit v4: * Updated commit message [Matthias] * Picked up R-b from Matthias drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index be85eb494a6b3..7d01df7bfa6cd 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -132,6 +132,7 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "qcom,apq8096", }, { .compatible = "qcom,msm8996", }, { .compatible = "qcom,qcs404", }, + { .compatible = "qcom,sc7180", }, { .compatible = "qcom,sdm845", }, { .compatible = "st,stih407", }, From patchwork Wed May 27 20:21:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11573903 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CCF1C913 for ; Wed, 27 May 2020 20:22:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B49DA20890 for ; Wed, 27 May 2020 20:22:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="pAphWKMw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728644AbgE0UWz (ORCPT ); Wed, 27 May 2020 16:22:55 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:42206 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728481AbgE0UWy (ORCPT ); Wed, 27 May 2020 16:22:54 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1590610974; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=kaXpJWySm8V8fWorli3+KZiQaHhCwHYGI4YHOvlKWA0=; b=pAphWKMwvjkVLNeKSnJ6cw4Ho4amA6caVTivVkIZgtwb7njssg3F3B7GCFR4Pl6xq4r0Isrq PL9XnvmwVVscoVndKvMYe0tPltCJyDSg3nvaEkiqHI5WxTSnVqajb0Rg+hvRDM3YkazKx3VC hqCuGJvpRQb33KXH7exxsX2DxUU= X-Mailgun-Sending-Ip: 104.130.122.27 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n04.prod.us-west-2.postgun.com with SMTP id 5ececc0dbf0e32d254665e54 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 27 May 2020 20:22:37 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 69C3FC433AD; Wed, 27 May 2020 20:22:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-caf-mail-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=2.0 tests=ALL_TRUSTED,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from blr-ubuntu-87.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: sibis) by smtp.codeaurora.org (Postfix) with ESMTPSA id 316FCC433CA; Wed, 27 May 2020 20:22:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 316FCC433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v5 3/5] OPP: Add and export helper to set bandwidth Date: Thu, 28 May 2020 01:51:51 +0530 Message-Id: <20200527202153.11659-4-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200527202153.11659-1-sibis@codeaurora.org> References: <20200527202153.11659-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and export 'dev_pm_opp_set_bw' to set the bandwidth levels associated with an OPP. Signed-off-by: Sibi Sankar --- v5: https://lkml.org/lkml/2020/5/27/7 * Rework the patch based on ^^ v4: https://patchwork.kernel.org/patch/11019737/ * Pass device opp to set bw levels [Bjorn] drivers/opp/core.c | 31 +++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 6 ++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index df12c38045330..c87e69f26e976 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -831,6 +831,37 @@ static int _set_required_opps(struct device *dev, return ret; } +/** + * dev_pm_opp_set_bw() - sets bandwidth levels corresponding to an opp + * @dev: device for which we do this operation + * @opp: opp based on which the bandwidth levels are to be configured + * + * This configures the bandwidth to the levels specified by the OPP. However + * if the OPP specified is NULL the bandwidth levels are cleared out. + * + * Return: 0 on success or a negative error value. + */ +int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp) +{ + struct opp_table *opp_table; + int ret; + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + dev_err(dev, "%s: device opp table doesn't exist\n", __func__); + return PTR_ERR(opp_table); + } + + if (opp) + ret = _set_opp_bw(opp_table, opp, dev, false); + else + ret = _set_opp_bw(opp_table, opp, dev, true); + + dev_pm_opp_put_opp_table(opp_table); + return ret; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_set_bw); + /** * dev_pm_opp_set_rate() - Configure new OPP based on frequency * @dev: device for which we do this operation diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index d5c4a329321dd..ae68417c0ae00 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -151,6 +151,7 @@ struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char **names void dev_pm_opp_detach_genpd(struct opp_table *opp_table); int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate); int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq); +int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp); int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask); int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask); void dev_pm_opp_remove_table(struct device *dev); @@ -342,6 +343,11 @@ static inline int dev_pm_opp_set_rate(struct device *dev, unsigned long target_f return -ENOTSUPP; } +static inline int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp) +{ + return -EOPNOTSUPP; +} + static inline int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask) { return -ENOTSUPP; From patchwork Wed May 27 20:21:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11573897 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7BC9E913 for ; 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spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v5 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change Date: Thu, 28 May 2020 01:51:52 +0530 Message-Id: <20200527202153.11659-5-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200527202153.11659-1-sibis@codeaurora.org> References: <20200527202153.11659-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support to parse optional OPP table attached to the cpu node when the OPP bandwidth values are populated. This allows for scaling of DDR/L3 bandwidth levels with frequency change. Signed-off-by: Sibi Sankar --- V5: * Use dev_pm_opp_adjust_voltage instead [Viresh] * Misc cleanup v4: * Split fast switch disable into another patch [Lukasz] drivers/cpufreq/qcom-cpufreq-hw.c | 77 ++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index fc92a8842e252..fbd73d106a3ae 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,52 @@ static unsigned long cpu_hw_rate, xo_rate; static struct platform_device *global_pdev; +static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, + unsigned long freq_khz) +{ + unsigned long freq_hz = freq_khz * 1000; + struct dev_pm_opp *opp; + struct device *dev; + int ret; + + dev = get_cpu_device(policy->cpu); + if (!dev) + return -ENODEV; + + opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + ret = dev_pm_opp_set_bw(dev, opp); + dev_pm_opp_put(opp); + return ret; +} + +static int qcom_cpufreq_update_opp(struct device *cpu_dev, + unsigned long freq_khz, + unsigned long volt) +{ + unsigned long freq_hz = freq_khz * 1000; + + if (dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt)) + return dev_pm_opp_add(cpu_dev, freq_hz, volt); + + /* Enable the opp after voltage update */ + return dev_pm_opp_enable(cpu_dev, freq_hz); +} + +/* Check for optional interconnect paths on CPU0 */ +static int qcom_cpufreq_find_icc_paths(struct device *dev) +{ + struct device *cpu_dev; + + cpu_dev = get_cpu_device(0); + if (!cpu_dev) + return -EPROBE_DEFER; + + return dev_pm_opp_of_find_icc_paths(cpu_dev, NULL); +} + static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { @@ -39,6 +86,8 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy, writel_relaxed(index, perf_state_reg); + qcom_cpufreq_set_bw(policy, freq); + arch_set_freq_scale(policy->related_cpus, freq, policy->cpuinfo.max_freq); return 0; @@ -88,12 +137,30 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, { u32 data, src, lval, i, core_count, prev_freq = 0, freq; u32 volt; + u64 rate; struct cpufreq_frequency_table *table; + struct device_node *opp_table_np, *np; + int ret; table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) return -ENOMEM; + ret = dev_pm_opp_of_add_table(cpu_dev); + if (!ret) { + /* Disable all opps and cross-validate against LUT */ + opp_table_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); + for_each_available_child_of_node(opp_table_np, np) { + ret = of_property_read_u64(np, "opp-hz", &rate); + if (!ret) + dev_pm_opp_disable(cpu_dev, rate); + } + of_node_put(opp_table_np); + } else if (ret != -ENODEV) { + dev_err(cpu_dev, "Invalid OPP table in Device tree\n"); + return ret; + } + for (i = 0; i < LUT_MAX_ENTRIES; i++) { data = readl_relaxed(base + REG_FREQ_LUT + i * LUT_ROW_SIZE); @@ -112,7 +179,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (freq != prev_freq && core_count != LUT_TURBO_IND) { table[i].frequency = freq; - dev_pm_opp_add(cpu_dev, freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, freq, volt); dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i, freq, core_count); } else if (core_count == LUT_TURBO_IND) { @@ -133,7 +200,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, if (prev->frequency == CPUFREQ_ENTRY_INVALID) { prev->frequency = prev_freq; prev->flags = CPUFREQ_BOOST_FREQ; - dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt); + qcom_cpufreq_update_opp(cpu_dev, prev_freq, + volt); } break; @@ -254,6 +322,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) void __iomem *base = policy->driver_data - REG_PERF_STATE; dev_pm_opp_remove_all_dynamic(cpu_dev); + dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); kfree(policy->freq_table); devm_iounmap(&global_pdev->dev, base); @@ -301,6 +370,10 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) global_pdev = pdev; + ret = qcom_cpufreq_find_icc_paths(&pdev->dev); + if (ret) + return ret; + ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); From patchwork Wed May 27 20:21:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 11573905 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2110D1392 for ; Wed, 27 May 2020 20:23:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0960C2088E for ; Wed, 27 May 2020 20:23:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="degv2GfX" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728687AbgE0UW7 (ORCPT ); Wed, 27 May 2020 16:22:59 -0400 Received: from mail27.static.mailgun.info ([104.130.122.27]:39007 "EHLO mail27.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728673AbgE0UW6 (ORCPT ); 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Wed, 27 May 2020 20:22:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 15589C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=sibis@codeaurora.org From: Sibi Sankar To: viresh.kumar@linaro.org, sboyd@kernel.org, georgi.djakov@linaro.org, saravanak@google.com, mka@chromium.org Cc: nm@ti.com, bjorn.andersson@linaro.org, agross@kernel.org, rjw@rjwysocki.net, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dianders@chromium.org, vincent.guittot@linaro.org, amit.kucheria@linaro.org, lukasz.luba@arm.com, sudeep.holla@arm.com, smasetty@codeaurora.org, Sibi Sankar Subject: [PATCH v5 5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3 Date: Thu, 28 May 2020 01:51:53 +0530 Message-Id: <20200527202153.11659-6-sibis@codeaurora.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200527202153.11659-1-sibis@codeaurora.org> References: <20200527202153.11659-1-sibis@codeaurora.org> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Disable fast switch when the opp-tables required for scaling DDR/L3 are populated. Signed-off-by: Sibi Sankar --- V5: * Drop dev_pm_opp_get_path_count [Saravana] drivers/cpufreq/qcom-cpufreq-hw.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index fbd73d106a3ae..ff6ad7ac38411 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -159,6 +159,8 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, } else if (ret != -ENODEV) { dev_err(cpu_dev, "Invalid OPP table in Device tree\n"); return ret; + } else { + policy->fast_switch_possible = true; } for (i = 0; i < LUT_MAX_ENTRIES; i++) { @@ -308,8 +310,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) dev_pm_opp_of_register_em(policy->cpus); - policy->fast_switch_possible = true; - return 0; error: devm_iounmap(dev, base);