From patchwork Thu May 28 06:40:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574805 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A417414F6 for ; Thu, 28 May 2020 06:41:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82CEA207D3 for ; Thu, 28 May 2020 06:41:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="RJyQgJSB"; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="nSGbYcCu" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82CEA207D3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To: Cc:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JyymQUzxXUDUGDiP40j+IBmm1X5EOZ7V5M3pcfRs+Ww=; b=RJyQgJSBl5K6O+xas0bf+8TOrJ p5oP6LM+WQcDPQ3skzP2K9H5GIwy1FchJyooSCQ0i4FPk6vcR8sPes8botHftBzKp4BKLanwIxukq 2Z9Bwg1fC5UWcjiaEAgQ9pTm/i8VHX5L6/15vZeje20AcWDOmiCPmq6Ph8Z4A5ZH634AEaVOP6KmM kaiHpExAVebyh99+ll9aG6itIxzAa7+5WDXyd2RDebT5VXDuighj5p5/FhdnwQOKI1D8KrSKxjYMt EiDQJMW3dQEFAMF689eBk8o4Q1umHng/0NQlynLvh1Xwtr0TlKK3aR5TIr23lex+96e/U0obmjMXO E3ejVkXA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jeCE4-0002tp-4e; Thu, 28 May 2020 06:41:12 +0000 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jeCE1-0002sJ-Ms for linux-riscv@lists.infradead.org; Thu, 28 May 2020 06:41:10 +0000 Received: by mail-pj1-x1043.google.com with SMTP id fs4so2621181pjb.5 for ; Wed, 27 May 2020 23:41:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JyymQUzxXUDUGDiP40j+IBmm1X5EOZ7V5M3pcfRs+Ww=; b=nSGbYcCuCPGVWjqWOVHQqHC7PCTc5ij0fPoq6BySG33lzDVIrRf1JPtcQIa/ivVNc9 LNp4JStadItLWo3DkG7jtSC8S4UfDUs7Z3/FcsGVWV6j8G1HzAqO/e8E3luqMzTTBlqF xBwpRvvb+ZhCShoKJSNdQ06b+DZ2dTa2xGwpsrE9qGZkW1Dpa3XXHGFKnlocpHRhQB3d H+7baFMj3qh3tysiWMmi0SEYWLjDjy0C2hNDiC5EEwJ1DZrdS0o+0FU2eb3nVTsbjD88 j3KIPwQtNZWYO2prsVyg73MITSout1wEnd2r6jdyIOMS6FL1QEdKlp3LmdPegSnl2tNg /fuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JyymQUzxXUDUGDiP40j+IBmm1X5EOZ7V5M3pcfRs+Ww=; b=eWmqGgybt9W+6SiAtiYMaBIhrvw8jOnpq6jESuQvmC1lmLKxauto1cVIrR88S5o2b4 /loWE2KLpw4rDDqheK4hLAHEwmEiImlGKDk3p1SfbiHeSpaOVNkWv4YWnrjrR/ArC6py nZkaxS+29giblkJ45/DrOH8TJcKcjcO1LET/B4YL+NCajIL6XwsC97AdnkuonLwaE0Kc muBEqrXqRX1ITdFzeqjD+BKVeGaXrdhRtMaj9OEREQuacgs3EzCAZRs1mm3VpEp9OmAE atN46p6nHBgm0fE4EotxFn7QM5i+rjGmnoGReMI9/w17wWnby1zM7bZRkHfcar661G3G 7Rhg== X-Gm-Message-State: AOAM530EAXtW63vHXcOgqM/09ARyl54JkBOvmHx+bpbNJmvnup3qxKI6 idZwMxROhKAuTOrql+t93ybieg== X-Google-Smtp-Source: ABdhPJyEpNcQ/jhi+ZpBBDbNNGSgjR2nPmE8d9un/VQNilVdrTBX0PbZyELaHSNRxRHNtd7DAiBUrA== X-Received: by 2002:a17:90a:ac0a:: with SMTP id o10mr2080869pjq.79.1590648068965; Wed, 27 May 2020 23:41:08 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:08 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 01/13] ptrace: Use regset_size() for dynamic regset Date: Thu, 28 May 2020 14:40:49 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234109_749712_6E1D80A4 X-CRM114-Status: UNSURE ( 9.20 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1043 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org This patch uses regset_size() instead of using regset->n and regset->size directly. In this case, it will call the get_size() ported by arch dynamically to support dynamic regset size case. Signed-off-by: Greentime Hu Acked-by: Oleg Nesterov --- kernel/ptrace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/ptrace.c b/kernel/ptrace.c index 43d6179508d6..946b2c4ec4fa 100644 --- a/kernel/ptrace.c +++ b/kernel/ptrace.c @@ -888,7 +888,7 @@ static int ptrace_regset(struct task_struct *task, int req, unsigned int type, regset_no = regset - view->regsets; kiov->iov_len = min(kiov->iov_len, - (__kernel_size_t) (regset->n * regset->size)); + (__kernel_size_t) regset_size(task, regset)); if (req == PTRACE_GETREGSET) return copy_regset_to_user(task, view, regset_no, 0, From patchwork Thu May 28 06:40:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574807 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDEE214F6 for ; Thu, 28 May 2020 06:41:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB1C1207E8 for ; Thu, 28 May 2020 06:41:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QzunIF0C"; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="bmB1UJf8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB1C1207E8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To: Cc:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=82NB9lCPMwXynDeXK6u4yXJsBZGIDVjhoL3cA6mdRsQ=; b=QzunIF0CHfdYmn/Frvpcm0PBjK qfswSM4X0TFOQLtJAJkjn1FM3MXR+o8N+1/qw4a2gaCKsDq/PYv0Jwm2dqu5mrg5JwQeuRZ+x0uk8 vDxgK4S0ZFeq1w0GbAGZGk353J+3fMMXLE3kZzMFCRgciy1rLLKnO6IOECRAzc+BdaVv2Xo0x5//H AA7r/Xz3BaEQh5WrPG7eGdQWqHuUyuhWMTsoKKIKnzTscjqB48Zkvaag/YF1nveMzlNq4yjiGJoox 1XdsVCDRNnlYklIbTR8yEVKf0Mn+xHR41nDXfJdBvYNJ7R+CzeJnFR5UyS4qJOYp3R4ExMUv1aBY2 a0dcV+cQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jeCE6-0002y5-7k; Thu, 28 May 2020 06:41:14 +0000 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jeCE3-0002t1-NY for linux-riscv@lists.infradead.org; Thu, 28 May 2020 06:41:13 +0000 Received: by mail-pj1-x1044.google.com with SMTP id t8so2581937pju.3 for ; Wed, 27 May 2020 23:41:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=82NB9lCPMwXynDeXK6u4yXJsBZGIDVjhoL3cA6mdRsQ=; b=bmB1UJf8gpuxPRCB+XRx67sSBKWiEBE/R42DEzA16KYeAq+ifi6W6BVWNSYpIefiYJ 7RN8ZZJFBEbGfW/JCCMgkkUvSZMeP73CDEa7jWyI5U7pPXSv7HUGq4aBNuKAJjg7Ku8I goPQSW/uLYwP1PxWl1Vpq6FAcda4NJDG7Pfi939kYjkC6jlyJJRnFMv7r1Cy9MILKKyV oTyMne95DQOxrtjoJcxe+2xsaJhk96jUPjuWqvWWwGOWoprpY/siIqHrBqnPuLT6Z1VA rc/fNcT+2Wj3VTdlb4OQgHEhOtvC9VpA+zOfEghDLbpHc0xHaKd9g3T+NrKrA8yzDbro TjgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=82NB9lCPMwXynDeXK6u4yXJsBZGIDVjhoL3cA6mdRsQ=; b=IYjdfKA55h8fMlbIGhMVtmpkUG9pVk65TsI5Ebi4e1yH3fzv1FxAiCO48LTknZa2Ji 7qenvfCcuErb/w4mv4KNIC1kPmQlZp14jJToNw2d3EoFsgfjk8TTNG/UXc5B9HPAfaAK 5lAF7GV3r0UVkCCyiLEzhIx6w9bxUTH42EBe8bdGSDB0a+T5Ish9wFC0NFW6YbI742/9 DMIaStlLc4fVyVFgwOrHg6wfqtXQv7tV+7KsMCwUBwm+LosKqBjVi5ERl+hK60MzwVRp FLrFABfq+6x7FFupVMbdeMVST/BorpUiTf04cOn+2nHE8hHl5OFMiSuPk4B2LBVxbTvt +p/g== X-Gm-Message-State: AOAM533ufsrtVseFydOebjmxpXUldKRZCiKYXSJiTH+at0Yk26eXOAxk ryI0Q1FeeVcPvjT4+aH2VLVzyw== X-Google-Smtp-Source: ABdhPJwJxYGvMR1o+/BSgiQ889SGEkiIRZp44iAixVFd5RbTS+e+kjD7BYVeV/PDAFwFmuWjgHrBPw== X-Received: by 2002:a17:902:7002:: with SMTP id y2mr2053163plk.94.1590648070946; Wed, 27 May 2020 23:41:10 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:10 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 02/13] riscv: Separate patch for cflags and aflags Date: Thu, 28 May 2020 14:40:50 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234111_772055_63CE313B X-CRM114-Status: UNSURE ( 6.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1044 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren From: Guo Ren Use "subst fd" in Makefile is a hack way and it's not convenient to add new ISA feature. Just separate them into riscv-march-cflags and riscv-march-aflags. Signed-off-by: Guo Ren --- arch/riscv/Makefile | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index fb6e37db836d..957d064bead0 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -37,12 +37,18 @@ else endif # ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima -riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c -KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) -KBUILD_AFLAGS += -march=$(riscv-march-y) +riscv-march-cflags-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-cflags-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +riscv-march-cflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-cflags-y)c + +riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd +riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c + +KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) +KBUILD_AFLAGS += -march=$(riscv-march-aflags-y) KBUILD_CFLAGS += -mno-save-restore KBUILD_CFLAGS += -DCONFIG_PAGE_OFFSET=$(CONFIG_PAGE_OFFSET) From patchwork Thu May 28 06:40:51 2020 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:12 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 03/13] riscv: Rename __switch_to_aux -> fpu Date: Thu, 28 May 2020 14:40:51 +0800 Message-Id: <690bd2391cf1a44e23d1e6e4df58c1083a71c7af.1590646208.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234113_992465_EB4AAE8A X-CRM114-Status: GOOD ( 10.58 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:444 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren From: Guo Ren The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren Reviewed-by: Anup Patel --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 407bcc96a710..b9234e7178d0 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -44,7 +44,7 @@ static inline void fstate_restore(struct task_struct *task, } } -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -60,7 +60,7 @@ extern bool has_fpu; #define has_fpu false #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif extern struct task_struct *__switch_to(struct task_struct *, @@ -71,7 +71,7 @@ do { \ struct task_struct *__prev = (prev); \ struct task_struct *__next = (next); \ if (has_fpu) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) From patchwork Thu May 28 06:40:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574811 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB92814F6 for ; Thu, 28 May 2020 06:41:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B97AB207E8 for ; Thu, 28 May 2020 06:41:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FKRLIKqt"; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:14 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 04/13] riscv: Extending cpufeature.c to detect V-extension Date: Thu, 28 May 2020 14:40:52 +0800 Message-Id: <4b2a5ec77dd0eee02818abb036518930fed8b105.1590646208.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234116_855265_2EE8DC68 X-CRM114-Status: UNSURE ( 9.28 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:544 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren From: Guo Ren Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it. Signed-off-by: Guo Ren Reviewed-by: Anup Patel --- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index dee98ee28318..a913e9a38819 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a5ad00043104..c8527d770c98 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,7 @@ void riscv_fill_hwcap(void) isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F; isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; + isa2hwcap['v'] = isa2hwcap['V'] = COMPAT_HWCAP_ISA_V; elf_hwcap = 0; @@ -44,7 +45,8 @@ void riscv_fill_hwcap(void) continue; } - for (i = 0; i < strlen(isa); ++i) + /* Skip rv64/rv32 to support v/V:vector */ + for (i = 4; i < strlen(isa); ++i) this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; /* From patchwork Thu May 28 06:40:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574813 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0CFF14F6 for ; Thu, 28 May 2020 06:41:29 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E22F2084C for ; Thu, 28 May 2020 06:41:29 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:17 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 05/13] riscv: Add new csr defines related to vector extension Date: Thu, 28 May 2020 14:40:53 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234118_578571_7BECF6D9 X-CRM114-Status: UNSURE ( 7.55 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:644 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren Follow the riscv vector spec to add new csr number. [greentime.hu@sifive.com: update the defined value based on new spec and remove unused ones] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 8e18d2c64399..cc13626c4bbe 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,6 +24,12 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) @@ -31,9 +37,9 @@ #define SR_XS_DIRTY _AC(0x00018000, UL) #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif /* SATP flags */ @@ -114,6 +120,12 @@ #define CSR_PMPADDR0 0x3b0 #define CSR_MHARTID 0xf14 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE From patchwork Thu May 28 06:40:54 2020 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:19 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 06/13] riscv: Add vector feature to compile Date: Thu, 28 May 2020 14:40:54 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234121_439284_11E52560 X-CRM114-Status: UNSURE ( 8.70 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:641 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren This patch adds a new config option which could enable assembler's vector feature. Signed-off-by: Guo Ren --- arch/riscv/Kconfig | 9 +++++++++ arch/riscv/Makefile | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 74f82cf4f781..3b742d949a09 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -305,6 +305,15 @@ config FPU If you don't know what to do here, say Y. +config VECTOR + bool "VECTOR support" + default n + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + endmenu menu "Kernel features" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 957d064bead0..7c80c95582e3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -46,6 +46,7 @@ riscv-march-aflags-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-aflags-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-aflags-$(CONFIG_FPU) := $(riscv-march-aflags-y)fd riscv-march-aflags-$(CONFIG_RISCV_ISA_C) := $(riscv-march-aflags-y)c +riscv-march-aflags-$(CONFIG_VECTOR) := $(riscv-march-aflags-y)v KBUILD_CFLAGS += -march=$(riscv-march-cflags-y) KBUILD_AFLAGS += -march=$(riscv-march-aflags-y) From patchwork Thu May 28 06:40:55 2020 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:21 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 07/13] riscv: Add has_vector/riscv_vsize to save vector features. Date: Thu, 28 May 2020 14:40:55 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234123_645826_8E6912B7 X-CRM114-Status: UNSURE ( 8.90 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1042 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [greentime.hu@sifive.com: add support for dynamic vlen] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c8527d770c98..5a68a926da68 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -16,6 +16,10 @@ unsigned long elf_hwcap __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif void riscv_fill_hwcap(void) { @@ -73,4 +77,11 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } From patchwork Thu May 28 06:40:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574817 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9806014F6 for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:23 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 08/13] riscv: Reset vector register Date: Thu, 28 May 2020 14:40:56 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234125_904908_A16B8892 X-CRM114-Status: GOOD ( 10.13 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:641 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren Reset vector registers at boot-time and disable vector instructions execution for kernel mode. Signed-off-by: Guo Ren --- arch/riscv/kernel/entry.S | 2 +- arch/riscv/kernel/head.S | 49 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 48 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 56d071b2c0a1..4e32770c19c8 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -70,7 +70,7 @@ _save_context: * Disable the FPU to detect illegal usage of floating point in kernel * space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS | SR_VS REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 98a406474e7d..1290ef680125 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -181,10 +181,10 @@ ENTRY(_start_kernel) .option pop /* - * Disable FPU to detect illegal usage of + * Disable FPU & VECTOR to detect illegal usage of * floating point in kernel space */ - li t0, SR_FS + li t0, SR_FS | SR_VS csrc CSR_STATUS, t0 #ifdef CONFIG_SMP @@ -341,6 +341,51 @@ ENTRY(reset_regs) csrw fcsr, 0 /* note that the caller must clear SR_FS */ #endif /* CONFIG_FPU */ + +#ifdef CONFIG_VECTOR + csrr t0, CSR_MISA + li t1, (COMPAT_HWCAP_ISA_V >> 16) + slli t1, t1, 16 + and t0, t0, t1 + beqz t0, .Lreset_regs_done + + li t1, SR_VS + csrs CSR_STATUS, t1 + vmv.v.i v0, 0 + vmv.v.i v1, 0 + vmv.v.i v2, 0 + vmv.v.i v3, 0 + vmv.v.i v4, 0 + vmv.v.i v5, 0 + vmv.v.i v6, 0 + vmv.v.i v7, 0 + vmv.v.i v8, 0 + vmv.v.i v9, 0 + vmv.v.i v10, 0 + vmv.v.i v11, 0 + vmv.v.i v12, 0 + vmv.v.i v13, 0 + vmv.v.i v14, 0 + vmv.v.i v15, 0 + vmv.v.i v16, 0 + vmv.v.i v17, 0 + vmv.v.i v18, 0 + vmv.v.i v19, 0 + vmv.v.i v20, 0 + vmv.v.i v21, 0 + vmv.v.i v22, 0 + vmv.v.i v23, 0 + vmv.v.i v24, 0 + vmv.v.i v25, 0 + vmv.v.i v26, 0 + vmv.v.i v27, 0 + vmv.v.i v28, 0 + vmv.v.i v29, 0 + vmv.v.i v30, 0 + vmv.v.i v31, 0 + /* note that the caller must clear SR_VS */ +#endif /* CONFIG_VECTOR */ + .Lreset_regs_done: ret END(reset_regs) From patchwork Thu May 28 06:40:57 2020 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:25 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 09/13] riscv: Add vector struct and assembler definitions Date: Thu, 28 May 2020 14:40:57 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234127_361940_85441305 X-CRM114-Status: GOOD ( 10.25 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:1043 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren Add vector state context struct in struct thread and asm-offsets.c definitions. The vector registers will be saved in datap pointer of __riscv_v_state. It will be dynamically allocated in kernel space. It will be put right after the __riscv_v_state data structure in user space. [greentime.hu@sifive.com: add support for dynamic vlen, add vcsr and remove vxsat, vxrm because these data can be get in vcsr, add new macros for _riscv_v_state elements offset and remove unused ones] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 13 +++++++++++++ arch/riscv/kernel/asm-offsets.c | 8 ++++++++ 3 files changed, 22 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 3ddb798264f1..217273375cfb 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -32,6 +32,7 @@ struct thread_struct { unsigned long sp; /* Kernel mode stack */ unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; + struct __riscv_v_state vstate; }; #define INIT_THREAD { \ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 882547f6bd5c..661b0466b850 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,6 +77,19 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; +struct __riscv_v_state { + __u32 magic; + __u32 size; + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + void *datap; +#if __riscv_xlen == 32 + __u32 __padding; +#endif +} __attribute__((aligned(16))); + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 07cb9c10de4e..6627fde230b2 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -70,6 +70,14 @@ void asm_offsets(void) OFFSET(TASK_THREAD_F31, task_struct, thread.fstate.f[31]); OFFSET(TASK_THREAD_FCSR, task_struct, thread.fstate.fcsr); + OFFSET(RISCV_V_STATE_MAGIC, __riscv_v_state, magic); + OFFSET(RISCV_V_STATE_SIZE, __riscv_v_state, size); + OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart); + OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl); + OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype); + OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr); + OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap); + DEFINE(PT_SIZE, sizeof(struct pt_regs)); OFFSET(PT_EPC, pt_regs, epc); OFFSET(PT_RA, pt_regs, ra); From patchwork Thu May 28 06:40:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574825 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C8F6C14F6 for ; Thu, 28 May 2020 06:41:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3D15207E8 for ; Thu, 28 May 2020 06:41:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="RK6NmSDj"; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="MD5Ps8/n" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3D15207E8 Authentication-Results: mail.kernel.org; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:28 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 10/13] riscv: Add task switch support for vector Date: Thu, 28 May 2020 14:40:58 +0800 Message-Id: <9f6b9469732f1334d8ac69261631360589d4f9c0.1590646208.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234129_603987_BB3BF171 X-CRM114-Status: GOOD ( 18.20 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:641 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nick Knight Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren This patch adds task switch support for vector. It supports lazy save and restore mechanism. It also supports all lengths of vlen. [greentime.hu@sifive.com: add support for dynamic vlen, fix __vstate_clean() and lazy save/restore bug] [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and code refine] Signed-off-by: Nick Knight Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/asm/switch_to.h | 71 +++++++++++++++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/process.c | 40 ++++++++++++++ arch/riscv/kernel/vector.S | 84 ++++++++++++++++++++++++++++++ 4 files changed, 196 insertions(+) create mode 100644 arch/riscv/kernel/vector.S diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index b9234e7178d0..a047dd75e09d 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -6,10 +6,12 @@ #ifndef _ASM_RISCV_SWITCH_TO_H #define _ASM_RISCV_SWITCH_TO_H +#include #include #include #include #include +#include #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -63,6 +65,73 @@ extern bool has_fpu; #define __switch_to_fpu(__prev, __next) do { } while (0) #endif +#ifdef CONFIG_VECTOR +extern bool has_vector; +extern unsigned long riscv_vsize; +extern void __vstate_save(struct __riscv_v_state *save_to, void *datap); +extern void __vstate_restore(struct __riscv_v_state *restore_from, void *datap); + +static inline void __vstate_clean(struct pt_regs *regs) +{ + regs->status = (regs->status & ~(SR_VS)) | SR_VS_CLEAN; +} + +static inline void vstate_off(struct task_struct *task, + struct pt_regs *regs) +{ + regs->status = (regs->status & ~SR_VS) | SR_VS_OFF; +} + +static inline void vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) == SR_VS_DIRTY) { + struct __riscv_v_state *vstate = &(task->thread.vstate); + + /* Allocate space for vector registers. */ + if (!vstate->datap) { + vstate->datap = kzalloc(riscv_vsize, GFP_KERNEL); + vstate->size = riscv_vsize; + } + __vstate_save(vstate, vstate->datap); + __vstate_clean(regs); + } +} + +static inline void vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) != SR_VS_OFF) { + struct __riscv_v_state *vstate = &(task->thread.vstate); + + /* Allocate space for vector registers. */ + if (!vstate->datap) { + vstate->datap = kzalloc(riscv_vsize, GFP_KERNEL); + vstate->size = riscv_vsize; + } + __vstate_restore(vstate, vstate->datap); + __vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs = task_pt_regs(prev); + if (unlikely(regs->status & SR_SD)) + vstate_save(prev, regs); + vstate_restore(next, task_pt_regs(next)); +} + +#else +#define has_vector false +#define vstate_save(task, regs) do { } while (0) +#define vstate_restore(task, regs) do { } while (0) +#define __switch_to_vector(__prev, __next) do { } while (0) +#endif + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); @@ -72,6 +141,8 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu) \ __switch_to_fpu(__prev, __next); \ + if (has_vector) \ + __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 86c83081044f..dee489a1a526 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += clint.o traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o +obj-$(CONFIG_VECTOR) += vector.o obj-$(CONFIG_SMP) += smpboot.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += cpu_ops.o diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 610c11e91606..fc8761c04e9f 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -76,6 +76,16 @@ void start_thread(struct pt_regs *regs, unsigned long pc, */ fstate_restore(current, regs); } + + if (has_vector) { + regs->status |= SR_VS_INITIAL; + /* + * Restore the initial value to the vector register + * before starting the user program. + */ + vstate_restore(current, regs); + } + regs->epc = pc; regs->sp = sp; set_fs(USER_DS); @@ -92,15 +102,45 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_VECTOR + /* Reset vector state */ + vstate_off(current, task_pt_regs(current)); + memset(¤t->thread.vstate, 0, sizeof(current->thread.vstate)); +#endif } int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); + if (has_vector) + /* To make sure every dirty vector context is saved. */ + vstate_save(src, task_pt_regs(src)); *dst = *src; + if (has_vector) { + /* Copy vector context to the forked task from parent. */ + if ((task_pt_regs(src)->status & SR_VS) != SR_VS_OFF) { + unsigned long size = src->thread.vstate.size; + + dst->thread.vstate.datap = kzalloc(size, GFP_KERNEL); + /* Failed to allocate memory. */ + if (!dst->thread.vstate.datap) + return -ENOMEM; + /* Copy the src vector context to dst. */ + memcpy(dst->thread.vstate.datap, + src->thread.vstate.datap, size); + } + } + return 0; } +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector) + kfree(tsk->thread.vstate.datap); +} + int copy_thread_tls(unsigned long clone_flags, unsigned long usp, unsigned long arg, struct task_struct *p, unsigned long tls) { diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S new file mode 100644 index 000000000000..91d5dd29cd0f --- /dev/null +++ b/arch/riscv/kernel/vector.S @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2019 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include + +#define vstatep a0 +#define datap a1 +#define x_vstart t0 +#define x_vtype t1 +#define x_vl t2 +#define x_vcsr t3 +#define incr t4 +#define m_one t5 +#define status t6 + +ENTRY(__vstate_save) + li status, SR_VS + csrs sstatus, status + + csrr x_vstart, CSR_VSTART + csrr x_vtype, CSR_VTYPE + csrr x_vl, CSR_VL + csrr x_vcsr, CSR_VCSR + li m_one, -1 + vsetvli incr, m_one, e8, m8 + vse.v v0, (datap) + add datap, datap, incr + vse.v v8, (datap) + add datap, datap, incr + vse.v v16, (datap) + add datap, datap, incr + vse.v v24, (datap) + + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_S x_vl, RISCV_V_STATE_VL(vstatep) + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep) + + csrc sstatus, status + ret +ENDPROC(__vstate_save) + +ENTRY(__vstate_restore) + li status, SR_VS + csrs sstatus, status + + li m_one, -1 + vsetvli incr, m_one, e8, m8 + vle.v v0, (datap) + add datap, datap, incr + vle.v v8, (datap) + add datap, datap, incr + vle.v v16, (datap) + add datap, datap, incr + vle.v v24, (datap) + + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_L x_vl, RISCV_V_STATE_VL(vstatep) + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep) + vsetvl x0, x_vl, x_vtype + csrw CSR_VSTART, x_vstart + csrw CSR_VCSR, x_vcsr + + csrc sstatus, status + ret +ENDPROC(__vstate_restore) From patchwork Thu May 28 06:40:59 2020 Content-Type: text/plain; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:30 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 11/13] riscv: Add ptrace vector support Date: Thu, 28 May 2020 14:40:59 +0800 Message-Id: <30cc61919c7b6ae3d65970c99a1e2e76cb045eaf.1590646208.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234135_203169_AFAD9BAA X-CRM114-Status: GOOD ( 15.81 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:441 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren This patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_state. This pointer will be set right after the __riscv_v_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. [greentime.hu@sifive.com: add support for dynamic vlen, fix vtype not saved bug] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/elf.h | 1 + arch/riscv/kernel/ptrace.c | 115 ++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 117 insertions(+) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..099434d075a7 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -23,6 +23,7 @@ typedef struct user_regs_struct elf_gregset_t; typedef __u64 elf_fpreg_t; typedef union __riscv_fp_state elf_fpregset_t; #define ELF_NFPREG (sizeof(struct __riscv_d_ext_state) / sizeof(elf_fpreg_t)) +#define ELF_NVREG (sizeof(struct __riscv_v_state) / sizeof(elf_greg_t)) #if __riscv_xlen == 64 #define ELF_RISCV_R_SYM(r_info) ELF64_R_SYM(r_info) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 444dc7b0fd78..ff846a53cd8d 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,9 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif +#ifdef CONFIG_VECTOR + REGSET_V, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -92,6 +96,107 @@ static int riscv_fpr_set(struct task_struct *target, } #endif +#ifdef CONFIG_VECTOR +static int riscv_vr_get(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + void *kbuf, void __user *ubuf) +{ + int ret; + struct __riscv_v_state *vstate = &target->thread.vstate; + /* Set the datap right after the address of vstate. */ + void *datap = ubuf + sizeof(struct __riscv_v_state); + u32 magic = RVV_MAGIC; + + /* Copy the magic number. */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &magic, 0, + sizeof(u32)); + if (unlikely(ret)) + return ret; + + /* Copy rest of vstate except datap. */ + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, vstate, 0, + RISCV_V_STATE_DATAP); + if (unlikely(ret)) + return ret; + + /* Copy the pointer datap itself. */ + pos = 0; + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &datap, 0, + sizeof(vstate->datap)); + if (unlikely(ret)) + return ret; + +#if __riscv_xlen == 32 + /* Skip copy _padding. */ + size = sizeof(vstate->__padding); + count -= size; + ubuf += size; +#endif + + /* Copy all the vector registers. */ + pos = 0; + ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, + vstate->datap, 0, vstate->size); + return ret; +} + +static int riscv_vr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret, size; + struct __riscv_v_state *vstate = &target->thread.vstate; + const void *datap = ubuf + sizeof(struct __riscv_v_state); + const void *datap_addr = ubuf + RISCV_V_STATE_DATAP; + long val_datap; + + /* Skip copy magic because kernel doesn't need to use it. */ + size = sizeof(vstate->magic); + pos += size; + count -= size; + ubuf += size; + + /* Copy rest of the vstate except datap and __padding. */ + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, + RISCV_V_STATE_DATAP); + if (unlikely(ret)) + return ret; + + /* Check if the datap is correct address of ubuf. */ + __get_user(val_datap, (long *)datap_addr); + if (val_datap != (long)datap) + return -EFAULT; + + /* Skip copy datap. */ + size = sizeof(vstate->datap); + count -= size; + ubuf += size; + +#if __riscv_xlen == 32 + /* Skip copy _padding. */ + size = sizeof(vstate->__padding); + count -= size; + ubuf += size; +#endif + + /* Copy all the vector registers. */ + pos = 0; + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap, + 0, vstate->size); + return ret; +} +static unsigned int riscv_vr_get_size(struct task_struct *target, + const struct user_regset *regset) +{ + if (!has_vector) + return 0; + + return sizeof(struct __riscv_v_state) + riscv_vsize; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -111,6 +216,16 @@ static const struct user_regset riscv_user_regset[] = { .set = &riscv_fpr_set, }, #endif +#ifdef CONFIG_VECTOR + [REGSET_V] = { + .core_note_type = NT_RISCV_VECTOR, + .align = 16, + .size = sizeof(unsigned long), + .get = riscv_vr_get, + .set = riscv_vr_set, + .get_size = riscv_vr_get_size, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 34c02e4290fe..e428f9e8710a 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -428,6 +428,7 @@ typedef struct elf64_shdr { #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ /* Note header in a PT_NOTE section */ typedef struct elf32_note { From patchwork Thu May 28 06:41:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574829 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B6031392 for ; Thu, 28 May 2020 06:41:54 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78A18207BC for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:35 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 12/13] riscv: Add sigcontext save/restore for vector Date: Thu, 28 May 2020 14:41:00 +0800 Message-Id: <8b544fbcee934ad31235049f49a14c8e7601692b.1590646208.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234144_091709_C09CF4E0 X-CRM114-Status: GOOD ( 11.79 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:544 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Guo Ren This patch adds sigcontext save/restore for vector. The vector registers will be saved in datap pointer. The datap pointer will be allocaed dynamically when the task needs in kernel space. The datap pointer will be set right after the __riscv_v_state data structure to save all the vector registers in the signal handler stack. [greentime.hu@sifive.com: add support for dynamic vlen] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/include/uapi/asm/sigcontext.h | 2 + arch/riscv/kernel/signal.c | 92 +++++++++++++++++++++++- 2 files changed, 91 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/uapi/asm/sigcontext.h index 84f2dfcfdbce..4217f3f1c8ba 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -8,6 +8,7 @@ #include +#define RVV_MAGIC 0x53465457 /* * Signal context structure * @@ -17,6 +18,7 @@ struct sigcontext { struct user_regs_struct sc_regs; union __riscv_fp_state sc_fpregs; + struct __riscv_v_state sc_vregs; }; #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 17ba190e84a5..9ada6f74bb95 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -83,6 +83,80 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif +#ifdef CONFIG_VECTOR +static long restore_v_state(struct pt_regs *regs, struct sigcontext *sc) +{ + long err; + struct __riscv_v_state __user *state = &sc->sc_vregs; + void *datap; + __u32 magic; + + /* Get magic number and check it. */ + err = __get_user(magic, &state->magic); + if (unlikely(err)) + return err; + + if (magic != RVV_MAGIC) + return -EINVAL; + + /* Copy everything of __riscv_v_state except datap. */ + err = __copy_from_user(¤t->thread.vstate, state, + RISCV_V_STATE_DATAP); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err = __get_user(datap, &state->datap); + if (unlikely(err)) + return err; + + + /* Copy the whole vector content from user space datap. */ + err = __copy_from_user(current->thread.vstate.datap, datap, + current->thread.vstate.size); + if (unlikely(err)) + return err; + + vstate_restore(current, regs); + + return err; +} + +static long save_v_state(struct pt_regs *regs, struct sigcontext *sc) +{ + long err; + struct __riscv_v_state __user *state = &sc->sc_vregs; + /* Set the datap right after the sigcntext structure. */ + void *datap = sc + 1; + + vstate_save(current, regs); + /* Copy everything of vstate but datap. */ + err = __copy_to_user(state, ¤t->thread.vstate, + RISCV_V_STATE_DATAP); + if (unlikely(err)) + return err; + + /* Copy the magic number. */ + err = __put_user(RVV_MAGIC, &state->magic); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err = __put_user(datap, &state->datap); + if (unlikely(err)) + return err; + + /* Copy the whole vector content to user space datap. */ + err = __copy_to_user(datap, current->thread.vstate.datap, + current->thread.vstate.size); + + return err; +} +#else +#define save_v_state(task, regs) (0) +#define restore_v_state(task, regs) (0) +#endif + static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { @@ -92,6 +166,9 @@ static long restore_sigcontext(struct pt_regs *regs, /* Restore the floating-point state. */ if (has_fpu) err |= restore_fp_state(regs, &sc->sc_fpregs); + /* Restore the vector state. */ + if (has_vector) + err |= restore_v_state(regs, sc); return err; } @@ -101,13 +178,16 @@ SYSCALL_DEFINE0(rt_sigreturn) struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; + size_t frame_size = sizeof(*frame); /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn = do_no_restart_syscall; frame = (struct rt_sigframe __user *)regs->sp; - if (!access_ok(frame, sizeof(*frame))) + if (has_vector) + frame_size += current->thread.vstate.size; + if (!access_ok(frame, frame_size)) goto badframe; if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) @@ -145,6 +225,9 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, /* Save the floating-point state. */ if (has_fpu) err |= save_fp_state(regs, &sc->sc_fpregs); + /* Save the vector state. */ + if (has_vector) + err |= save_v_state(regs, sc); return err; } @@ -176,9 +259,12 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, { struct rt_sigframe __user *frame; long err = 0; + size_t frame_size = sizeof(*frame); - frame = get_sigframe(ksig, regs, sizeof(*frame)); - if (!access_ok(frame, sizeof(*frame))) + if (has_vector) + frame_size += current->thread.vstate.size; + frame = get_sigframe(ksig, regs, frame_size); + if (!access_ok(frame, frame_size)) return -EFAULT; err |= copy_siginfo_to_user(&frame->info, &ksig->info); From patchwork Thu May 28 06:41:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greentime Hu X-Patchwork-Id: 11574831 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CE6314F6 for ; Thu, 28 May 2020 06:41:58 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 29428207BC for ; Thu, 28 May 2020 06:41:58 +0000 (UTC) Authentication-Results: mail.kernel.org; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id q29sm3773366pfg.79.2020.05.27.23.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 May 2020 23:41:44 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, guoren@linux.alibaba.com, vincent.chen@sifive.com, paul.walmsley@sifive.com, palmerdabbelt@google.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, oleg@redhat.com Subject: [RFC PATCH v5 13/13] riscv: signal: Report signal frame size to userspace via auxv Date: Thu, 28 May 2020 14:41:01 +0800 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200527_234146_926623_63E523B5 X-CRM114-Status: GOOD ( 12.71 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:541 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org From: Vincent Chen The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ #define (2KB) to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Signed-off-by: Vincent Chen --- arch/riscv/include/asm/elf.h | 17 +++++++++++++---- arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 2 ++ arch/riscv/kernel/setup.c | 5 +++++ arch/riscv/kernel/signal.c | 16 ++++++++++++++++ 5 files changed, 38 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index d83a4efd052b..b6b15fc5f784 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -57,10 +57,19 @@ extern unsigned long elf_hwcap; #define ELF_PLATFORM (NULL) #ifdef CONFIG_MMU -#define ARCH_DLINFO \ -do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 217273375cfb..5be2da702897 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include +#include #include @@ -79,6 +80,7 @@ int riscv_of_processor_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index d86cb17bbabe..9745a01e5e61 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -10,4 +10,6 @@ /* vDSO location */ #define AT_SYSINFO_EHDR 33 +#define AT_MINSIGSTKSZ 51 + #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 145128a7e560..6220e25ea9b0 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -62,6 +63,8 @@ void __init parse_dtb(void) #endif } +extern void __init minsigstksz_setup(void); + void __init setup_arch(char **cmdline_p) { init_mm.start_code = (unsigned long) _stext; @@ -95,6 +98,8 @@ void __init setup_arch(char **cmdline_p) #endif riscv_fill_hwcap(); + + minsigstksz_setup(); } static int __init topology_init(void) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 9ada6f74bb95..4f81251867e6 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -404,3 +404,19 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs, tracehook_notify_resume(regs); } } + +unsigned long __ro_after_init signal_minsigstksz; + +/* + * Determine the stack space required for guaranteed signal devliery. + * This function is used to populate AT_MINSIGSTKSZ at process startup. + * cpufeatures setup is assumed to be complete. + */ +void __init minsigstksz_setup(void) +{ + signal_minsigstksz = sizeof(struct rt_sigframe); +#ifdef CONFIG_VECTOR + if (has_vector) + signal_minsigstksz += riscv_vsize; +#endif +}