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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id r4-v6sm5949838ljg.12.2018.10.11.00.42.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 Oct 2018 00:42:26 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Mark Brown , linux-spi@vger.kernel.org Cc: Kamal Dasu , Boris Brezillon , Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH FIX] spi: bcm-qspi: switch back to reading flash using smaller chunks Date: Thu, 11 Oct 2018 09:42:17 +0200 Message-Id: <20181011074217.10149-1-zajec5@gmail.com> X-Mailer: git-send-email 2.13.7 MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rafał Miłecki Fixing/optimizing bcm_qspi_bspi_read() performance introduced two changes: 1) It added a loop to read all requested data using multiple BSPI ops. 2) It bumped max size of a single BSPI block request from 256 to 512 B. The later change resulted in occasional BSPI timeouts causing a regression. For some unknown reason hardware doesn't always handle reads as expected when using 512 B chunks. In such cases it may happen that BSPI returns amount of requested bytes without the last 1-3 ones. It provides the remaining bytes later but doesn't raise an interrupt until another LR start. Switching back to 256 B reads fixes that problem and regression. Fixes: 345309fa7c0c ("spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance") Signed-off-by: Rafał Miłecki Cc: stable@vger.kernel.org # 4.11+ --- This fixes a regression I reported 2,5 months ago in the e-mail thread: bcm-qspi: unstable bspi mode since the 345309fa7c0c ("spi: bcm-qspi: Fix bcm_qspi_bspi_read() performance") --- drivers/spi/spi-bcm-qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index eb3d67f01e8c..584bcb018a62 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -89,7 +89,7 @@ #define BSPI_BPP_MODE_SELECT_MASK BIT(8) #define BSPI_BPP_ADDR_SELECT_MASK BIT(16) -#define BSPI_READ_LENGTH 512 +#define BSPI_READ_LENGTH 256 /* MSPI register offsets */ #define MSPI_SPCR0_LSB 0x000