From patchwork Wed Jun 3 08:54:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585349 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 084EA618 for ; Wed, 3 Jun 2020 08:55:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF41D207ED for ; Wed, 3 Jun 2020 08:55:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726365AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from mx.socionext.com ([202.248.49.38]:18835 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726202AbgFCIyw (ORCPT ); Wed, 3 Jun 2020 04:54:52 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:50 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 625E7180BCB; Wed, 3 Jun 2020 17:54:50 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:50 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id A7A7D1A12AD; Wed, 3 Jun 2020 17:54:49 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi , Marc Zyngier Subject: [PATCH v3 1/6] PCI: dwc: Add msi_host_isr() callback Date: Wed, 3 Jun 2020 17:54:36 +0900 Message-Id: <1591174481-13975-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds msi_host_isr() callback function support to describe SoC-dependent service triggered by MSI. For example, when AER interrupt is triggered by MSI, the callback function reads SoC-dependent registers and detects that the interrupt is from AER, and invoke AER interrupts related to MSI. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++---- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0a4a5aa..9b628a2 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -112,13 +112,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) static void dw_chained_msi_isr(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - struct pcie_port *pp; + struct pcie_port *pp = irq_desc_get_handler_data(desc); - chained_irq_enter(chip, desc); + if (pp->ops->msi_host_isr) + pp->ops->msi_host_isr(pp); - pp = irq_desc_get_handler_data(desc); + chained_irq_enter(chip, desc); dw_handle_msi_irq(pp); - chained_irq_exit(chip, desc); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 656e00f..e741967 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -170,6 +170,7 @@ struct dw_pcie_host_ops { void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_isr)(struct pcie_port *pp); }; struct pcie_port { From patchwork Wed Jun 3 08:54:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585341 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E01D618 for ; Wed, 3 Jun 2020 08:55:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EDEF9207D3 for ; Wed, 3 Jun 2020 08:55:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726390AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from mx.socionext.com ([202.248.49.38]:18848 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726296AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:50 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id C2B22180BCB; Wed, 3 Jun 2020 17:54:50 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:50 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 716CF1A12AD; Wed, 3 Jun 2020 17:54:50 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi , Marc Zyngier Subject: [PATCH v3 2/6] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Date: Wed, 3 Jun 2020 17:54:37 +0900 Message-Id: <1591174481-13975-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The misc interrupts consisting of PME, AER, and Link event, is handled by INTx handler, however, these interrupts should be also handled by MSI handler. This adds the function uniphier_pcie_misc_isr() that handles misc intterupts, which is called from both INTx and MSI handlers. This function detects PME and AER interrupts with the status register, and invoke PME and AER drivers related to INTx or MSI. And this sets the mask for misc interrupts from INTx if MSI is enabled and sets the mask for misc interrupts from MSI if MSI is disabled. Cc: Marc Zyngier Cc: Jingoo Han Cc: Gustavo Pimentel Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 53 +++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index a5401a0..a8dda39 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -44,7 +44,9 @@ #define PCL_SYS_AUX_PWR_DET BIT(8) #define PCL_RCV_INT 0x8108 +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) #define PCL_CFG_BW_MGT_STATUS BIT(4) #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) @@ -167,7 +169,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) { - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); + u32 val; + + val = PCL_RCV_INT_ALL_ENABLE; + if (pci_msi_enabled()) + val |= PCL_RCV_INT_ALL_INT_MASK; + else + val |= PCL_RCV_INT_ALL_MSI_MASK; + + writel(val, priv->base + PCL_RCV_INT); writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); } @@ -231,28 +241,48 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = { .map = uniphier_pcie_intx_map, }; -static void uniphier_pcie_irq_handler(struct irq_desc *desc) +static void uniphier_pcie_misc_isr(struct pcie_port *pp) { - struct pcie_port *pp = irq_desc_get_handler_data(desc); struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); - struct irq_chip *chip = irq_desc_get_chip(desc); - unsigned long reg; - u32 val, bit, virq; + u32 val, virq; - /* INT for debug */ val = readl(priv->base + PCL_RCV_INT); if (val & PCL_CFG_BW_MGT_STATUS) dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); + if (val & PCL_CFG_LINK_AUTO_BW_STATUS) dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); - if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) - dev_dbg(pci->dev, "Root Error\n"); - if (val & PCL_CFG_PME_MSI_STATUS) - dev_dbg(pci->dev, "PME Interrupt\n"); + + if (pci_msi_enabled()) { + if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) { + dev_dbg(pci->dev, "Root Error Status\n"); + virq = irq_linear_revmap(pp->irq_domain, 0); + generic_handle_irq(virq); + } + + if (val & PCL_CFG_PME_MSI_STATUS) { + dev_dbg(pci->dev, "PME Interrupt\n"); + virq = irq_linear_revmap(pp->irq_domain, 0); + generic_handle_irq(virq); + } + } writel(val, priv->base + PCL_RCV_INT); +} + +static void uniphier_pcie_irq_handler(struct irq_desc *desc) +{ + struct pcie_port *pp = irq_desc_get_handler_data(desc); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long reg; + u32 val, bit, virq; + + /* misc interrupt */ + uniphier_pcie_misc_isr(pp); /* INTx */ chained_irq_enter(chip, desc); @@ -330,6 +360,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { .host_init = uniphier_pcie_host_init, + .msi_host_isr = uniphier_pcie_misc_isr, }; static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, From patchwork Wed Jun 3 08:54:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585337 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5B8492A for ; Wed, 3 Jun 2020 08:54:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AEBD5207D3 for ; Wed, 3 Jun 2020 08:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726321AbgFCIyy (ORCPT ); Wed, 3 Jun 2020 04:54:54 -0400 Received: from mx.socionext.com ([202.248.49.38]:18827 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725854AbgFCIyx (ORCPT ); Wed, 3 Jun 2020 04:54:53 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:51 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id E9ADB60057; Wed, 3 Jun 2020 17:54:51 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:51 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 40D0F1A12AD; Wed, 3 Jun 2020 17:54:51 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 3/6] dt-bindings: PCI: uniphier: Add iATU register description Date: Wed, 3 Jun 2020 17:54:38 +0900 Message-Id: <1591174481-13975-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org In the dt-bindings, "atu" reg-names is required to get the register space for iATU in Synopsys DWC version 4.80 or later. Signed-off-by: Kunihiko Hayashi Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/uniphier-pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt index 1fa2c59..c4b7381 100644 --- a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -16,6 +16,7 @@ Required properties: "dbi" - controller configuration registers "link" - SoC-specific glue layer registers "config" - PCIe configuration space + "atu" - iATU registers for DWC version 4.80 or later - clocks: A phandle to the clock gate for PCIe glue layer including the host controller. - resets: A phandle to the reset line for PCIe glue layer including From patchwork Wed Jun 3 08:54:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585351 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65FB792A for ; Wed, 3 Jun 2020 08:55:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4357620897 for ; Wed, 3 Jun 2020 08:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726337AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from mx.socionext.com ([202.248.49.38]:18844 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726268AbgFCIyy (ORCPT ); Wed, 3 Jun 2020 04:54:54 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:52 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 717B360057; Wed, 3 Jun 2020 17:54:52 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:52 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 108B81A12AD; Wed, 3 Jun 2020 17:54:52 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 4/6] PCI: uniphier: Add iATU register support Date: Wed, 3 Jun 2020 17:54:39 +0900 Message-Id: <1591174481-13975-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This gets iATU register area from reg property. In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index a8dda39..ad14e67 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -447,6 +447,11 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.dbi_base)) return PTR_ERR(priv->pci.dbi_base); + priv->pci.atu_base = + devm_platform_ioremap_resource_byname(pdev, "atu"); + if (IS_ERR(priv->pci.atu_base)) + priv->pci.atu_base = NULL; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); priv->base = devm_ioremap_resource(dev, res); if (IS_ERR(priv->base)) From patchwork Wed Jun 3 08:54:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585345 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2C8CD92A for ; Wed, 3 Jun 2020 08:55:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 15699207ED for ; Wed, 3 Jun 2020 08:55:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726606AbgFCIzK (ORCPT ); Wed, 3 Jun 2020 04:55:10 -0400 Received: from mx.socionext.com ([202.248.49.38]:18835 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726308AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 593DD60057; Wed, 3 Jun 2020 17:54:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:53 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id B3EA61A12AD; Wed, 3 Jun 2020 17:54:52 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 5/6] PCI: uniphier: Add error message when failed to get phy Date: Wed, 3 Jun 2020 17:54:40 +0900 Message-Id: <1591174481-13975-6-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Even if phy driver doesn't probe, the error message can't be distinguished from other errors. This displays error message caused by the phy driver explicitly. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index ad14e67..3b51561 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -466,8 +466,12 @@ static int uniphier_pcie_probe(struct platform_device *pdev) return PTR_ERR(priv->rst); priv->phy = devm_phy_optional_get(dev, "pcie-phy"); - if (IS_ERR(priv->phy)) - return PTR_ERR(priv->phy); + if (IS_ERR(priv->phy)) { + ret = PTR_ERR(priv->phy); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get phy (%d)\n", ret); + return ret; + } platform_set_drvdata(pdev, priv); From patchwork Wed Jun 3 08:54:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11585343 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 897CE618 for ; Wed, 3 Jun 2020 08:55:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F336207DF for ; Wed, 3 Jun 2020 08:55:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726563AbgFCIzJ (ORCPT ); Wed, 3 Jun 2020 04:55:09 -0400 Received: from mx.socionext.com ([202.248.49.38]:18852 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726312AbgFCIyz (ORCPT ); Wed, 3 Jun 2020 04:54:55 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 03 Jun 2020 17:54:53 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 02E8860057; Wed, 3 Jun 2020 17:54:54 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 3 Jun 2020 17:54:54 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 616C01A12AD; Wed, 3 Jun 2020 17:54:53 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 6/6] PCI: uniphier: Use devm_platform_ioremap_resource_byname() Date: Wed, 3 Jun 2020 17:54:41 +0900 Message-Id: <1591174481-13975-7-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1591174481-13975-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Use devm_platform_ioremap_resource_byname() to simplify the code a bit. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-uniphier.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index 3b51561..ce47622 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -452,8 +452,7 @@ static int uniphier_pcie_probe(struct platform_device *pdev) if (IS_ERR(priv->pci.atu_base)) priv->pci.atu_base = NULL; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "link"); - priv->base = devm_ioremap_resource(dev, res); + priv->base = devm_platform_ioremap_resource_byname(pdev, "link"); if (IS_ERR(priv->base)) return PTR_ERR(priv->base);