From patchwork Fri Jun 5 00:23:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 11588823 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 874F4618 for ; Fri, 5 Jun 2020 00:24:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 64ADB206DC for ; Fri, 5 Jun 2020 00:24:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 64ADB206DC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C65926E405; Fri, 5 Jun 2020 00:24:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id ABB826E405 for ; Fri, 5 Jun 2020 00:24:26 +0000 (UTC) IronPort-SDR: 3UBtqNjAd0Iq2gRpZsmo1/u5jh/CSKSj9jUfljNwdkmnJTh/gU0s1JYvdGh1CXzCP3EZzFsnNn 516UThmZNjwA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2020 17:24:25 -0700 IronPort-SDR: 1rCQZFydX278h3CGMqkpf/b7do1O+6t+SW3u4h/AORN36UGSi/e9/bhe63RZ8K39eI7LXfOiT6 HN6O2jeo4VTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,474,1583222400"; d="scan'208";a="378580615" Received: from helsinki.fi.intel.com ([10.237.66.162]) by fmsmga001.fm.intel.com with ESMTP; 04 Jun 2020 17:24:23 -0700 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Fri, 5 Jun 2020 03:23:50 +0300 Message-Id: <20200605002350.151449-1-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.25.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/psr: Program default IO buffer Wake and Fast Wake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The IO buffer Wake and Fast Wake bit size and value have been changed from Gen12+. It programs default value of IO buffer Wake and Fast Wake on Gen12+. - Pre Gen12 Bit location: IO buffer Wake: Register_PSR2_CTL[14:13] Fast Wake: Register_PSR2_CTL[12:11] Value: 0x0: 8 lines 0x1: 7 lines 0x2: 6 lines 0x3: 5 lines - Gen12+ Bit location: IO buffer Wake: Register_PSR2_CTL[15:13] Fast Wake: Register_PSR2_CTL[12:10] Value: 0x0: 5 lines 0x1: 6 lines 0x2: 7 lines 0x3: 8 lines 0x4: 9 lines 0x5: 10 lines 0x6: 11 lines 0x7: 12 lines Cc: José Roberto de Souza Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b7a2c102648a..de2a17fe8860 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -518,6 +518,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) else val |= EDP_PSR2_TP2_TIME_2500us; + if (INTEL_GEN(dev_priv) >= 12) { + /* + * TODO: In order to setting an optimal power consumption, + * lower than 4k resoluition mode needs to decrese IO_BUFFER_WAKE + * and FAST_WAKE. And higher than 4K resolution mode needs + * to increase IO_BUFFER_WAKE and FAST_WAKE. + */ + u32 io_buffer_wake = 0x2; /* default BSpec value, 7 lines */ + u32 fast_wake = 0x2; /* default BSpec value, 7 lines */ + + /* + * To program line 9 to 12 on IO_BUFFER_WAKE and FAST_WAKE, + * EDP_PSR2_CTL should be set EDP_PSR2_BLOCK_COUNT_NUM_3. + */ + val |= EDP_PSR2_BLOCK_COUNT_NUM_2; + val |= EDP_PSR2_IO_BUFFER_WAKE(io_buffer_wake); + val |= EDP_PSR2_FAST_WAKE(fast_wake); + } + /* * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 96d351fbeebb..d055b7d93a5d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4514,10 +4514,16 @@ enum { #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) #define EDP_PSR2_ENABLE (1 << 31) #define EDP_SU_TRACK_ENABLE (1 << 30) +#define EDP_PSR2_BLOCK_COUNT_NUM_2 (0 << 28) /* TGL+ */ +#define EDP_PSR2_BLOCK_COUNT_NUM_3 (1 << 28) /* TGL+ */ #define EDP_Y_COORDINATE_VALID (1 << 26) /* GLK and CNL+ */ #define EDP_Y_COORDINATE_ENABLE (1 << 25) /* GLK and CNL+ */ #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) +#define EDP_PSR2_IO_BUFFER_WAKE(a) ((a) << 13) +#define EDP_PSR2_IO_BUFFER_WAKE_MASK (0x7 << 13) /* TGL+ */ +#define EDP_PSR2_FAST_WAKE(a) ((a) << 10) /* TGL+ */ +#define EDP_PSR2_FAST_WAKE_MASK (0x7 << 10) /* TGL+ */ #define EDP_PSR2_TP2_TIME_500us (0 << 8) #define EDP_PSR2_TP2_TIME_100us (1 << 8) #define EDP_PSR2_TP2_TIME_2500us (2 << 8)