From patchwork Fri Jun 5 09:11:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 11589227 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 827F692A for ; Fri, 5 Jun 2020 09:11:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A5AD207F5 for ; Fri, 5 Jun 2020 09:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726274AbgFEJL1 (ORCPT ); Fri, 5 Jun 2020 05:11:27 -0400 Received: from mail.loongson.cn ([114.242.206.163]:51162 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726062AbgFEJLZ (ORCPT ); Fri, 5 Jun 2020 05:11:25 -0400 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxXesqDNpeHOw9AA--.611S2; Fri, 05 Jun 2020 17:11:06 +0800 (CST) From: Bibo Mao To: Thomas Bogendoerfer , Andrew Morton , Paul Burton , Jiaxun Yang Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org Subject: [PATCH 1/2] MIPS: set page access bit with pgprot on some MIPS platform Date: Fri, 5 Jun 2020 17:11:05 +0800 Message-Id: <1591348266-28392-1-git-send-email-maobibo@loongson.cn> X-Mailer: git-send-email 1.8.3.1 X-CM-TRANSID: AQAAf9DxXesqDNpeHOw9AA--.611S2 X-Coremail-Antispam: 1UD129KBjvJXoW3WF43GF1UtFyfKFy5tF48tFb_yoWxZrW3pF 97A34xArW2qry3AryxurnrAa1rCwsrtFWUJw17C3W8Z3y7XrykKrnrCa97ZrykuFWvva18 Aa1UXr4UWayIvFUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk0b7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r4j6ryUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwV C2z280aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC 0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr 1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxkIecxEwVCm-wCF04k20xvY 0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I 0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAI cVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcV CF04k26cxKx2IYs7xG6rW3Jr0E3s1lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280 aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUqEoXUUUUU X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On MIPS system which has rixi hardware bit, page access bit is not set in pgrot. For memory reading, there will be one page fault to allocate physical page; however valid bit is not set, there will be the second fast tlb-miss fault handling to set valid/access bit. This patch set page access/valid bit with pgrot if there is reading access privilege. It will reduce one tlb-miss handling for memory reading access. The valid/access bit will be cleared in order to track memory accessing activity. If the page is accessed, tlb-miss fast handling will set valid/access bit, pte_sw_mkyoung is not necessary in slow page fault path. This patch removes pte_sw_mkyoung function which is defined as empty function except MIPS system. Signed-off-by: Bibo Mao Acked-by: Andrew Morton --- arch/mips/include/asm/pgtable.h | 11 +++++++++-- arch/mips/mm/cache.c | 34 +++++++++++++++++----------------- include/asm-generic/pgtable.h | 16 ---------------- mm/memory.c | 3 --- 4 files changed, 26 insertions(+), 38 deletions(-) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 85b39c9..e2452ab 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -25,6 +25,15 @@ struct mm_struct; struct vm_area_struct; +#define __PP _PAGE_PRESENT +#define __NX _PAGE_NO_EXEC +#define __NR _PAGE_NO_READ +#define ___W _PAGE_WRITE +#define ___A _PAGE_ACCESSED +#define ___R (_PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __PC _page_cachable_default + + #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_NO_READ | \ _page_cachable_default) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | \ @@ -414,8 +423,6 @@ static inline pte_t pte_mkyoung(pte_t pte) return pte; } -#define pte_sw_mkyoung pte_mkyoung - #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; } diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index ad6df1c..f814e43 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -158,23 +158,23 @@ void __update_cache(unsigned long address, pte_t pte) static inline void setup_protection_map(void) { if (cpu_has_rixi) { - protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - - protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); - protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); - protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); - protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); - protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); - protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); - protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); + protection_map[0] = __pgprot(__PC | __PP | __NX | __NR); + protection_map[1] = __pgprot(__PC | __PP | __NX | ___R); + protection_map[2] = __pgprot(__PC | __PP | __NX | __NR); + protection_map[3] = __pgprot(__PC | __PP | __NX | ___R); + protection_map[4] = __pgprot(__PC | __PP | ___R); + protection_map[5] = __pgprot(__PC | __PP | ___R); + protection_map[6] = __pgprot(__PC | __PP | ___R); + protection_map[7] = __pgprot(__PC | __PP | ___R); + + protection_map[8] = __pgprot(__PC | __PP | __NX | __NR); + protection_map[9] = __pgprot(__PC | __PP | __NX | ___R); + protection_map[10] = __pgprot(__PC | __PP | __NX | ___W | __NR); + protection_map[11] = __pgprot(__PC | __PP | __NX | ___W | ___R); + protection_map[12] = __pgprot(__PC | __PP | ___R); + protection_map[13] = __pgprot(__PC | __PP | ___R); + protection_map[14] = __pgprot(__PC | __PP | ___W | ___R); + protection_map[15] = __pgprot(__PC | __PP | ___W | ___R); } else { protection_map[0] = PAGE_NONE; diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index b5278ec..fa5c73f 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -244,22 +244,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres } #endif -/* - * On some architectures hardware does not set page access bit when accessing - * memory page, it is responsibilty of software setting this bit. It brings - * out extra page fault penalty to track page access bit. For optimization page - * access bit can be set during all page fault flow on these arches. - * To be differentiate with macro pte_mkyoung, this macro is used on platforms - * where software maintains page access bit. - */ -#ifndef pte_sw_mkyoung -static inline pte_t pte_sw_mkyoung(pte_t pte) -{ - return pte; -} -#define pte_sw_mkyoung pte_sw_mkyoung -#endif - #ifndef pte_savedwrite #define pte_savedwrite pte_write #endif diff --git a/mm/memory.c b/mm/memory.c index c7c8960..8bb31c4 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -2704,7 +2704,6 @@ static vm_fault_t wp_page_copy(struct vm_fault *vmf) } flush_cache_page(vma, vmf->address, pte_pfn(vmf->orig_pte)); entry = mk_pte(new_page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); entry = maybe_mkwrite(pte_mkdirty(entry), vma); /* * Clear the pte entry and flush it first, before updating the @@ -3379,7 +3378,6 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) __SetPageUptodate(page); entry = mk_pte(page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); if (vma->vm_flags & VM_WRITE) entry = pte_mkwrite(pte_mkdirty(entry)); @@ -3662,7 +3660,6 @@ vm_fault_t alloc_set_pte(struct vm_fault *vmf, struct mem_cgroup *memcg, flush_icache_page(vma, page); entry = mk_pte(page, vma->vm_page_prot); - entry = pte_sw_mkyoung(entry); if (write) entry = maybe_mkwrite(pte_mkdirty(entry), vma); /* copy-on-write page */ From patchwork Fri Jun 5 09:11:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 11589229 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19C12159A for ; Fri, 5 Jun 2020 09:11:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09BE82075B for ; Fri, 5 Jun 2020 09:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726265AbgFEJL1 (ORCPT ); Fri, 5 Jun 2020 05:11:27 -0400 Received: from mail.loongson.cn ([114.242.206.163]:51160 "EHLO loongson.cn" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726261AbgFEJLZ (ORCPT ); Fri, 5 Jun 2020 05:11:25 -0400 Received: from kvm-dev1.localdomain (unknown [10.2.5.134]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9DxXesqDNpeHOw9AA--.611S3; Fri, 05 Jun 2020 17:11:07 +0800 (CST) From: Bibo Mao To: Thomas Bogendoerfer , Andrew Morton , Paul Burton , Jiaxun Yang Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org Subject: [PATCH 2/2] MIPS: Add writable-applies-readable policy with pgrot Date: Fri, 5 Jun 2020 17:11:06 +0800 Message-Id: <1591348266-28392-2-git-send-email-maobibo@loongson.cn> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1591348266-28392-1-git-send-email-maobibo@loongson.cn> References: <1591348266-28392-1-git-send-email-maobibo@loongson.cn> X-CM-TRANSID: AQAAf9DxXesqDNpeHOw9AA--.611S3 X-Coremail-Antispam: 1UD129KBjvJXoW7tr1fJryDXF1xAF4rGr45Wrg_yoW8Gw45pF 9rA343JrWqgFy0yryUuFWrGayUGr4Dta47Jw17WF1xAws8Xw18KF93KF92qryruFsava10 y3WxWr48JayxAFUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9Eb7Iv0xC_KF4lb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv 6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c 02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE 4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc2xSY4AK6svPMxAIw28IcxkI7VAKI4 8JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xv wVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjx v20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20E Y4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267 AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8Q_-PUUUUU== X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Linux system, writable applies readable privilege in most architectures, this patch adds this policy on MIPS platform where hardware rixi is supported. Signed-off-by: Bibo Mao --- arch/mips/mm/cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index f814e43..dae0617 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -160,7 +160,7 @@ static inline void setup_protection_map(void) if (cpu_has_rixi) { protection_map[0] = __pgprot(__PC | __PP | __NX | __NR); protection_map[1] = __pgprot(__PC | __PP | __NX | ___R); - protection_map[2] = __pgprot(__PC | __PP | __NX | __NR); + protection_map[2] = __pgprot(__PC | __PP | __NX | ___R); protection_map[3] = __pgprot(__PC | __PP | __NX | ___R); protection_map[4] = __pgprot(__PC | __PP | ___R); protection_map[5] = __pgprot(__PC | __PP | ___R); @@ -169,7 +169,7 @@ static inline void setup_protection_map(void) protection_map[8] = __pgprot(__PC | __PP | __NX | __NR); protection_map[9] = __pgprot(__PC | __PP | __NX | ___R); - protection_map[10] = __pgprot(__PC | __PP | __NX | ___W | __NR); + protection_map[10] = __pgprot(__PC | __PP | __NX | ___W | ___R); protection_map[11] = __pgprot(__PC | __PP | __NX | ___W | ___R); protection_map[12] = __pgprot(__PC | __PP | ___R); protection_map[13] = __pgprot(__PC | __PP | ___R);