From patchwork Fri Jun 5 09:35:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Sm9obnNvbiBDSCBDaGVuICjpmbPmmK3li7Mp?= X-Patchwork-Id: 11589271 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D981C175A for ; Fri, 5 Jun 2020 09:35:44 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B41C2207D3 for ; Fri, 5 Jun 2020 09:35:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="UPgKcBKO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B41C2207D3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=moxa.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+4722+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id siYFYY4521763xq6C2fkd7wh; Fri, 05 Jun 2020 02:35:44 -0700 X-Received: from APC01-PU1-obe.outbound.protection.outlook.com (APC01-PU1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web10.7257.1591349742430264239 for ; Fri, 05 Jun 2020 02:35:44 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LynztU/u07JSURM6GaYxkoJL8PLmjNMPsOSym4lCzreMluwOKbzHpj4/bgH7CiW2VIVdTRzw+rbbXFS1arFZ18V+2Y9ZUxsJv4jXE/1OhYyOyqgNzSDhXb6Lt/3FXYw2UkE38DiMrfQWLSadt0YWydO8ISaJOzT79yBCz/U46dHoXsXR3N0VHu2Kx4O8mvXY3hM6kWEGhPlgYk5xaTdHa17mZPaiKcHQQN9rIFUGBNCm4DjiQUiBcwlnQ3HLwfPvBpfU0jKL3rXMrf7QKcOsq1S2kNVWECHCBFReHldjBMJiauvuDWIegFPiJ+4ttbatY8sQYWpdNEREObwrUO3AEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+3/agXVD2QJrJ0YOKTyQtSIeiVOVBl297/dTLpolViE=; b=BrGRg9fiubPrC1ukqhujXs++Rk9hIBVcOiDh+SA1/MRD7LCP8YvvIJ0phQBbtxq1DYXxK7raN5WrnL7AyAJ/0ESz8gO3NA8nuA2+OJrXhq7h54Q0jv0oHl6EuEhfhTaN8wPKF/0uRCWZHdcw2/Ikbvg57ta0xvB3JUa1X5DglBDn36Dz/IMCQV778e+hzGQKIBy9bcKn/WqgHy8jK3AREC8RqayhxSRraHSIVXQrCtP+76+ikJgcZkUo1asePFewOJW8kC6rRPxI9ORMTe603kY3zvIFnKmOGiAhC8H3KZaD4GkAXhLhGOo6P0JnnCYULhiE0NQ9oYje25UxGqZHNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=moxa.com; dmarc=pass action=none header.from=moxa.com; dkim=pass header.d=moxa.com; arc=none X-Received: from HK2PR01MB3281.apcprd01.prod.exchangelabs.com (2603:1096:202:22::12) by HK2PR01MB3140.apcprd01.prod.exchangelabs.com (2603:1096:202:18::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.18; Fri, 5 Jun 2020 09:35:41 +0000 X-Received: from HK2PR01MB3281.apcprd01.prod.exchangelabs.com ([fe80::712b:170d:f873:68a3]) by HK2PR01MB3281.apcprd01.prod.exchangelabs.com ([fe80::712b:170d:f873:68a3%6]) with mapi id 15.20.3066.018; Fri, 5 Jun 2020 09:35:41 +0000 From: "johnsonch.chen@moxa.com" To: "nobuhiro1.iwamatsu@toshiba.co.jp" , "pavel@denx.de" , "cip-dev@lists.cip-project.org" Subject: [cip-dev][PATCH 4.4.y-cip 1/2] ARM: DTS: am33xx: Use the new DT bindings for the eDMA3 Thread-Topic: [cip-dev][PATCH 4.4.y-cip 1/2] ARM: DTS: am33xx: Use the new DT bindings for the eDMA3 Thread-Index: AdY7G8WKfCaPk2RlSCampVV/E3SVxA== Date: Fri, 5 Jun 2020 09:35:41 +0000 Message-ID: Accept-Language: zh-TW, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [123.51.145.16] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1a7c2451-78b8-454c-8a6e-08d80933d07b x-ms-traffictypediagnostic: HK2PR01MB3140: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1148; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dX1kzC/OwxDY7NQm4OH5zH1bLqYFYc2xoBvchkhaRFI90z/WkPsUTGxUoBjhaw4xQByY4eBtSHTeN8Oa2LAu5wog0kuPRnE0M2CLczdfWUaH8zJt6xXn76zg/USpREYkiGXnMjplE5ttDJEJG3VUYCk4FKIAaq0YUE9sTP268BD9bSp+ekCr/ccjTUOmk3f8u+IA80dUwjBY8eKTcCMLi5cx4/nHvEpgoWT+Jef3MirKbSDyDhDPMVQFOTc7zbsK2CgeWgl9s9h0Ud/qyamvixHjT9m9O9RTXOQXIz0ckBWJPeB4HxvNaGk0Cy6Ql2tKklV6rGH12WzDf+fudwfglw== x-ms-exchange-antispam-messagedata: WF2QrzYGYT5+bpaHtOczmJiE6XISlvyFtD0BgmkFRxBK8ZtRJ64dW9ha7oj6ZNzA47n6emcS+t/s+5nwa4ViY1JsdwMFlTd2DNgtIFuk9RyifA7WwC8W+ilzqE9AtEQsoo2V0sCvIgWnCiQYu99qKf5znBTucFaaMi/fxWDqCJMfLRbmaCckMhrH0IpiUcgkYl0cl8VBmqpVjo0o2CcBNjDOpzTmFK7bEuZiXUNas6Yl5fCkgvzfemQoAfbyxWeF8A+5s6xGDsJRBS18Cw2IfJSTwOGllSANLDWxkeGNWIUoN/O0oaRSK0F0dwwBKzQjrOs2ExZJZSPJnzhvWjouc+Zm8b3EK80E5ZoCmUGi6SOazHGf35Ya39kEU0zDhbMV0RUirhJjbMRdSY4mYvXg6FMaU7/jp+ATEPB+rFk80NBTe0gMu7qwzFb10xIdJmJKUWtI5j81mivWlkUGOXQH6tbS4UtjO7KdjgqUgPlYRTo= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: moxa.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a7c2451-78b8-454c-8a6e-08d80933d07b X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2020 09:35:41.7655 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5571c7d4-286b-47f6-9dd5-0aa688773c8e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fLN5/LmDdHpBlHBJ50BafXeasp6tVLNvIcOdACDSmnH1LBAkIsBv3pJBcP6uPadvFjiQFnaFcGLl/UZaw1dl1Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR01MB3140 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: 7etEibiAd5YJ4BR7NYAOmobEx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1591349744; bh=mEkNyIUzk4ztggNE34DBvNylKjhbaAg3nH4TlANIyhI=; h=Content-Type:Date:From:Reply-To:Subject:To; b=UPgKcBKOfE530bUSsnXLYLmHXniXAaDnk6lRQMem5AefwTzVkofnZ6Ry5MjzAtVqcOy PaTkmJEFNtEhPxjG0ismzkgoZ5cVlPJaXWbfJv1j7kAfzE+Opti2Rq8A5O0tHippnHX5g /BnaHxUaTIgVyVYZfHNNLQi6mEhV6xZqrnM= From: Peter Ujfalusi commit b5e5090660742c838ddc0b5d1a001e6fe3d5bfd5 upstream. Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3 and enable the DMA even crossbar with ti,am335x-edma-crossbar. With the new bindings boards can customize and tweak the DMA channel priority to match their needs. With the new binding the memcpy is safe to be used since with the old binding it was not possible for a driver to know which channel is allowed to be used as non HW triggered channel. Signed-off-by: Peter Ujfalusi Signed-off-by: Tony Lindgren Signed-off-by: Johnson Chen --- arch/arm/boot/dts/am335x-evm.dts | 9 +--- arch/arm/boot/dts/am335x-pepper.dts | 11 +---- arch/arm/boot/dts/am33xx.dtsi | 94 ++++++++++++++++++++++++++----------- 3 files changed, 71 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 2b8614e406f0..656d4304ab6b 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -743,8 +743,8 @@ &mmc3 { /* these are on the crossbar and are outlined in the xbar-event-map element */ - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; status = "okay"; vmmc-supply = <&wlan_en_reg>; @@ -766,11 +766,6 @@ }; }; -&edma { - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 7106114c7464..39073b921664 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -339,13 +339,6 @@ ti,non-removable; }; -&edma { - /* Map eDMA MMC2 Events from Crossbar */ - ti,edma-xbar-event-map = /bits/ 16 <1 12 - 2 13>; -}; - - &mmc3 { /* Wifi & Bluetooth on MMC #3 */ status = "okay"; @@ -354,8 +347,8 @@ vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; ti,non-removable; - dmas = <&edma 12 - &edma 13>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; dma-names = "tx", "rx"; }; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index be9c37e89be1..4b40e6d401a0 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -162,6 +162,14 @@ mboxes = <&mailbox &mbox_wkupm3>; }; + edma_xbar: dma-router@f90 { + compatible = "ti,am335x-edma-crossbar"; + reg = <0xf90 0x40>; + #dma-cells = <3>; + dma-requests = <32>; + dma-masters = <&edma>; + }; + scm_clockdomains: clockdomains { }; }; @@ -175,12 +183,44 @@ }; edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x49000000 0x10000>; + reg-names = "edma3_cc"; interrupts = <12 13 14>; - #dma-cells = <1>; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, + <&edma_tptc2 0>; + + ti,edma-memcpy-channels = <20 21>; + }; + + edma_tptc0: tptc@49800000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x49800000 0x100000>; + interrupts = <112>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@49900000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x49900000 0x100000>; + interrupts = <113>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc2: tptc@49a00000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc2"; + reg = <0x49a00000 0x100000>; + interrupts = <114>; + interrupt-names = "edma3_tcerrint"; }; gpio0: gpio@44e07000 { @@ -234,7 +274,7 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; - dmas = <&edma 26>, <&edma 27>; + dmas = <&edma 26 0>, <&edma 27 0>; dma-names = "tx", "rx"; }; @@ -245,7 +285,7 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; - dmas = <&edma 28>, <&edma 29>; + dmas = <&edma 28 0>, <&edma 29 0>; dma-names = "tx", "rx"; }; @@ -256,7 +296,7 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; - dmas = <&edma 30>, <&edma 31>; + dmas = <&edma 30 0>, <&edma 31 0>; dma-names = "tx", "rx"; }; @@ -323,8 +363,8 @@ ti,dual-volt; ti,needs-special-reset; ti,needs-special-hs-handling; - dmas = <&edma 24 - &edma 25>; + dmas = <&edma_xbar 24 0 0 + &edma_xbar 25 0 0>; dma-names = "tx", "rx"; interrupts = <64>; interrupt-parent = <&intc>; @@ -336,8 +376,8 @@ compatible = "ti,omap4-hsmmc"; ti,hwmods = "mmc2"; ti,needs-special-reset; - dmas = <&edma 2 - &edma 3>; + dmas = <&edma 2 0 + &edma 3 0>; dma-names = "tx", "rx"; interrupts = <28>; interrupt-parent = <&intc>; @@ -475,10 +515,10 @@ interrupts = <65>; ti,spi-num-cs = <2>; ti,hwmods = "spi0"; - dmas = <&edma 16 - &edma 17 - &edma 18 - &edma 19>; + dmas = <&edma 16 0 + &edma 17 0 + &edma 18 0 + &edma 19 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -491,10 +531,10 @@ interrupts = <125>; ti,spi-num-cs = <2>; ti,hwmods = "spi1"; - dmas = <&edma 42 - &edma 43 - &edma 44 - &edma 45>; + dmas = <&edma 42 0 + &edma 43 0 + &edma 44 0 + &edma 45 0>; dma-names = "tx0", "rx0", "tx1", "rx1"; status = "disabled"; }; @@ -832,7 +872,7 @@ ti,hwmods = "sham"; reg = <0x53100000 0x200>; interrupts = <109>; - dmas = <&edma 36>; + dmas = <&edma 36 0>; dma-names = "rx"; }; @@ -841,8 +881,8 @@ ti,hwmods = "aes"; reg = <0x53500000 0xa0>; interrupts = <103>; - dmas = <&edma 6>, - <&edma 5>; + dmas = <&edma 6 0>, + <&edma 5 0>; dma-names = "tx", "rx"; }; @@ -855,8 +895,8 @@ interrupts = <80>, <81>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 8>, - <&edma 9>; + dmas = <&edma 8 2>, + <&edma 9 2>; dma-names = "tx", "rx"; }; @@ -869,8 +909,8 @@ interrupts = <82>, <83>; interrupt-names = "tx", "rx"; status = "disabled"; - dmas = <&edma 10>, - <&edma 11>; + dmas = <&edma 10 2>, + <&edma 11 2>; dma-names = "tx", "rx"; }; From patchwork Fri Jun 5 09:35:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Sm9obnNvbiBDSCBDaGVuICjpmbPmmK3li7Mp?= X-Patchwork-Id: 11589273 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 144E2159A for ; Fri, 5 Jun 2020 09:35:48 +0000 (UTC) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E1EBE206A2 for ; Fri, 5 Jun 2020 09:35:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=lists.cip-project.org header.i=@lists.cip-project.org header.b="T9J70cZ7" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E1EBE206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=moxa.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=bounce+64572+4723+4520428+8129116@lists.cip-project.org X-Received: by 127.0.0.2 with SMTP id A4svYY4521763xLNvR7MNXH1; Fri, 05 Jun 2020 02:35:47 -0700 X-Received: from APC01-PU1-obe.outbound.protection.outlook.com (APC01-PU1-obe.outbound.protection.outlook.com [40.107.132.87]) by mx.groups.io with SMTP id smtpd.web12.7399.1591349746598968140 for ; Fri, 05 Jun 2020 02:35:47 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PAjfOnuZ3cTNXXMp0lCKpxyw9h4HKUgV+PuU+UoEhgMNDIIS9gNw1PIJTcSsHLIq0m8qP6ORiFvYdGqGG6RQ34Ee6SocKqPTh+FBg3sknflaChYqccjQk8//FVBwd5/qErFeVEtA94RqE0cR4z+wVaTrSwISN4OyLDgHSY2kF9jbFA/35cvYFY54ao6M2zgN93U7nnNiQcdHMfJ6LBc00RAo1FDD3tIq2FwkE96Sj0Wx41MY0g37AES50HuDFxxmcpTkLsQPDNRPnz2zU0EVESb7WYwCn+LBXoL2mBn+HA+S78y1JHgkpX+W5LqUzoO8vh7Gv39ayfNC0+91wWYadA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hzPNlrv+dSLxLvc6Bc+ioVfFo2tT+XiaI4PyacbzRVk=; b=lq+UpZqDrrpy5Htk+TdIqUEcskT0Ytr+p6O3pvlXdyl7pmylRqtfuaMRa4alp8sHvWIQ+lQV+QG4u/VnPUYECv9KimMp7iUTI9misyTpcgtPB7IcnTEQIPkgDPQKveITSTpgMBd2xCc7DhbBQPYEwj5CAr4BInsUUoc0p/+hkiBVOu08yasZSzN6dDlbkj4D+HJD72AbapzTl5lURPfa9QT8ce5/Q5/YTairHpmd9N+Jdrpeg0wXPztHefNwKRB53xN6eD71md83ZyszjnuB+e1e+GWUd9JU6iTqZXK8g8GYm73VMWFB8oh216xTqH5P1yhc0r0OKvuEgO9Y2uM7ng== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=moxa.com; dmarc=pass action=none header.from=moxa.com; dkim=pass header.d=moxa.com; arc=none X-Received: from HK2PR01MB3281.apcprd01.prod.exchangelabs.com (2603:1096:202:22::12) by HK2PR01MB3140.apcprd01.prod.exchangelabs.com (2603:1096:202:18::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3066.18; Fri, 5 Jun 2020 09:35:44 +0000 X-Received: from HK2PR01MB3281.apcprd01.prod.exchangelabs.com ([fe80::712b:170d:f873:68a3]) by HK2PR01MB3281.apcprd01.prod.exchangelabs.com ([fe80::712b:170d:f873:68a3%6]) with mapi id 15.20.3066.018; Fri, 5 Jun 2020 09:35:44 +0000 From: "johnsonch.chen@moxa.com" To: "nobuhiro1.iwamatsu@toshiba.co.jp" , "pavel@denx.de" , "cip-dev@lists.cip-project.org" Subject: [cip-dev][PATCH 4.4.y-cip 2/2] ARM: dts: am335x: add support for Moxa UC-8100-ME-T open platform Thread-Topic: [cip-dev][PATCH 4.4.y-cip 2/2] ARM: dts: am335x: add support for Moxa UC-8100-ME-T open platform Thread-Index: AdY7G9dCWw5GJ5BuQvOUo7cRN56WKQ== Date: Fri, 5 Jun 2020 09:35:44 +0000 Message-ID: Accept-Language: zh-TW, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [123.51.145.16] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 85240697-ce44-45f1-9b01-08d80933d230 x-ms-traffictypediagnostic: HK2PR01MB3140: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:229; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: o6nOFTry3SLM1RLdyivwmwsCfqa7URnMs/Zf8Qdt/RwewB5a6lsFEAJ7Nj7h88l4J95A0uVRgGnuIPijIG1OFbTIEDZj8DkVJHUPlfYzVORIbwnvHwbl1KzYiH49bPVs5JDc7uwz4v4DhMMDbvhuwEq1i4rYe+S8ir6H382UIWKep4BIXRrufKJd8ajz5rKR6zgO6zNtg6JcfR1QzN38c/9TRzfhbw2gOQu9l55PhJ+Y5jkMX9jDYO2HwSfjAZl2XiUk2kP0mufoSfD4mGyvCVBVdFegVrahXryryZmhSOMvUFmdSLuTBgmRRrHqYanfGoYCmdcdILqe6boCgLposdi1NKNJib+vyPFj/w7Dh81Xk1Qqk5OVh/Td1i8n4ItKqPg9QCHZ4bnIsUtLT8BXCP0CUyn65SEUgZUDCsaLUUQ0wxQvIsVVyZuJOQZCzY82l9Jo+dpe4IBThj2XHO9Rsg== x-ms-exchange-antispam-messagedata: QPPLujizZWrVGj2aQKyu5rGphv4NYFr5UoR3AWY6F+kNLQ9+Y3IqgMy1fxaqoNnXh/FpNbGIEzQVMNfRMvKywe4EM0lllQPvErphbGLBcSvCM1v94gYjKvt0hwpStQTbIedCAaun4LkuvuiefSWlgN7k8oRwfhKTB5RNeDWCkT28WoDpBl+/fmlGlbaOGnsOZ2EiUbFG5mrLn8Q1yMOTpSVIOL5QZWlTYiWYvhiZPIlJiLkk5R7VwXa63LJDWpxoUt+U9SPa56bSssl2r+Zu8q/MivBWPccAxy862dol24xWk0Fwjq2Ct2XTP0ehkhE+2F3YNcmgUkm+ILqw7ezd/M2649Icso+yMfgsuMeV0pW6Do3FDbyKKQo77hhmL3D9lsNDtOW7axLqHRsC+gNUVvFfwsGyTexXz3h/6IKqCvTLBylq4xOy9UTfIuvqcB5UyGJPPoOy7p9ZHQztE4peEyiq4G7f53mZbzdlPbc5RDE= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: moxa.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85240697-ce44-45f1-9b01-08d80933d230 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jun 2020 09:35:44.5958 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 5571c7d4-286b-47f6-9dd5-0aa688773c8e X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3JluTsIzXGI1OW0jum51ievXuqSKj41HMXq8LhiElKjoJz1z/+8r3IJk+oDQpo0gT5fpv4RNRfrSL3sozULcYQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2PR01MB3140 Precedence: Bulk List-Unsubscribe: Sender: cip-dev@lists.cip-project.org List-Id: Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Delivered-To: mailing list cip-dev@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org X-Gm-Message-State: L5qEO0QmOOYgww9thYGtth1Hx4520428AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.cip-project.org; q=dns/txt; s=20140610; t=1591349747; bh=tGhstipK7raOOYvUaviiZ2dLtdMl1XjSyGb/aNdMAvM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=T9J70cZ7KP4c8a8erR/dWpKsHAJytrrasS2R90OFKWLTZ8JKTIV7SLNmFQ6dog1FeGH MgFlnWqyrowcunHp1zQw21Pk9ak9hiJDmUtCLNaOpmoWH539J6HUPh/25paEjqvjfc0uG D2rB2w3ubdCfxM8WBelf/YxY8KV94L+zyGY= From: SZ Lin commit 5e452865954fe3f18a89cb7bce8c3216636b311d upstream. Add support for Moxa UC-8100-ME-T open platform The UC-8100-ME-T computing platform is designed for embedded data acquisition industrial applications The features of UC-8100-ME-T series are: * eMMC * SPI flash * SD slot * 2x LAN * 2 RS-232/422/485 ports, software-selectable * Mini PCIe form factor with USB signal * USB host * EEPROM * TPM * Watchdog * RTC * User gpio-keys * User LEDs * User button Signed-off-by: SZ Lin Acked-by: Rob Herring [tony@atomide.com: fix unit adress as suggested by Rob] Signed-off-by: Tony Lindgren [Johnson: add string vendor "infineon"] Signed-off-by: Johnson Chen --- .../devicetree/bindings/arm/omap/omap.txt | 3 + .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 525 +++++++++++++++++++++ 4 files changed, 530 insertions(+) create mode 100644 arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 12af302bca6a..a19b92f4dab0 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -139,6 +139,9 @@ Boards: - AM335X phyBOARD-WEGA: Single Board Computer dev kit compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx" +- AM335X UC-8100-ME-T: Communication-centric industrial computing platform + compatible = "moxa,uc-8100-me-t", "ti,am33xx"; + - OMAP5 EVM : Evaluation Module compatible = "ti,omap5-evm", "ti,omap5" diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 12e4560d1c23..7c1ffa49d804 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -113,6 +113,7 @@ ibm International Business Machines (IBM) idt Integrated Device Technologies, Inc. iom Iomega Corporation img Imagination Technologies Ltd. +infineon Infineon Technologies ingenic Ingenic Semiconductor innolux Innolux Corporation intel Intel Corporation diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 147c66b6c213..84f8bd09d2ce 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -462,6 +462,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-sl50.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ + am335x-moxa-uc-8100-me-t.dtb \ am335x-nano.dtb \ am335x-pepper.dtb \ am335x-lxm.dtb \ diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts new file mode 100644 index 000000000000..f82233cd18e0 --- /dev/null +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -0,0 +1,525 @@ +/* + * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/ + * + * Author: SZ Lin (林上智) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Moxa UC-8100-ME-T"; + compatible = "moxa,uc-8100-me-t", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: vmmcsd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "uc8100me:CEL1"; + gpios = <&gpio_xten 8 0>; + default-state = "off"; + }; + + led2 { + label = "uc8100me:CEL2"; + gpios = <&gpio_xten 9 0>; + default-state = "off"; + }; + + led3 { + label = "uc8100me:CEL3"; + gpios = <&gpio_xten 10 0>; + default-state = "off"; + }; + + led4 { + label = "uc8100me:DIA1"; + gpios = <&gpio_xten 11 0>; + default-state = "off"; + }; + led5 { + label = "uc8100me:DIA2"; + gpios = <&gpio_xten 12 0>; + default-state = "off"; + }; + led6 { + label = "uc8100me:DIA3"; + gpios = <&gpio_xten 13 0>; + default-state = "off"; + }; + led7 { + label = "uc8100me:SD"; + gpios = <&gpio_xten 14 0>; + default-state = "off"; + }; + led8 { + label = "uc8100me:USB"; + gpios = <&gpio_xten 15 0>; + default-state = "off"; + }; + led9 { + label = "uc8100me:USER"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + buttons: push_button { + compatible = "gpio-keys"; + }; + +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins>; + + minipcie_pins: pinmux_minipcie { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2_24 */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ + >; + }; + + push_button_pins: pinmux_push_button { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_ctsn.i2c1_sda */ + AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE3) /* uart0_rtsn.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ + AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE6) /* lcd_data14.uart5_ctsn */ + AM33XX_IOPAD(0x8dc, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* lcd_data15.uart5_rtsn */ + AM33XX_IOPAD(0x8c4, PIN_INPUT_PULLUP | MUX_MODE4) /* lcd_data9.uart5_rxd */ + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE4) /* lcd_data8.uart5_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mii1_refclk.rmii1_refclk */ + + /* Slave 2 */ + AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ + AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ + AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ + + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + mmc0_pins_default: pinmux_mmc0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ + >; + }; + + mmc2_pins_default: pinmux_mmc2_pins { + pinctrl-single,pins = < + /* eMMC */ + AM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x95C, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */ + >; + }; + +}; + +&uart0 { + /* Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* UART 1 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart5 { + /* UART 2 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_wdt: rtc_wdt@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + gpio_xten: gpio_xten@27 { + compatible = "nxp,pca9535"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; +}; + +&cpsw_emac0 { + status = "okay"; + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + status = "okay"; + phy_id = <&davinci_mdio>, <5>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + reg= <0x44e10650 0xf5>; + rmii-clock-ext; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&mmc1 { + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-0 = <&mmc0_pins_default>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-0 = <&mmc2_pins_default>; + ti,non-removable; + status = "okay"; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "push_button"; + linux,code = <0x100>; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + m25p80@0 { + compatible = "mx25l6405d"; + spi-max-frequency = <40000000>; + + reg = <0>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* reg : The partition's offset and size within the mtd bank. */ + partitions@0 { + label = "MLO"; + reg = <0x0 0x80000>; + }; + + partitions@1 { + label = "U-Boot"; + reg = <0x80000 0x100000>; + }; + + partitions@2 { + label = "U-Boot Env"; + reg = <0x180000 0x20000>; + }; + }; +};