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Fri, 12 Oct 2018 02:23:08 +0000 Received: from VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123]) by VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123%3]) with mapi id 15.20.1207.024; Fri, 12 Oct 2018 02:23:08 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "tudor.ambarus@microchip.com" CC: "marek.vasut@gmail.com" , "cyrille.pitchen@wedev4u.fr" , "boris.brezillon@bootlin.com" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash Thread-Topic: [PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash Thread-Index: AQHUYdKDjlmkWwN6/UiXD412Qj9EqQ== Date: Fri, 12 Oct 2018 02:23:08 +0000 Message-ID: <1539310881-17438-2-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0225.apcprd06.prod.outlook.com (2603:1096:4:68::33) To VI1PR04MB1038.eurprd04.prod.outlook.com (2a01:111:e400:5092::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: JlxuogUeQ4MbJCxEOlPxxaVYnDld6LezYOe7bnxu62+Z9WRSJWyDiHorkue3puudicY0aSfouQeDkDLYiW+JBVYQ1sMgflvT9SYVdRS/qM+r1Oz++xoxV4qsyIfqa4c3xPV32PotYPC/4YU0Ii1AwJkDTaLFu+QIRLW1hHk978HUeRlZxEfMzmSI6aBEcQDoQDKkzlviLew5J6ELCWHa5gJ/PXygseoV4QKEw5kAYTbD92B1q5D3ilz9Hhab9aCxflC0RUVAumIvvaXfP6eIQfkQu8S7k8ndsdPJJ/VqP6y6lfSbPUJQj5G+1PcWNkP58XaLjBLoBeZQLNaRRWzcATH7irIkrhXGGjndEP2Okpw= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1cbb3f47-b682-41d7-6bc4-08d62fe9a612 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Oct 2018 02:23:08.5552 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB1166 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus --- Changes for v3: - None Changes for v2: - None drivers/mtd/spi-nor/spi-nor.c | 9 ++++++--- include/linux/mtd/cfi.h | 1 + include/linux/mtd/spi-nor.h | 3 ++- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 9407ca5..b8b494f 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, u8 cmd; switch (JEDEC_MFR(info)) { + case SNOR_MFR_ST: case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; @@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, - /* Micron */ + /* Micron <--> ST Micro */ { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, @@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor, params->quad_enable = macronix_quad_enable; break; + case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; @@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, mtd->_resume = spi_nor_resume; /* NOR protection support for STmicro/Micron chips and similar */ - if (JEDEC_MFR(info) == SNOR_MFR_MICRON || - info->flags & SPI_NOR_HAS_LOCK) { + if (JEDEC_MFR(info) == SNOR_MFR_ST || + JEDEC_MFR(info) == SNOR_MFR_MICRON || + info->flags & SPI_NOR_HAS_LOCK) { nor->flash_lock = stm_lock; nor->flash_unlock = stm_unlock; nor->flash_is_locked = stm_is_locked; diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h index 9b57a9b..cbf7716 100644 --- a/include/linux/mtd/cfi.h +++ b/include/linux/mtd/cfi.h @@ -377,6 +377,7 @@ struct cfi_fixup { #define CFI_MFR_SHARP 0x00B0 #define CFI_MFR_SST 0x00BF #define CFI_MFR_ST 0x0020 /* STMicroelectronics */ +#define CFI_MFR_MICRON 0x002C /* Micron */ #define CFI_MFR_TOSHIBA 0x0098 #define CFI_MFR_WINBOND 0x00DA diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7f0c730..8b1acf6 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -23,7 +23,8 @@ #define SNOR_MFR_ATMEL CFI_MFR_ATMEL #define SNOR_MFR_GIGADEVICE 0xc8 #define SNOR_MFR_INTEL CFI_MFR_INTEL -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */ +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST From patchwork Fri Oct 12 02:23:13 2018 Content-Type: text/plain; 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Fri, 12 Oct 2018 02:23:13 +0000 Received: from VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123]) by VI1PR04MB1038.eurprd04.prod.outlook.com ([fe80::d887:3c96:479a:4123%3]) with mapi id 15.20.1207.024; Fri, 12 Oct 2018 02:23:13 +0000 From: Yogesh Narayan Gaur To: "linux-mtd@lists.infradead.org" , "linux-spi@vger.kernel.org" , "tudor.ambarus@microchip.com" CC: "marek.vasut@gmail.com" , "cyrille.pitchen@wedev4u.fr" , "boris.brezillon@bootlin.com" , "computersforpeace@gmail.com" , "frieder.schrempf@exceet.de" , "linux-kernel@vger.kernel.org" , Yogesh Narayan Gaur Subject: [PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Topic: [PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash Thread-Index: AQHUYdKGKD+kbaBkdUSmApnPC/zheg== Date: Fri, 12 Oct 2018 02:23:13 +0000 Message-ID: <1539310881-17438-3-git-send-email-yogeshnarayan.gaur@nxp.com> References: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> In-Reply-To: <1539310881-17438-1-git-send-email-yogeshnarayan.gaur@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0225.apcprd06.prod.outlook.com (2603:1096:4:68::33) To VI1PR04MB1038.eurprd04.prod.outlook.com (2a01:111:e400:5092::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yogeshnarayan.gaur@nxp.com; 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This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus --- Changes for v3: - Modified flash node style as suggested by Tudor. Changes for v2: - Removed checkpatch warning, 80 character limit. drivers/mtd/spi-nor/spi-nor.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..0b8a6e0 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1405,6 +1405,12 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Micron */ + { + "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) + }, + /* PMC */ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) }, { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },