From patchwork Sun Jun 7 19:46:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592139 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D7F8A92A for ; Sun, 7 Jun 2020 19:48:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AEB522067B for ; Sun, 7 Jun 2020 19:48:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Oc/y/bf2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AEB522067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ji1HM-0005gJ-ES for patchwork-qemu-devel@patchwork.kernel.org; Sun, 07 Jun 2020 15:48:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ji1FY-0003pq-6J for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:32 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:56259) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ji1FU-0004kU-Oc for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:31 -0400 Received: by mail-wm1-x32b.google.com with SMTP id c71so13281032wmd.5 for ; Sun, 07 Jun 2020 12:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Gyc4jAqqb4iRdL2lJtXMg0ZbvCkpCJJT7AmeHRVjQIU=; b=Oc/y/bf2YKbsou+FlECJQQaWRWfE/7OhJ/02ijQSogrkL+dUbvzNJUUYqc5nCju72I eTq0dAS3izv3b0jJMTvhDX0fcSwBvUz7G0pm8iOxL6b3YxK7FMydc0InC8mRIto3OAng 2s3lH+kJj2BWvEo3zMqxicvIYsUSAbQwfYHmUeuEOS21UV02bklR8Eh41Ql+LgGvsWgb YEvq9IWm8++COw0cI5IlrSyY38+8xP8bX29RKXcEH6Cr8J3I4EPNJTL/IV54s+5suKQl HQ2WaO3sflqnQkcLbqgdqYT9U/fqQc4MFVCM+y4DtAriE3XAo3MH3gV6glGoNtJzVNmp UGXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Gyc4jAqqb4iRdL2lJtXMg0ZbvCkpCJJT7AmeHRVjQIU=; b=tuKrEOkAr509XlY21MWjoLByGTZIHRy7ie0diYoZ5ifyQOLKg+eEruq5LLv4iX3dJd mYMO2BhhDcii8D3Kjhy6sg6dc4nMGuosyfMA59tgh4D/NAXlBHO+8EovGd6CAs+qK2dp 6t229h0uBAb9d9erf+7DvmtR7/7gQfCT/jeiv1hdkQ+WdkcOT698ZWFWPS+8LyjO5iPo OvpAzV8v9VUebNrQN9Q/cVxtwbGig73Y9MvW5oQ77gJ5Nuh7X1HOCuTsxAQVlrBRf5+k idXpcSuHBlJ1lOz4e8tiyg7oQ05QuEYGKKgadRknS3emGnXssjT8Z8nMXw2WPUWQlXuC UY3w== X-Gm-Message-State: AOAM533ZHVbBzK4iEgz8UKoFL5iPVOJwmLHz66FfgklDuXM7eZCb3Jab HSTohsi2VgP7H4BydQ+vmo/D5YnR X-Google-Smtp-Source: ABdhPJyr3f5wRPm0XgYy715q3Ru7xWkQPHX73N4SznEciEeEX0OnYqUjkQZxXYIHtDgjMA5p88O2oA== X-Received: by 2002:a1c:810a:: with SMTP id c10mr13079865wmd.107.1591559187212; Sun, 07 Jun 2020 12:46:27 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.26 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:26 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 01/21] mailmap: Change email address of Filip Bozuta Date: Sun, 7 Jun 2020 21:46:05 +0200 Message-Id: <1591559185-31287-2-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Filip Bozuta wants to use his new email address for his future work in QEMU. CC: Filip Bozuta Signed-off-by: Aleksandar Markovic Reviewed-by: Filip Bozuta Message-Id: <20200602085215.12585-2-aleksandar.qemu.devel@gmail.com> --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index e3628c7..9f2a3a5 100644 --- a/.mailmap +++ b/.mailmap @@ -45,6 +45,7 @@ Aleksandar Markovic Aleksandar Rikalo Aleksandar Rikalo Anthony Liguori Anthony Liguori +Filip Bozuta James Hogan Leif Lindholm Paul Burton From patchwork Sun Jun 7 19:46:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592137 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 391BA92A for ; Sun, 7 Jun 2020 19:48:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0FEB82067B for ; Sun, 7 Jun 2020 19:48:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="i4mhadx6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0FEB82067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ji1HM-0005fh-79 for patchwork-qemu-devel@patchwork.kernel.org; Sun, 07 Jun 2020 15:48:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59826) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ji1FX-0003ow-6p for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:31 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:38448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ji1FV-0004kc-Bw for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:30 -0400 Received: by mail-wr1-x430.google.com with SMTP id e1so15169553wrt.5 for ; Sun, 07 Jun 2020 12:46:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vpjGR3SSo/dqO1sryzCVOBY48tat7koG6WnUT5kfYuU=; b=i4mhadx6/ynf7Kw3aBFKur7jf99VeoAanafiHFDGydNTQJUxMN+S394xTsylnxhabq B/FWSWqEJeveQU/gZ0aWp9+Hw62NRy/24/irF3XJjscOCXJatitxaj8LnD/vUvZVODq4 Ss6yeSKZQtlHBpw84ra86lcsj3SVIJiPM+rfvO9CtiVwYacM/MG8MTtxR3KQNMU2eZZ3 rx/2T9+ciPf0NmZ4j2mjPmqfdAUzTA6U3tStEfY0yUm7NSMVBFiHg2JdHhK5cNNCQNGt u6KgbYLBQyTRTKJzBbX/So0kS8iLbxWAdUQXkBXjcDQvyPAikoEY7hmGli9sUt+Bfv14 kKjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vpjGR3SSo/dqO1sryzCVOBY48tat7koG6WnUT5kfYuU=; b=izJQmArqzW1xvkqCJklB3hhvua5wwy9hckK0sqxwxnTB0wD7dn/W/xehe94GSzcZeh Pond5bNifIYZwhqVXBAfRscmZPoOzxt3oLomhfvphGDLNhucVCNrCa/Tg9JlCyrt8ZIT XqSMn5/TRfjDCqSPMCwanZ7IUQBHhcOKL/RPR0l4mHtv2cedSVJMkYfn1YJL1Hy7GbRU EU0S0CWO28TaEwkiTkDdmSfEczq+HIq8P0cxkxWtI8+xIseY0IMiSfxCccO/iYSvbZ0G 5kztGUiTjqfRlZ0EqlMbXBTvcnuA+lihrbSg8x/AjO99kf0OgpUb8+2Lj/GmoIItkMKJ LlsA== X-Gm-Message-State: AOAM530obX4Wu99S08xvh9XI19nsRcd4B7AnIJt8SsekQv1jP6OHOrzn SIWykrmICCqc3fJ66qhiXKqaPfE3 X-Google-Smtp-Source: ABdhPJy2CNGcRZpcxASVtmMo/y0s0naN5WFeYhXJG4p3QeJgwikw/6w6EFs1TBlkXDnaw0p8N1dF3A== X-Received: by 2002:adf:ea90:: with SMTP id s16mr19956415wrm.299.1591559188013; Sun, 07 Jun 2020 12:46:28 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:27 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 02/21] mailmap: Change email address of Stefan Brankovic Date: Sun, 7 Jun 2020 21:46:06 +0200 Message-Id: <1591559185-31287-3-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Stefan Brankovic wants to use his new email address for his future work in QEMU. CC: Stefan Brankovic Signed-off-by: Aleksandar Markovic Reviewed-by: Stefan Brankovic Message-Id: <20200602085215.12585-3-aleksandar.qemu.devel@gmail.com> --- .mailmap | 1 + 1 file changed, 1 insertion(+) diff --git a/.mailmap b/.mailmap index 9f2a3a5..84f3659 100644 --- a/.mailmap +++ b/.mailmap @@ -52,6 +52,7 @@ Paul Burton Paul Burton Paul Burton Philippe Mathieu-Daudé +Stefan Brankovic Yongbok Kim # Also list preferred name forms where people have changed their From patchwork Sun Jun 7 19:46:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592141 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11780618 for ; Sun, 7 Jun 2020 19:48:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC5882067B for ; Sun, 7 Jun 2020 19:48:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P3oruxSx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DC5882067B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:59746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ji1HR-0005hk-Vg for patchwork-qemu-devel@patchwork.kernel.org; Sun, 07 Jun 2020 15:48:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ji1FX-0003pT-QL for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:31 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:39101) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ji1FW-0004kq-62 for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:31 -0400 Received: by mail-wr1-x436.google.com with SMTP id t18so15164222wru.6 for ; Sun, 07 Jun 2020 12:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GR4eimU9t63Pw1mCFxbwUNXUU4YvTN5YihjHWjA0XDI=; b=P3oruxSxyZp9KdYNDiwu+6cw6x/Wb7gc1UgYelJUWgDxdciMlwmaM2/OfTywZku/am MBU9/qm0zzN5se7wLYoI3z41j0DjPeYPAEFCSyNGRlhH85PhVdyhbFyonW1FT8MVE0SC lq37xRHz0Ysao9/mW/RZuGiYan7iv09IROFu8Wv/oq4xqthPPY1+Oul2oaOsofA1qJ96 IxnR39HGs1f1YoqYtJnPXRAXgg75eirroV54xxTNM/DYSM/h66VDm1qaKWCdxZH+pPmM SP64lo7opD+ShdnTv9jzblukJMBCLU8dyklw+sjirQKRQRe3gsA1KRyW1Nx6RxmnINK5 D/Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GR4eimU9t63Pw1mCFxbwUNXUU4YvTN5YihjHWjA0XDI=; b=ipqRDF4MSPkNh0p0gc5x8Tc4RQh8Nx7WIyuZMy3Fhy3LWheAI8scDtRtIj7o4r99ad JJZe7kDINgKV4k8arF/U8SX3CTwsxrXnONAgPxrHGJSaEIeRAy0hhAZwXR+GSwlQzgk6 n5CjrOUqOTVAwVavEpprLN/qVc3GUlzrbC8nrkSLRnPoH1QJFM0OOo3xf/GMM/OCIdHN BwO8LP2AI1i9MTH/+MeVQg9hitsLtTSqln4cQQZFtTVKmSahDpB5KW80L/vKEZ6C96Pt infw3zW8Mg3Ogu7aaNJOFCYuQvUJG/NcrRY1B0MjpwMi9zt4C0FjATqCpGiDm0HLYFfd OBAA== X-Gm-Message-State: AOAM533z1EET7+OS7GHR2gK/LZya1f8+7jos9n5K/Pa4t7nwYZjU4gR4 YrSw8eplJVIFtSpd7zI6myc7pK4k X-Google-Smtp-Source: ABdhPJxzlRDsepqMVublejJlY7a8iW8/8sR/qn1HfxvabumaA6GIG+UJLdfEFbZmvjLx0Oe9X0q56A== X-Received: by 2002:a5d:654c:: with SMTP id z12mr19648203wrv.315.1591559188784; Sun, 07 Jun 2020 12:46:28 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:28 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 03/21] target/mips: fpu: Demacro ADD. Date: Sun, 7 Jun 2020 21:46:07 +0200 Message-Id: <1591559185-31287-4-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-2-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 5287c86..984f3f4 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1208,12 +1208,48 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ return ((uint64_t)wth2 << 32) | wt2; \ } -FLOAT_BINOP(add) FLOAT_BINOP(sub) FLOAT_BINOP(mul) FLOAT_BINOP(div) #undef FLOAT_BINOP +uint64_t helper_float_add_d(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint64_t dt2; + + dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_add_s(CPUMIPSState *env, + uint32_t fst0, uint32_t fst1) +{ + uint32_t wt2; + + wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_add_ps(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t wtl2; + uint32_t wth2; + + wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status); + wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)wth2 << 32) | wtl2; +} + + /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { From patchwork Sun Jun 7 19:46:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592149 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D8F34618 for ; Sun, 7 Jun 2020 19:51:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB7AF20663 for ; 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Date: Sun, 7 Jun 2020 21:46:08 +0200 Message-Id: <1591559185-31287-5-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-3-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 984f3f4..715a872 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ return ((uint64_t)wth2 << 32) | wt2; \ } -FLOAT_BINOP(sub) FLOAT_BINOP(mul) FLOAT_BINOP(div) #undef FLOAT_BINOP @@ -1249,6 +1248,42 @@ uint64_t helper_float_add_ps(CPUMIPSState *env, return ((uint64_t)wth2 << 32) | wtl2; } +uint64_t helper_float_sub_d(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint64_t dt2; + + dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_sub_s(CPUMIPSState *env, + uint32_t fst0, uint32_t fst1) +{ + uint32_t wt2; + + wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_sub_ps(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t wtl2; + uint32_t wth2; + + wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status); + wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)wth2 << 32) | wtl2; +} + /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) From patchwork Sun Jun 7 19:46:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592143 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 138C0618 for ; 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Sun, 07 Jun 2020 12:46:29 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 05/21] target/mips: fpu: Demacro MUL. Date: Sun, 7 Jun 2020 21:46:09 +0200 Message-Id: <1591559185-31287-6-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-4-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 715a872..449e945 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ return ((uint64_t)wth2 << 32) | wt2; \ } -FLOAT_BINOP(mul) FLOAT_BINOP(div) #undef FLOAT_BINOP @@ -1284,6 +1283,42 @@ uint64_t helper_float_sub_ps(CPUMIPSState *env, return ((uint64_t)wth2 << 32) | wtl2; } +uint64_t helper_float_mul_d(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint64_t dt2; + + dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_mul_s(CPUMIPSState *env, + uint32_t fst0, uint32_t fst1) +{ + uint32_t wt2; + + wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_mul_ps(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t wtl2; + uint32_t wth2; + + wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status); + wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)wth2 << 32) | wtl2; +} + /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) From patchwork Sun Jun 7 19:46:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592147 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B94DE60D for ; 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Sun, 07 Jun 2020 12:46:30 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 06/21] target/mips: fpu: Demacro DIV. Date: Sun, 7 Jun 2020 21:46:10 +0200 Message-Id: <1591559185-31287-7-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x329.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. 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Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-5-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 449e945..2759c99 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ return ((uint64_t)wth2 << 32) | wt2; \ } -FLOAT_BINOP(div) #undef FLOAT_BINOP uint64_t helper_float_add_d(CPUMIPSState *env, @@ -1319,6 +1318,42 @@ uint64_t helper_float_mul_ps(CPUMIPSState *env, return ((uint64_t)wth2 << 32) | wtl2; } +uint64_t helper_float_div_d(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint64_t dt2; + + dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_div_s(CPUMIPSState *env, + uint32_t fst0, uint32_t fst1) +{ + uint32_t wt2; + + wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_div_ps(CPUMIPSState *env, + uint64_t fdt0, uint64_t fdt1) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t wtl2; + uint32_t wth2; + + wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status); + wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)wth2 << 32) | wtl2; +} + /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) From patchwork Sun Jun 7 19:46:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592145 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 87D2160D for ; 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Sun, 07 Jun 2020 12:46:31 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 07/21] target/mips: fpu: Remove now unused macro FLOAT_BINOP Date: Sun, 7 Jun 2020 21:46:11 +0200 Message-Id: <1591559185-31287-8-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" After demacroing ., this macro is not needed anymore. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-6-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 39 --------------------------------------- 1 file changed, 39 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 2759c99..a3a3968 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1170,45 +1170,6 @@ FLOAT_CLASS(class_d, 64) #undef FLOAT_CLASS /* binary operations */ -#define FLOAT_BINOP(name) \ -uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - uint64_t dt2; \ - \ - dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\ - update_fcr31(env, GETPC()); \ - return dt2; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ - uint32_t fst0, uint32_t fst1) \ -{ \ - uint32_t wt2; \ - \ - wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\ - update_fcr31(env, GETPC()); \ - return wt2; \ -} \ - \ -uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1) \ -{ \ - uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 = fdt0 >> 32; \ - uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 = fdt1 >> 32; \ - uint32_t wt2; \ - uint32_t wth2; \ - \ - wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \ - wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return ((uint64_t)wth2 << 32) | wt2; \ -} - -#undef FLOAT_BINOP uint64_t helper_float_add_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) From patchwork Sun Jun 7 19:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592151 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE25F618 for ; Sun, 7 Jun 2020 19:53:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 602512074B for ; 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Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-7-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index a3a3968..c070081 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1495,12 +1495,51 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ update_fcr31(env, GETPC()); \ return ((uint64_t)fsth0 << 32) | fst0; \ } -FLOAT_FMA(madd, 0) FLOAT_FMA(msub, float_muladd_negate_c) FLOAT_FMA(nmadd, float_muladd_negate_result) FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) #undef FLOAT_FMA +uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0, + uint64_t fst1, uint64_t fst2) +{ + fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0, + uint32_t fst1, uint32_t fst2) +{ + fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0, + uint64_t fdt1, uint64_t fdt2) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status); + fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status); + fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status); + fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return ((uint64_t)fsth0 << 32) | fstl0; +} + + #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ uint ## bits ## _t fs, \ From patchwork Sun Jun 7 19:46:13 2020 Content-Type: text/plain; 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Sun, 07 Jun 2020 12:46:32 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 09/21] target/mips: fpu: Demacro MSUB. Date: Sun, 7 Jun 2020 21:46:13 +0200 Message-Id: <1591559185-31287-10-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is just a cosmetic change to enable tools like gcov, gdb, callgrind, etc. to better display involved source code. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-8-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index c070081..e37fc40 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ update_fcr31(env, GETPC()); \ return ((uint64_t)fsth0 << 32) | fst0; \ } -FLOAT_FMA(msub, float_muladd_negate_c) FLOAT_FMA(nmadd, float_muladd_negate_result) FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) #undef FLOAT_FMA @@ -1539,6 +1538,45 @@ uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0, return ((uint64_t)fsth0 << 32) | fstl0; } +uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0, + uint64_t fst1, uint64_t fst2) +{ + fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0, + uint32_t fst1, uint32_t fst2) +{ + fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0, + uint64_t fdt1, uint64_t fdt2) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status); + fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status); + fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status); + fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status); + + update_fcr31(env, GETPC()); + return ((uint64_t)fsth0 << 32) | fstl0; +} + #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ From patchwork Sun Jun 7 19:46:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592153 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AF5B760D for ; Sun, 7 Jun 2020 19:53:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83FED2074B for ; Sun, 7 Jun 2020 19:53:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tn2Vf0mr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83FED2074B Authentication-Results: mail.kernel.org; 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Date: Sun, 7 Jun 2020 21:46:14 +0200 Message-Id: <1591559185-31287-11-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is just a cosmetic change to enable tools like gcov, gdb, callgrind, etc. to better display involved source code. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-9-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index e37fc40..d4c065f 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ update_fcr31(env, GETPC()); \ return ((uint64_t)fsth0 << 32) | fst0; \ } -FLOAT_FMA(nmadd, float_muladd_negate_result) FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) #undef FLOAT_FMA @@ -1577,6 +1576,49 @@ uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0, return ((uint64_t)fsth0 << 32) | fstl0; } +uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0, + uint64_t fst1, uint64_t fst2) +{ + fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status); + fst0 = float64_chs(fst0); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0, + uint32_t fst1, uint32_t fst2) +{ + fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status); + fst0 = float32_chs(fst0); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0, + uint64_t fdt1, uint64_t fdt2) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status); + fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status); + fstl0 = float32_chs(fstl0); + fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status); + fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status); + fsth0 = float32_chs(fsth0); + + update_fcr31(env, GETPC()); + return ((uint64_t)fsth0 << 32) | fstl0; +} + #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ From patchwork Sun Jun 7 19:46:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EB886618 for ; Sun, 7 Jun 2020 19:56:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B6AAB2074B for ; Sun, 7 Jun 2020 19:56:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hKMHmCCW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B6AAB2074B Authentication-Results: mail.kernel.org; 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Date: Sun, 7 Jun 2020 21:46:15 +0200 Message-Id: <1591559185-31287-12-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is just a cosmetic change to enable tools like gcov, gdb, callgrind, etc. to better display involved source code. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-10-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index d4c065f..927bac2 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ update_fcr31(env, GETPC()); \ return ((uint64_t)fsth0 << 32) | fst0; \ } -FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) #undef FLOAT_FMA uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0, @@ -1619,6 +1618,49 @@ uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0, return ((uint64_t)fsth0 << 32) | fstl0; } +uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0, + uint64_t fst1, uint64_t fst2) +{ + fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status); + fst0 = float64_chs(fst0); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0, + uint32_t fst1, uint32_t fst2) +{ + fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status); + fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status); + fst0 = float32_chs(fst0); + + update_fcr31(env, GETPC()); + return fst0; +} + +uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0, + uint64_t fdt1, uint64_t fdt2) +{ + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; + uint32_t fsth0 = fdt0 >> 32; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; + uint32_t fsth1 = fdt1 >> 32; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; + uint32_t fsth2 = fdt2 >> 32; + + fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status); + fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status); + fstl0 = float32_chs(fstl0); + fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status); + fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status); + fsth0 = float32_chs(fsth0); + + update_fcr31(env, GETPC()); + return ((uint64_t)fsth0 << 32) | fstl0; +} + #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ From patchwork Sun Jun 7 19:46:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A624D618 for ; Sun, 7 Jun 2020 19:58:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B93A2074B for ; Sun, 7 Jun 2020 19:58:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZlnUV/l9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B93A2074B Authentication-Results: mail.kernel.org; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" After demacroing ., these macros are not needed anymore. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-11-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 50 ------------------------------------------------ 1 file changed, 50 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 927bac2..e8e50e4 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1446,56 +1446,6 @@ FLOAT_MINMAX(mina_d, 64, minnummag) #undef FLOAT_MINMAX /* ternary operations */ -#define UNFUSED_FMA(prefix, a, b, c, flags) \ -{ \ - a = prefix##_mul(a, b, &env->active_fpu.fp_status); \ - if ((flags) & float_muladd_negate_c) { \ - a = prefix##_sub(a, c, &env->active_fpu.fp_status); \ - } else { \ - a = prefix##_add(a, c, &env->active_fpu.fp_status); \ - } \ - if ((flags) & float_muladd_negate_result) { \ - a = prefix##_chs(a); \ - } \ -} - -/* FMA based operations */ -#define FLOAT_FMA(name, type) \ -uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \ - update_fcr31(env, GETPC()); \ - return fdt0; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ - uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ -{ \ - UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ - update_fcr31(env, GETPC()); \ - return fst0; \ -} \ - \ -uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 = fdt0 >> 32; \ - uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 = fdt1 >> 32; \ - uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ - uint32_t fsth2 = fdt2 >> 32; \ - \ - UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ - UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \ - update_fcr31(env, GETPC()); \ - return ((uint64_t)fsth0 << 32) | fst0; \ -} -#undef FLOAT_FMA uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0, uint64_t fst1, uint64_t fst2) From patchwork Sun Jun 7 19:46:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F69760D for ; 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Sun, 07 Jun 2020 12:46:35 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 13/21] target/mips: fpu: Demacro CLASS. Date: Sun, 7 Jun 2020 21:46:17 +0200 Message-Id: <1591559185-31287-14-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is just a cosmetic change to enable tools like gcov, gdb, callgrind, etc. to better display involved source code. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-12-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index e8e50e4..b3903f5 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1165,10 +1165,76 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ return float_ ## name(arg, &env->active_fpu.fp_status); \ } -FLOAT_CLASS(class_s, 32) -FLOAT_CLASS(class_d, 64) #undef FLOAT_CLASS +uint64_t float_class_d(uint64_t arg, float_status *status) +{ + if (float64_is_signaling_nan(arg, status)) { + return FLOAT_CLASS_SIGNALING_NAN; + } else if (float64_is_quiet_nan(arg, status)) { + return FLOAT_CLASS_QUIET_NAN; + } else if (float64_is_neg(arg)) { + if (float64_is_infinity(arg)) { + return FLOAT_CLASS_NEGATIVE_INFINITY; + } else if (float64_is_zero(arg)) { + return FLOAT_CLASS_NEGATIVE_ZERO; + } else if (float64_is_zero_or_denormal(arg)) { + return FLOAT_CLASS_NEGATIVE_SUBNORMAL; + } else { + return FLOAT_CLASS_NEGATIVE_NORMAL; + } + } else { + if (float64_is_infinity(arg)) { + return FLOAT_CLASS_POSITIVE_INFINITY; + } else if (float64_is_zero(arg)) { + return FLOAT_CLASS_POSITIVE_ZERO; + } else if (float64_is_zero_or_denormal(arg)) { + return FLOAT_CLASS_POSITIVE_SUBNORMAL; + } else { + return FLOAT_CLASS_POSITIVE_NORMAL; + } + } +} + +uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg) +{ + return float_class_d(arg, &env->active_fpu.fp_status); +} + +uint32_t float_class_s(uint32_t arg, float_status *status) +{ + if (float32_is_signaling_nan(arg, status)) { + return FLOAT_CLASS_SIGNALING_NAN; + } else if (float32_is_quiet_nan(arg, status)) { + return FLOAT_CLASS_QUIET_NAN; + } else if (float32_is_neg(arg)) { + if (float32_is_infinity(arg)) { + return FLOAT_CLASS_NEGATIVE_INFINITY; + } else if (float32_is_zero(arg)) { + return FLOAT_CLASS_NEGATIVE_ZERO; + } else if (float32_is_zero_or_denormal(arg)) { + return FLOAT_CLASS_NEGATIVE_SUBNORMAL; + } else { + return FLOAT_CLASS_NEGATIVE_NORMAL; + } + } else { + if (float32_is_infinity(arg)) { + return FLOAT_CLASS_POSITIVE_INFINITY; + } else if (float32_is_zero(arg)) { + return FLOAT_CLASS_POSITIVE_ZERO; + } else if (float32_is_zero_or_denormal(arg)) { + return FLOAT_CLASS_POSITIVE_SUBNORMAL; + } else { + return FLOAT_CLASS_POSITIVE_NORMAL; + } + } +} + +uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg) +{ + return float_class_s(arg, &env->active_fpu.fp_status); +} + /* binary operations */ uint64_t helper_float_add_d(CPUMIPSState *env, From patchwork Sun Jun 7 19:46:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592187 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8916360D for ; Sun, 7 Jun 2020 19:59:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5F0B22074B for ; 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Sun, 07 Jun 2020 12:46:36 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:36 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 14/21] target/mips: fpu: Remove now unused FLOAT_CLASS macro Date: Sun, 7 Jun 2020 21:46:18 +0200 Message-Id: <1591559185-31287-15-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" After demacroing CLASS., this macro is not needed anymore. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-13-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 39 --------------------------------------- 1 file changed, 39 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index b3903f5..e227e53 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1128,45 +1128,6 @@ FLOAT_RINT(rint_d, 64) #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100 #define FLOAT_CLASS_POSITIVE_ZERO 0x200 -#define FLOAT_CLASS(name, bits) \ -uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \ - float_status *status) \ -{ \ - if (float ## bits ## _is_signaling_nan(arg, status)) { \ - return FLOAT_CLASS_SIGNALING_NAN; \ - } else if (float ## bits ## _is_quiet_nan(arg, status)) { \ - return FLOAT_CLASS_QUIET_NAN; \ - } else if (float ## bits ## _is_neg(arg)) { \ - if (float ## bits ## _is_infinity(arg)) { \ - return FLOAT_CLASS_NEGATIVE_INFINITY; \ - } else if (float ## bits ## _is_zero(arg)) { \ - return FLOAT_CLASS_NEGATIVE_ZERO; \ - } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ - return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \ - } else { \ - return FLOAT_CLASS_NEGATIVE_NORMAL; \ - } \ - } else { \ - if (float ## bits ## _is_infinity(arg)) { \ - return FLOAT_CLASS_POSITIVE_INFINITY; \ - } else if (float ## bits ## _is_zero(arg)) { \ - return FLOAT_CLASS_POSITIVE_ZERO; \ - } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ - return FLOAT_CLASS_POSITIVE_SUBNORMAL; \ - } else { \ - return FLOAT_CLASS_POSITIVE_NORMAL; \ - } \ - } \ -} \ - \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t arg) \ -{ \ - return float_ ## name(arg, &env->active_fpu.fp_status); \ -} - -#undef FLOAT_CLASS - uint64_t float_class_d(uint64_t arg, float_status *status) { if (float64_is_signaling_nan(arg, status)) { From patchwork Sun Jun 7 19:46:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 244B3913 for ; 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Sun, 07 Jun 2020 12:46:36 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 15/21] target/mips: fpu: Demacro RINT. Date: Sun, 7 Jun 2020 21:46:19 +0200 Message-Id: <1591559185-31287-16-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x330.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is just a cosmetic change to enable tools like gcov, gdb, callgrind, etc. to better display involved source code. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-14-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index e227e53..dae1331 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1113,10 +1113,26 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ return fdret; \ } -FLOAT_RINT(rint_s, 32) -FLOAT_RINT(rint_d, 64) #undef FLOAT_RINT +uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs) +{ + uint64_t fdret; + + fdret = float64_round_to_int(fs, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdret; +} + +uint32_t helper_float_rint_s(CPUMIPSState *env, uint32_t fs) +{ + uint32_t fdret; + + fdret = float32_round_to_int(fs, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdret; +} + #define FLOAT_CLASS_SIGNALING_NAN 0x001 #define FLOAT_CLASS_QUIET_NAN 0x002 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004 From patchwork Sun Jun 7 19:46:20 2020 Content-Type: text/plain; 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Sun, 07 Jun 2020 12:46:37 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 16/21] target/mips: fpu: Remove now unused FLOAT_RINT macro Date: Sun, 7 Jun 2020 21:46:20 +0200 Message-Id: <1591559185-31287-17-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" After demacroing RINT., this macro is not needed anymore. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-15-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index dae1331..56ba491 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1102,19 +1102,6 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) return ((uint64_t)fsth2 << 32) | fst2; } -#define FLOAT_RINT(name, bits) \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t fs) \ -{ \ - uint ## bits ## _t fdret; \ - \ - fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return fdret; \ -} - -#undef FLOAT_RINT - uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs) { uint64_t fdret; From patchwork Sun Jun 7 19:46:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592161 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3441A60D for ; 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Sun, 07 Jun 2020 12:46:38 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 17/21] target/mips: fpu: Name better paired-single variables Date: Sun, 7 Jun 2020 21:46:21 +0200 Message-Id: <1591559185-31287-18-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Use consistently 'l' and 'h' for low and high halves. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-16-aleksandar.qemu.devel@gmail.com> --- target/mips/fpu_helper.c | 62 ++++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index 56ba491..dbb8ca5 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -1059,14 +1059,14 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; - fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, - &env->active_fpu.fp_status); + fstl2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) @@ -1091,15 +1091,15 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) { - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; - fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fstl2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fstl2 = float32_div(float32_one, fstl2, &env->active_fpu.fp_status); fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs) @@ -1367,19 +1367,19 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { - uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; - uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; uint32_t fsth2 = fdt2 >> 32; - fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, float32_one, + fstl2 = float32_chs(float32_sub(fstl2, float32_one, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) @@ -1404,51 +1404,51 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { - uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; - uint32_t fst2 = fdt2 & 0XFFFFFFFF; + uint32_t fstl2 = fdt2 & 0XFFFFFFFF; uint32_t fsth2 = fdt2 >> 32; - fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fstl2 = float32_sub(fstl2, float32_one, &env->active_fpu.fp_status); fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, + fstl2 = float32_chs(float32_div(fstl2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { - uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; - uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; uint32_t fsth1 = fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; - fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 = float32_add(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_add(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) { - uint32_t fst0 = fdt0 & 0XFFFFFFFF; + uint32_t fstl0 = fdt0 & 0XFFFFFFFF; uint32_t fsth0 = fdt0 >> 32; - uint32_t fst1 = fdt1 & 0XFFFFFFFF; + uint32_t fstl1 = fdt1 & 0XFFFFFFFF; uint32_t fsth1 = fdt1 >> 32; - uint32_t fst2; + uint32_t fstl2; uint32_t fsth2; - fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status); + fstl2 = float32_mul(fstl0, fsth0, &env->active_fpu.fp_status); + fsth2 = float32_mul(fstl1, fsth1, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; + return ((uint64_t)fsth2 << 32) | fstl2; } #define FLOAT_MINMAX(name, bits, minmaxfunc) \ From patchwork Sun Jun 7 19:46:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592199 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6111913 for ; Sun, 7 Jun 2020 20:05:31 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B267206F6 for ; Sun, 7 Jun 2020 20:05:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mq051vAM" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B267206F6 Authentication-Results: mail.kernel.org; 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Sun, 07 Jun 2020 12:46:39 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:38 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 18/21] target/mips: fpu: Refactor conversion from ieee to mips exception flags Date: Sun, 7 Jun 2020 21:46:22 +0200 Message-Id: <1591559185-31287-19-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The original coversion function is used for regular and MSA floating point instructions handling. Since there are some nuanced differences between regular and MSA floating point exception handling, provide two instances of the conversion function, rather than just a single common one. Inline both instances of this function instances for the sake of performance. Improve variable naming in surrounding code for clarity. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200518200920.17344-17-aleksandar.qemu.devel@gmail.com> --- target/mips/internal.h | 1 - target/mips/fpu_helper.c | 55 ++++++++++++++++++---------------- target/mips/msa_helper.c | 77 ++++++++++++++++++++++++++++++++---------------- 3 files changed, 82 insertions(+), 51 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 1bf274b..684356e 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -224,7 +224,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst); uint64_t float_class_d(uint64_t arg, float_status *fst); extern unsigned int ieee_rm[]; -int ieee_ex_to_mips(int xcpt); void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); static inline void restore_rounding_mode(CPUMIPSState *env) diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index dbb8ca5..7a3a61c 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -189,43 +189,48 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) } } -int ieee_ex_to_mips(int xcpt) +static inline int ieee_to_mips_xcpt(int ieee_xcpt) { - int ret = 0; - if (xcpt) { - if (xcpt & float_flag_invalid) { - ret |= FP_INVALID; - } - if (xcpt & float_flag_overflow) { - ret |= FP_OVERFLOW; - } - if (xcpt & float_flag_underflow) { - ret |= FP_UNDERFLOW; - } - if (xcpt & float_flag_divbyzero) { - ret |= FP_DIV0; - } - if (xcpt & float_flag_inexact) { - ret |= FP_INEXACT; - } + int mips_xcpt = 0; + + if (ieee_xcpt & float_flag_invalid) { + mips_xcpt |= FP_INVALID; + } + if (ieee_xcpt & float_flag_overflow) { + mips_xcpt |= FP_OVERFLOW; } - return ret; + if (ieee_xcpt & float_flag_underflow) { + mips_xcpt |= FP_UNDERFLOW; + } + if (ieee_xcpt & float_flag_divbyzero) { + mips_xcpt |= FP_DIV0; + } + if (ieee_xcpt & float_flag_inexact) { + mips_xcpt |= FP_INEXACT; + } + + return mips_xcpt; } static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) { - int tmp = ieee_ex_to_mips(get_float_exception_flags( - &env->active_fpu.fp_status)); + int ieee_exception_flags = get_float_exception_flags( + &env->active_fpu.fp_status); + int mips_exception_flags = 0; + + if (ieee_exception_flags) { + mips_exception_flags = ieee_to_mips_xcpt(ieee_exception_flags); + } - SET_FP_CAUSE(env->active_fpu.fcr31, tmp); + SET_FP_CAUSE(env->active_fpu.fcr31, mips_exception_flags); - if (tmp) { + if (mips_exception_flags) { set_float_exception_flags(0, &env->active_fpu.fp_status); - if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { + if (GET_FP_ENABLE(env->active_fpu.fcr31) & mips_exception_flags) { do_raise_exception(env, EXCP_FPE, pc); } else { - UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); + UPDATE_FP_FLAGS(env->active_fpu.fcr31, mips_exception_flags); } } } diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 3c7012c..c3b2719 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -5419,54 +5419,81 @@ static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr) #define CLEAR_IS_INEXACT 2 #define RECIPROCAL_INEXACT 4 -static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) + +static inline int ieee_to_mips_xcpt_msa(int ieee_xcpt) { - int ieee_ex; + int mips_xcpt = 0; - int c; + if (ieee_xcpt & float_flag_invalid) { + mips_xcpt |= FP_INVALID; + } + if (ieee_xcpt & float_flag_overflow) { + mips_xcpt |= FP_OVERFLOW; + } + if (ieee_xcpt & float_flag_underflow) { + mips_xcpt |= FP_UNDERFLOW; + } + if (ieee_xcpt & float_flag_divbyzero) { + mips_xcpt |= FP_DIV0; + } + if (ieee_xcpt & float_flag_inexact) { + mips_xcpt |= FP_INEXACT; + } + + return mips_xcpt; +} + +static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) +{ + int ieee_exception_flags; + int mips_exception_flags = 0; int cause; int enable; - ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status); + ieee_exception_flags = get_float_exception_flags( + &env->active_tc.msa_fp_status); /* QEMU softfloat does not signal all underflow cases */ if (denormal) { - ieee_ex |= float_flag_underflow; + ieee_exception_flags |= float_flag_underflow; + } + if (ieee_exception_flags) { + mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags); } - - c = ieee_ex_to_mips(ieee_ex); enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED; /* Set Inexact (I) when flushing inputs to zero */ - if ((ieee_ex & float_flag_input_denormal) && + if ((ieee_exception_flags & float_flag_input_denormal) && (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { if (action & CLEAR_IS_INEXACT) { - c &= ~FP_INEXACT; + mips_exception_flags &= ~FP_INEXACT; } else { - c |= FP_INEXACT; + mips_exception_flags |= FP_INEXACT; } } /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */ - if ((ieee_ex & float_flag_output_denormal) && + if ((ieee_exception_flags & float_flag_output_denormal) && (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { - c |= FP_INEXACT; + mips_exception_flags |= FP_INEXACT; if (action & CLEAR_FS_UNDERFLOW) { - c &= ~FP_UNDERFLOW; + mips_exception_flags &= ~FP_UNDERFLOW; } else { - c |= FP_UNDERFLOW; + mips_exception_flags |= FP_UNDERFLOW; } } /* Set Inexact (I) when Overflow (O) is not enabled */ - if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) { - c |= FP_INEXACT; + if ((mips_exception_flags & FP_OVERFLOW) != 0 && + (enable & FP_OVERFLOW) == 0) { + mips_exception_flags |= FP_INEXACT; } /* Clear Exact Underflow when Underflow (U) is not enabled */ - if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 && - (c & FP_INEXACT) == 0) { - c &= ~FP_UNDERFLOW; + if ((mips_exception_flags & FP_UNDERFLOW) != 0 && + (enable & FP_UNDERFLOW) == 0 && + (mips_exception_flags & FP_INEXACT) == 0) { + mips_exception_flags &= ~FP_UNDERFLOW; } /* @@ -5474,11 +5501,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) * divide by zero */ if ((action & RECIPROCAL_INEXACT) && - (c & (FP_INVALID | FP_DIV0)) == 0) { - c = FP_INEXACT; + (mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) { + mips_exception_flags = FP_INEXACT; } - cause = c & enable; /* all current enabled exceptions */ + cause = mips_exception_flags & enable; /* all current enabled exceptions */ if (cause == 0) { /* @@ -5486,7 +5513,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) * with all current exceptions */ SET_FP_CAUSE(env->active_tc.msacsr, - (GET_FP_CAUSE(env->active_tc.msacsr) | c)); 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Sun, 07 Jun 2020 12:46:40 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:39 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 19/21] hw/mips: Implement the kvm_type() hook in MachineClass Date: Sun, 7 Jun 2020 21:46:23 +0200 Message-Id: <1591559185-31287-20-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x331.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Huacai Chen MIPS has two types of KVM: TE & VZ, and TE is the default type. Now we can't create a VZ guest in QEMU because it lacks the kvm_type() hook in MachineClass. Besides, libvirt uses a null-machine to detect the kvm capability, so by default it will return "KVM not supported" on a VZ platform. Thus, null-machine also need the kvm_type() hook. Reviewed-by: Aleksandar Markovic Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang Signed-off-by: Aleksandar Markovic Message-Id: <1591065557-9174-2-git-send-email-chenhc@lemote.com> --- include/hw/mips/mips.h | 3 +++ hw/core/null-machine.c | 4 ++++ hw/mips/common.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++ hw/core/Makefile.objs | 2 +- hw/mips/Makefile.objs | 2 +- 5 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 hw/mips/common.c diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h index 0af4c3d..2ac0580 100644 --- a/include/hw/mips/mips.h +++ b/include/hw/mips/mips.h @@ -20,4 +20,7 @@ void rc4030_dma_write(void *dma, uint8_t *buf, int len); DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr); +/* common.c */ +int mips_kvm_type(MachineState *machine, const char *vm_type); + #endif diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index cb47d9d..94a36f9 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -17,6 +17,7 @@ #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "hw/core/cpu.h" +#include "hw/mips/mips.h" static void machine_none_init(MachineState *mch) { @@ -50,6 +51,9 @@ static void machine_none_machine_init(MachineClass *mc) mc->max_cpus = 1; mc->default_ram_size = 0; mc->default_ram_id = "ram"; +#ifdef TARGET_MIPS + mc->kvm_type = mips_kvm_type; +#endif } DEFINE_MACHINE("none", machine_none_machine_init) diff --git a/hw/mips/common.c b/hw/mips/common.c new file mode 100644 index 0000000..fd7e10a --- /dev/null +++ b/hw/mips/common.c @@ -0,0 +1,55 @@ +/* + * Common MIPS routines + * + * Copyright (C) 2020 Huacai Chen + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "hw/boards.h" +#include "hw/mips/mips.h" +#include "sysemu/kvm_int.h" + +#ifndef CONFIG_KVM + +int mips_kvm_type(MachineState *machine, const char *vm_type) +{ + return 0; +} + +#else + +int mips_kvm_type(MachineState *machine, const char *vm_type) +{ + int r; + KVMState *s = KVM_STATE(machine->accelerator); + + r = kvm_check_extension(s, KVM_CAP_MIPS_VZ); + if (r > 0) { + return KVM_VM_MIPS_VZ; + } + + r = kvm_check_extension(s, KVM_CAP_MIPS_TE); + if (r > 0) { + return KVM_VM_MIPS_TE; + } + + return -1; +} + +#endif diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 1d540ed..b5672f4 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -17,11 +17,11 @@ common-obj-$(CONFIG_SOFTMMU) += vm-change-state-handler.o common-obj-$(CONFIG_SOFTMMU) += qdev-properties-system.o common-obj-$(CONFIG_SOFTMMU) += sysbus.o common-obj-$(CONFIG_SOFTMMU) += machine.o -common-obj-$(CONFIG_SOFTMMU) += null-machine.o common-obj-$(CONFIG_SOFTMMU) += loader.o common-obj-$(CONFIG_SOFTMMU) += machine-hmp-cmds.o common-obj-$(CONFIG_SOFTMMU) += numa.o common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o +obj-$(CONFIG_SOFTMMU) += null-machine.o obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs index 739e2b7..3b3e6ea 100644 --- a/hw/mips/Makefile.objs +++ b/hw/mips/Makefile.objs @@ -1,4 +1,4 @@ -obj-y += addr.o mips_int.o +obj-y += addr.o common.o mips_int.o obj-$(CONFIG_R4K) += r4k.o obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o obj-$(CONFIG_MIPSSIM) += mipssim.o From patchwork Sun Jun 7 19:46:24 2020 Content-Type: text/plain; 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Sun, 07 Jun 2020 12:46:40 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 20/21] target/mips: Add Loongson-3 CPU definition Date: Sun, 7 Jun 2020 21:46:24 +0200 Message-Id: <1591559185-31287-21-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Huacai Chen Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while Loongson-3A R4 is the newest and its ISA is almost the superset of all others. To reduce complexity, we just define two CPU types: 1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is suitable for TCG because Loongson-3A R1 has fewest ASE. 2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is suitable for KVM because Loongson-3A R4 has the VZ ASE. Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well. [AM: Rearranged insn_flags, added comments, renamed lmi_helper.c, improved commit message, fixed checkpatch warnings] Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com> --- target/mips/cpu.h | 32 ++++++++++- target/mips/internal.h | 2 + target/mips/mips-defs.h | 45 ++++++++------- target/mips/{lmi_helper.c => lmmi_helper.c} | 0 target/mips/translate.c | 2 + target/mips/translate_init.inc.c | 86 +++++++++++++++++++++++++++++ target/mips/Makefile.objs | 2 +- 7 files changed, 146 insertions(+), 23 deletions(-) rename target/mips/{lmi_helper.c => lmmi_helper.c} (100%) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 94d01ea..7cf7f52 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t; * 3 Config3 WatchLo3 WatchHi * 4 Config4 WatchLo4 WatchHi * 5 Config5 WatchLo5 WatchHi - * 6 WatchLo6 WatchHi - * 7 WatchLo7 WatchHi + * 6 Config6 WatchLo6 WatchHi + * 7 Config7 WatchLo7 WatchHi * * * Register 20 Register 21 Register 22 Register 23 @@ -940,7 +940,35 @@ struct CPUMIPSState { #define CP0C5_UFR 2 #define CP0C5_NFExists 0 int32_t CP0_Config6; + int32_t CP0_Config6_rw_bitmask; +#define CP0C6_BPPASS 31 +#define CP0C6_KPOS 24 +#define CP0C6_KE 23 +#define CP0C6_VTLBONLY 22 +#define CP0C6_LASX 21 +#define CP0C6_SSEN 20 +#define CP0C6_DISDRTIME 19 +#define CP0C6_PIXNUEN 18 +#define CP0C6_SCRAND 17 +#define CP0C6_LLEXCEN 16 +#define CP0C6_DISVC 15 +#define CP0C6_VCLRU 14 +#define CP0C6_DCLRU 13 +#define CP0C6_PIXUEN 12 +#define CP0C6_DISBLKLYEN 11 +#define CP0C6_UMEMUALEN 10 +#define CP0C6_SFBEN 8 +#define CP0C6_FLTINT 7 +#define CP0C6_VLTINT 6 +#define CP0C6_DISBTB 5 +#define CP0C6_STPREFCTL 2 +#define CP0C6_INSTPREF 1 +#define CP0C6_DATAPREF 0 int32_t CP0_Config7; + int64_t CP0_Config7_rw_bitmask; +#define CP0C7_NAPCGEN 2 +#define CP0C7_UNIMUEN 1 +#define CP0C7_VFPUCGEN 0 uint64_t CP0_LLAddr; uint64_t CP0_MAAR[MIPS_MAAR_MAX]; int32_t CP0_MAARI; diff --git a/target/mips/internal.h b/target/mips/internal.h index 684356e..7f159a9 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -36,7 +36,9 @@ struct mips_def_t { int32_t CP0_Config5; int32_t CP0_Config5_rw_bitmask; int32_t CP0_Config6; + int32_t CP0_Config6_rw_bitmask; int32_t CP0_Config7; + int32_t CP0_Config7_rw_bitmask; target_ulong CP0_LLAddr_rw_bitmask; int CP0_LLAddr_shift; int32_t SYNCI_Step; diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index a831bb4..0c12910 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -15,7 +15,7 @@ * ------------------------------------------------ */ /* - * bits 0-31: MIPS base instruction sets + * bits 0-23: MIPS base instruction sets */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL @@ -34,30 +34,33 @@ #define ISA_MIPS64R6 0x0000000000004000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL /* - * bits 32-47: MIPS ASEs + * bits 24-39: MIPS ASEs */ -#define ASE_MIPS16 0x0000000100000000ULL -#define ASE_MIPS3D 0x0000000200000000ULL -#define ASE_MDMX 0x0000000400000000ULL -#define ASE_DSP 0x0000000800000000ULL -#define ASE_DSP_R2 0x0000001000000000ULL -#define ASE_DSP_R3 0x0000002000000000ULL -#define ASE_MT 0x0000004000000000ULL -#define ASE_SMARTMIPS 0x0000008000000000ULL -#define ASE_MICROMIPS 0x0000010000000000ULL -#define ASE_MSA 0x0000020000000000ULL +#define ASE_MIPS16 0x0000000001000000ULL +#define ASE_MIPS3D 0x0000000002000000ULL +#define ASE_MDMX 0x0000000004000000ULL +#define ASE_DSP 0x0000000008000000ULL +#define ASE_DSP_R2 0x0000000010000000ULL +#define ASE_DSP_R3 0x0000000020000000ULL +#define ASE_MT 0x0000000040000000ULL +#define ASE_SMARTMIPS 0x0000000080000000ULL +#define ASE_MICROMIPS 0x0000000100000000ULL +#define ASE_MSA 0x0000000200000000ULL /* - * bits 48-55: vendor-specific base instruction sets + * bits 40-51: vendor-specific base instruction sets */ -#define INSN_LOONGSON2E 0x0001000000000000ULL -#define INSN_LOONGSON2F 0x0002000000000000ULL -#define INSN_VR54XX 0x0004000000000000ULL -#define INSN_R5900 0x0008000000000000ULL +#define INSN_VR54XX 0x0000010000000000ULL +#define INSN_R5900 0x0000020000000000ULL +#define INSN_LOONGSON2E 0x0000040000000000ULL +#define INSN_LOONGSON2F 0x0000080000000000ULL +#define INSN_LOONGSON3A 0x0000100000000000ULL /* - * bits 56-63: vendor-specific ASEs + * bits 52-63: vendor-specific ASEs */ -#define ASE_MMI 0x0100000000000000ULL -#define ASE_MXU 0x0200000000000000ULL +#define ASE_MMI 0x0010000000000000ULL +#define ASE_MXU 0x0020000000000000ULL +#define ASE_LMMI 0x0040000000000000ULL +#define ASE_LEXT 0x0080000000000000ULL /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) @@ -94,6 +97,8 @@ /* Wave Computing: "nanoMIPS" */ #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) +#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A) + /* * Strictly follow the architecture standard: * - Disallow "special" instruction handling for PMON/SPIM. diff --git a/target/mips/lmi_helper.c b/target/mips/lmmi_helper.c similarity index 100% rename from target/mips/lmi_helper.c rename to target/mips/lmmi_helper.c diff --git a/target/mips/translate.c b/target/mips/translate.c index 25b595a..2caf4cb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Config5 = env->cpu_model->CP0_Config5; env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; env->CP0_Config6 = env->cpu_model->CP0_Config6; + env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; env->CP0_Config7 = env->cpu_model->CP0_Config7; + env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask << env->cpu_model->CP0_LLAddr_shift; env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index 6d145a9..ffae10d 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -802,6 +802,92 @@ const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "Loongson-3A1000", + .CP0_PRid = 0x6305, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) | + (3 << CP0C2_SA), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x74D8FFFF, + .CP0_PageGrain = (1 << CP0PG_ELPA), + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | + (0x1 << FCR0_D) | (0x1 << FCR0_S), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 42, + .PABITS = 48, + .insn_flags = CPU_LOONGSON3A, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-3A4000", + .CP0_PRid = 0x14C000, + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) | + (15 << CP0C2_SA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | + (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist), + .CP0_Config4_rw_bitmask = 0, + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists), + .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), + .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) | + (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) | + (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF), + .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) | + (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) | + (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) | + (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) | + (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) | + (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) | + (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) | + (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) | + (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) | + (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) | + (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) | + (1 << CP0C6_DATAPREF), + .CP0_Config7 = 0, + .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) | + (1 << CP0C7_VFPUCGEN), + .CP0_LLAddr_rw_bitmask = 1, + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x7DDBFFFF, + .CP0_PageGrain = (1 << CP0PG_ELPA), + .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | + (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | + (0x1 << FCR0_D) | (0x1 << FCR0_S), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, + .SEGBITS = 48, + .PABITS = 48, + .insn_flags = CPU_LOONGSON3A, + .mmu_type = MMU_TYPE_R4000, + }, + { /* A generic CPU providing MIPS64 DSP R2 ASE features. FIXME: Eventually this should be replaced by a real CPU model. */ .name = "mips64dspr2", diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs index 91eb691..b820b3b 100644 --- a/target/mips/Makefile.objs +++ b/target/mips/Makefile.objs @@ -1,6 +1,6 @@ obj-y += translate.o cpu.o gdbstub.o helper.o obj-y += op_helper.o cp0_helper.o fpu_helper.o -obj-y += dsp_helper.o lmi_helper.o msa_helper.o +obj-y += dsp_helper.o lmmi_helper.o msa_helper.o obj-$(CONFIG_SOFTMMU) += mips-semi.o obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o obj-$(CONFIG_KVM) += kvm.o From patchwork Sun Jun 7 19:46:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 11592201 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50AF513B1 for ; Sun, 7 Jun 2020 20:06:40 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 259E2206F6 for ; Sun, 7 Jun 2020 20:06:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DpTgdNVk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 259E2206F6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:52404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ji1Z1-0001GH-EH for patchwork-qemu-devel@patchwork.kernel.org; Sun, 07 Jun 2020 16:06:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ji1Fk-0003zc-8q for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:45 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:50925) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ji1Fj-0004nd-8y for qemu-devel@nongnu.org; Sun, 07 Jun 2020 15:46:43 -0400 Received: by mail-wm1-x335.google.com with SMTP id l17so2112506wmj.0 for ; Sun, 07 Jun 2020 12:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ujyzI6PK0Cj6j4urUhXNN+eZBMUkCinKRwasIhMry7Y=; b=DpTgdNVkT5/xWgXDIYHzSexX0GMMVYEn/MexXB+mesI9PxfNdwFUsY+XXY58sqcTEN iAV05BIzbvNRIbxxOyHqjy3DpsCdSzvZ1HdemNWmiHOpc52kpZCGn8miXTSLbkrhi7P7 gjY6kJ77HsZSn7fue1ViUer1XWNMlvoVxvIz0pbAsajuthkDyQsV3zL/LABa6bkoJdZP 68pfjmYpGxv13jzWNUSSpDjtPmGhSYscBbf1ZzAkQjXsOg7/nkwgcE0CMaXkGtsLEw5h I5e8Uz8qQXEV1Dl3jodj2l13paiPoO7OxQjdMVvit5sF2ruqvDRO9wjcU57/sRam1352 r5tA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ujyzI6PK0Cj6j4urUhXNN+eZBMUkCinKRwasIhMry7Y=; b=q6p2oBwvhiYKjv4m4xYNKH0CkF4r8rpPFSuOVo9yHWQwy78UwWCDBeHlatdiWyi9aN ivhFNxXsUUiSlAh2KtCUDik+weCFu196qqDn97iZ2CM3XeZI/OmC/RoYQDI37hRlpLGs 1m2zj6amvinoqIesyEOQVklbaXD1mpVKMxEwyVM+WwYowpHjBoms6fp6tX/xP1O7QdcS 6kFejvMxbx8Uj9Tt4TYdv/TG2z5Dpm4gZU6U3pd9VB/805o8VzxhvSQDJmUIKzZ6avER dOX1atulUlyI54NRBk2gKwmMvil2FmGRyb0WOP8MFEnPzd1FIbGfpeTHqMXeFunRxz4X 6z0Q== X-Gm-Message-State: AOAM532697DH7lo91USiNaAsB1DbWTpHP3I+yph/NcrmHlyCccu4M/S1 nAT654uACynFHMv5fcGcIFLx6g6A X-Google-Smtp-Source: ABdhPJzyMKNchnoSpWFrBc+b+POFfslevcnf194RJ2XBGey3u9wShmHUnr9rvw9YMkwRP4WHO2MAxQ== X-Received: by 2002:a1c:a901:: with SMTP id s1mr13838370wme.66.1591559201371; Sun, 07 Jun 2020 12:46:41 -0700 (PDT) Received: from rtrkw774-lin.syrmia.com ([46.240.135.226]) by smtp.gmail.com with ESMTPSA id u130sm21091339wmg.32.2020.06.07.12.46.40 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Jun 2020 12:46:41 -0700 (PDT) From: Aleksandar Markovic To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 21/21] target/mips: Enable hardware page table walker and CMGCR features for P5600 Date: Sun, 7 Jun 2020 21:46:25 +0200 Message-Id: <1591559185-31287-22-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1591559185-31287-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x335.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Andrea Oliveri Enable hardware page table walker and CMGCR features for P5600 that supports both. Signed-off-by: Andrea Oliveri Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Message-Id: --- target/mips/translate_init.inc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c index ffae10d..637cacc 100644 --- a/target/mips/translate_init.inc.c +++ b/target/mips/translate_init.inc.c @@ -366,7 +366,7 @@ const mips_def_t mips_defs[] = }, { /* FIXME: - * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL + * Config3: VZ, CTXTC, CDMM, TL * Config4: MMUExtDef * Config5: MRP * FIR(FCR0): Has2008 @@ -380,10 +380,11 @@ const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_FP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | + (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | - (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | - (1 << CP0C3_VInt), + (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_LPA) | (1 << CP0C3_VInt), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | (0x1c << CP0C4_KScrExist), .CP0_Config4_rw_bitmask = 0,