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Thu, 11 Jun 2020 11:55:07 +0000 From: Bertrand Marquis To: xen-devel@lists.xenproject.org Subject: [PATCH] xen/arm: Add arm Neoverse N1 processor Date: Thu, 11 Jun 2020 12:54:51 +0100 Message-Id: <5d99ae7a1432152e25d063c634e1e7292ab988aa.1591806668.git.bertrand.marquis@arm.com> X-Mailer: git-send-email 2.17.1 X-ClientProxiedBy: DM5PR21CA0053.namprd21.prod.outlook.com (2603:10b6:3:129::15) To DB7PR08MB3689.eurprd08.prod.outlook.com (2603:10a6:10:79::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from e109506-lin.cambridge.arm.com (217.140.106.54) by DM5PR21CA0053.namprd21.prod.outlook.com (2603:10b6:3:129::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3109.0 via Frontend Transport; Thu, 11 Jun 2020 11:55:05 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [217.140.106.54] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e7f51b4b-81b1-4bbf-d411-08d80dfe4d30 X-MS-TrafficTypeDiagnostic: DB7PR08MB3707:|AM0PR08MB4114: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:439;OLM:439; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB4114 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Volodymyr Babchuk , nd@arm.com, Julien Grall , Stefano Stabellini Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add MIDR and CPU part numbers for Arm Neoverse N1 processor Signed-off-by: Bertrand Marquis --- xen/include/asm-arm/processor.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index aa642e3ab2..3ca67f8157 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -58,6 +58,7 @@ #define ARM_CPU_PART_CORTEX_A73 0xD09 #define ARM_CPU_PART_CORTEX_A75 0xD0A #define ARM_CPU_PART_CORTEX_A76 0xD0B +#define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A12) #define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17) @@ -68,6 +69,7 @@ #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) +#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) /* MPIDR Multiprocessor Affinity Register */ #define _MPIDR_UP (30)