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Thu, 11 Jun 2020 21:48:37 +0000 Subject: [PATCH 1/3] KVM: X86: Move handling of INVPCID types to x86 From: Babu Moger To: wanpengli@tencent.com, joro@8bytes.org, x86@kernel.org, sean.j.christopherson@intel.com, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, pbonzini@redhat.com, vkuznets@redhat.com, tglx@linutronix.de, jmattson@google.com Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Date: Thu, 11 Jun 2020 16:48:35 -0500 Message-ID: <159191211555.31436.7157754769653935735.stgit@bmoger-ubuntu> In-Reply-To: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> References: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> User-Agent: StGit/0.17.1-dirty X-ClientProxiedBy: DM6PR14CA0043.namprd14.prod.outlook.com (2603:10b6:5:18f::20) To SN1PR12MB2560.namprd12.prod.outlook.com (2603:10b6:802:26::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [127.0.1.1] (165.204.77.1) by DM6PR14CA0043.namprd14.prod.outlook.com (2603:10b6:5:18f::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3088.18 via Frontend Transport; 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So, move the code to common x86.c. Signed-off-by: Babu Moger --- arch/x86/kvm/vmx/vmx.c | 78 +----------------------------------------- arch/x86/kvm/x86.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.h | 2 + 3 files changed, 92 insertions(+), 77 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 170cc76a581f..d9c35f337da6 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5477,29 +5477,15 @@ static int handle_invpcid(struct kvm_vcpu *vcpu) { u32 vmx_instruction_info; unsigned long type; - bool pcid_enabled; gva_t gva; - struct x86_exception e; - unsigned i; - unsigned long roots_to_free = 0; struct { u64 pcid; u64 gla; } operand; - if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { - kvm_queue_exception(vcpu, UD_VECTOR); - return 1; - } - vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); - if (type > 3) { - kvm_inject_gp(vcpu, 0); - return 1; - } - /* According to the Intel instruction reference, the memory operand * is read even if it isn't needed (e.g., for type==all) */ @@ -5508,69 +5494,7 @@ static int handle_invpcid(struct kvm_vcpu *vcpu) sizeof(operand), &gva)) return 1; - if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { - kvm_inject_emulated_page_fault(vcpu, &e); - return 1; - } - - if (operand.pcid >> 12 != 0) { - kvm_inject_gp(vcpu, 0); - return 1; - } - - pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); - - switch (type) { - case INVPCID_TYPE_INDIV_ADDR: - if ((!pcid_enabled && (operand.pcid != 0)) || - is_noncanonical_address(operand.gla, vcpu)) { - kvm_inject_gp(vcpu, 0); - return 1; - } - kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); - return kvm_skip_emulated_instruction(vcpu); - - case INVPCID_TYPE_SINGLE_CTXT: - if (!pcid_enabled && (operand.pcid != 0)) { - kvm_inject_gp(vcpu, 0); - return 1; - } - - if (kvm_get_active_pcid(vcpu) == operand.pcid) { - kvm_mmu_sync_roots(vcpu); - kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); - } - - for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) - if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) - == operand.pcid) - roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); - - kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); - /* - * If neither the current cr3 nor any of the prev_roots use the - * given PCID, then nothing needs to be done here because a - * resync will happen anyway before switching to any other CR3. - */ - - return kvm_skip_emulated_instruction(vcpu); - - case INVPCID_TYPE_ALL_NON_GLOBAL: - /* - * Currently, KVM doesn't mark global entries in the shadow - * page tables, so a non-global flush just degenerates to a - * global flush. If needed, we could optimize this later by - * keeping track of global entries in shadow page tables. - */ - - /* fall-through */ - case INVPCID_TYPE_ALL_INCL_GLOBAL: - kvm_mmu_unload(vcpu); - return kvm_skip_emulated_instruction(vcpu); - - default: - BUG(); /* We have already checked above that type <= 3 */ - } + return kvm_handle_invpcid_types(vcpu, gva, type); } static int handle_pml_full(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9e41b5135340..13373359608c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -72,6 +72,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -10714,6 +10715,94 @@ u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu) } EXPORT_SYMBOL_GPL(kvm_spec_ctrl_valid_bits); +int kvm_handle_invpcid_types(struct kvm_vcpu *vcpu, gva_t gva, + unsigned long type) +{ + unsigned long roots_to_free = 0; + struct x86_exception e; + bool pcid_enabled; + unsigned i; + struct { + u64 pcid; + u64 gla; + } operand; + + if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { + kvm_queue_exception(vcpu, UD_VECTOR); + return 1; + } + + if (type > 3) { + kvm_inject_gp(vcpu, 0); + return 1; + } + + if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { + kvm_inject_emulated_page_fault(vcpu, &e); + return 1; + } + + if (operand.pcid >> 12 != 0) { + kvm_inject_gp(vcpu, 0); + return 1; + } + + pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); + + switch (type) { + case INVPCID_TYPE_INDIV_ADDR: + if ((!pcid_enabled && (operand.pcid != 0)) || + is_noncanonical_address(operand.gla, vcpu)) { + kvm_inject_gp(vcpu, 0); + return 1; + } + kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); + return kvm_skip_emulated_instruction(vcpu); + + case INVPCID_TYPE_SINGLE_CTXT: + if (!pcid_enabled && (operand.pcid != 0)) { + kvm_inject_gp(vcpu, 0); + return 1; + } + + if (kvm_get_active_pcid(vcpu) == operand.pcid) { + kvm_mmu_sync_roots(vcpu); + kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu); + } + + for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) + if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].pgd) + == operand.pcid) + roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); + + kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); + /* + * If neither the current cr3 nor any of the prev_roots use the + * given PCID, then nothing needs to be done here because a + * resync will happen anyway before switching to any other CR3. + */ + + return kvm_skip_emulated_instruction(vcpu); + + case INVPCID_TYPE_ALL_NON_GLOBAL: + /* + * Currently, KVM doesn't mark global entries in the shadow + * page tables, so a non-global flush just degenerates to a + * global flush. If needed, we could optimize this later by + * keeping track of global entries in shadow page tables. + */ + + /* fall-through */ + case INVPCID_TYPE_ALL_INCL_GLOBAL: + kvm_mmu_unload(vcpu); + return kvm_skip_emulated_instruction(vcpu); + + default: + BUG(); /* We have already checked above that type <= 3 */ + } +} +EXPORT_SYMBOL_GPL(kvm_handle_invpcid_types); + EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 6eb62e97e59f..8e23f2705344 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -365,5 +365,7 @@ void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu); void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu); u64 kvm_spec_ctrl_valid_bits(struct kvm_vcpu *vcpu); bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu); +int kvm_handle_invpcid_types(struct kvm_vcpu *vcpu, gva_t gva, + unsigned long type); #endif From patchwork Thu Jun 11 21:48:43 2020 Content-Type: text/plain; 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Thu, 11 Jun 2020 21:48:45 +0000 Subject: [PATCH 2/3] KVM:SVM: Add extended intercept support From: Babu Moger To: wanpengli@tencent.com, joro@8bytes.org, x86@kernel.org, sean.j.christopherson@intel.com, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, pbonzini@redhat.com, vkuznets@redhat.com, tglx@linutronix.de, jmattson@google.com Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Date: Thu, 11 Jun 2020 16:48:43 -0500 Message-ID: <159191212308.31436.11785815366008795008.stgit@bmoger-ubuntu> In-Reply-To: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> References: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> User-Agent: StGit/0.17.1-dirty X-ClientProxiedBy: DM5PR11CA0002.namprd11.prod.outlook.com (2603:10b6:3:115::12) To SN1PR12MB2560.namprd12.prod.outlook.com (2603:10b6:802:26::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [127.0.1.1] (165.204.77.1) by DM5PR11CA0002.namprd11.prod.outlook.com (2603:10b6:3:115::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3088.21 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: mmVpxNVtYqjMkaytq4AbxwL8VHX7zFfANIaAyZ4h0VfXrWL3Ker32hVl+Y9TVZLog2xa4OsaPSUiLy9rob59IktjMq6IflPvsdB23rR0rtg147WE5TlKij/jXAEON5TDmlVMpQQu2yEdJVd1REEErXuklrj+AOJBynvdfXA50Hl6cwuFk75u7j0KxJjXVZoQyPFfeXNI6BJApO43vsKwotZavzfGDg2jXFdUoLuki+Uh/E2p6jClp6Tpjrgxn9/HBZ6KujaXTfKFy/bZL7u+DEeFhuReBCJwqMWMtMENBeH5okD3wxX6Yppo6wbvGr038E/7ru0qxC9hwf+maDKhg8h3/8nk060Qn0hf77+9gadcw6bt+usfW92/eRspZWIsW7/0AVWF8fdmWRDTxerfAzutLlA7Ppqi90vOb3ahXRXWWwTKFba50gleAFTbCU+6fk/mVdCz66GzD+LK0vHJh6boqx1hG19MzIVL3Hj4VYc= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4a9d8c9a-2d21-4d16-697f-08d80e5136de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2020 21:48:44.9849 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8klLjHOgqP+n+hWAZL1+6kNDV764o+bDRha577j4G5zPALIdeqbQSNAIYyesylT2 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4589 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The new intercept bits have been added in vmcb control area to support the interception of INVPCID instruction. The following bit is added to the VMCB layout control area to control intercept of INVPCID: Byte Offset Bit(s) Function 14h 2 intercept INVPCID Add the interfaces to support these extended interception. Also update the tracing for extended intercepts. AMD documentation for INVPCID feature is available at "AMD64 Architecture Programmer’s Manual Volume 2: System Programming, Pub. 24593 Rev. 3.34(or later)" The documentation can be obtained at the links below: Link: https://www.amd.com/system/files/TechDocs/24593.pdf Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/svm.h | 3 ++- arch/x86/kvm/svm/nested.c | 6 +++++- arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 18 ++++++++++++++++++ arch/x86/kvm/trace.h | 12 ++++++++---- 5 files changed, 34 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 8a1f5382a4ea..62649fba8908 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -61,7 +61,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { u32 intercept_dr; u32 intercept_exceptions; u64 intercept; - u8 reserved_1[40]; + u32 intercept_extended; + u8 reserved_1[36]; u16 pause_filter_thresh; u16 pause_filter_count; u64 iopm_base_pa; diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 8a6db11dcb43..7f6d0f2533e2 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -121,6 +121,7 @@ void recalc_intercepts(struct vcpu_svm *svm) c->intercept_dr = h->intercept_dr; c->intercept_exceptions = h->intercept_exceptions; c->intercept = h->intercept; + c->intercept_extended = h->intercept_extended; if (g->int_ctl & V_INTR_MASKING_MASK) { /* We only want the cr8 intercept bits of L1 */ @@ -142,6 +143,7 @@ void recalc_intercepts(struct vcpu_svm *svm) c->intercept_dr |= g->intercept_dr; c->intercept_exceptions |= g->intercept_exceptions; c->intercept |= g->intercept; + c->intercept_extended |= g->intercept_extended; } static void copy_vmcb_control_area(struct vmcb_control_area *dst, @@ -151,6 +153,7 @@ static void copy_vmcb_control_area(struct vmcb_control_area *dst, dst->intercept_dr = from->intercept_dr; dst->intercept_exceptions = from->intercept_exceptions; dst->intercept = from->intercept; + dst->intercept_extended = from->intercept_extended; dst->iopm_base_pa = from->iopm_base_pa; dst->msrpm_base_pa = from->msrpm_base_pa; dst->tsc_offset = from->tsc_offset; @@ -433,7 +436,8 @@ int nested_svm_vmrun(struct vcpu_svm *svm) trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff, nested_vmcb->control.intercept_cr >> 16, nested_vmcb->control.intercept_exceptions, - nested_vmcb->control.intercept); + nested_vmcb->control.intercept, + nested_vmcb->control.intercept_extended); /* Clear internal status */ kvm_clear_exception_queue(&svm->vcpu); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 9e333b91ff78..285e5e1ff518 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2801,6 +2801,7 @@ static void dump_vmcb(struct kvm_vcpu *vcpu) pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16); pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions); pr_err("%-20s%016llx\n", "intercepts:", control->intercept); + pr_err("%-20s%08x\n", "intercepts (extended):", control->intercept_extended); pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count); pr_err("%-20s%d\n", "pause filter threshold:", control->pause_filter_thresh); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 6ac4c00a5d82..935d08fac03d 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -311,6 +311,24 @@ static inline void clr_intercept(struct vcpu_svm *svm, int bit) recalc_intercepts(svm); } +static inline void set_extended_intercept(struct vcpu_svm *svm, int bit) +{ + struct vmcb *vmcb = get_host_vmcb(svm); + + vmcb->control.intercept_extended |= (1U << bit); + + recalc_intercepts(svm); +} + +static inline void clr_extended_intercept(struct vcpu_svm *svm, int bit) +{ + struct vmcb *vmcb = get_host_vmcb(svm); + + vmcb->control.intercept_extended &= ~(1U << bit); + + recalc_intercepts(svm); +} + static inline bool is_intercept(struct vcpu_svm *svm, int bit) { return (svm->vmcb->control.intercept & (1ULL << bit)) != 0; diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index b66432b015d2..5c841c42b33d 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -544,14 +544,16 @@ TRACE_EVENT(kvm_nested_vmrun, ); TRACE_EVENT(kvm_nested_intercepts, - TP_PROTO(__u16 cr_read, __u16 cr_write, __u32 exceptions, __u64 intercept), - TP_ARGS(cr_read, cr_write, exceptions, intercept), + TP_PROTO(__u16 cr_read, __u16 cr_write, __u32 exceptions, __u64 intercept, + __u32 extended), + TP_ARGS(cr_read, cr_write, exceptions, intercept, extended), TP_STRUCT__entry( __field( __u16, cr_read ) __field( __u16, cr_write ) __field( __u32, exceptions ) __field( __u64, intercept ) + __field( __u32, extended ) ), TP_fast_assign( @@ -559,11 +561,13 @@ TRACE_EVENT(kvm_nested_intercepts, __entry->cr_write = cr_write; __entry->exceptions = exceptions; __entry->intercept = intercept; + __entry->extended = extended; ), - TP_printk("cr_read: %04x cr_write: %04x excp: %08x intercept: %016llx", + TP_printk("cr_read: %04x cr_write: %04x excp: %08x intercept: %016llx" + "intercept (extended): %08x", __entry->cr_read, __entry->cr_write, __entry->exceptions, - __entry->intercept) + __entry->intercept, __entry->extended) ); /* * Tracepoint for #VMEXIT while nested From patchwork Thu Jun 11 21:48:50 2020 Content-Type: text/plain; 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Thu, 11 Jun 2020 21:48:52 +0000 Subject: [PATCH 3/3] KVM:SVM: Enable INVPCID feature on AMD From: Babu Moger To: wanpengli@tencent.com, joro@8bytes.org, x86@kernel.org, sean.j.christopherson@intel.com, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, pbonzini@redhat.com, vkuznets@redhat.com, tglx@linutronix.de, jmattson@google.com Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Date: Thu, 11 Jun 2020 16:48:50 -0500 Message-ID: <159191213022.31436.11150808867377936241.stgit@bmoger-ubuntu> In-Reply-To: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> References: <159191202523.31436.11959784252237488867.stgit@bmoger-ubuntu> User-Agent: StGit/0.17.1-dirty X-ClientProxiedBy: DM5PR2001CA0002.namprd20.prod.outlook.com (2603:10b6:4:16::12) To SN1PR12MB2560.namprd12.prod.outlook.com (2603:10b6:802:26::19) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [127.0.1.1] (165.204.77.1) by DM5PR2001CA0002.namprd20.prod.outlook.com (2603:10b6:4:16::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3088.18 via Frontend Transport; Thu, 11 Jun 2020 21:48:51 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 0a2ceafe-c592-4952-347f-08d80e513b40 X-MS-TrafficTypeDiagnostic: SA0PR12MB4589: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 0431F981D8 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PUv27XDlXbtZK/0I5Mv5PfgeAfnci+ZjySqsmM9wpDQUCzGxl2uNnh4Qe8CVufH0kukHTODqXj0fNEBm/E79YFak7NHk7MLMTxmP9AsHWhVILEeAEG+yqQN+6cZWq3HU6nA9TacCYyVJs0d58CzD14GSMu/nCWiLUwpxINzd8NPBSBqBaHdsHv3qgW7EUApXw+52NVxwdNEX3+A62HO4PzqtcnfJBTToCqR26EbmRBMPS+iuT2UDXjVUZJ9v/5UGnH8GadMjiq2mF9xCan3Qj+Q2wNp73MCQ8w2JMtF9oyfF41wgRa3Ltqps+epRWrQ0a2FEqjWwQiT866kU1pDy4VDEhBS6h7EhXO2sOquKLWnxI8EPHjZiGoJwycojcqpLXFm5bB9ls7jansrVL+/4br+d2dCdWF/2QJ6nrz9az80A/+9J9WKUKyr2FDGakKUSqUTX8TyZKN6UPr+hzmQvGg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SN1PR12MB2560.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(7916004)(4636009)(366004)(396003)(39860400002)(346002)(376002)(136003)(52116002)(33716001)(6486002)(16576012)(8936002)(2906002)(8676002)(16526019)(9686003)(7416002)(186003)(4326008)(316002)(478600001)(966005)(103116003)(44832011)(956004)(5660300002)(83380400001)(26005)(66476007)(66556008)(66946007)(86362001)(921003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: gcWGThW8fSBBNhPdruklzgpSa29ZU2qt0l5UCLJwz82jyNA48ViVMo0OrghuQSrgnQmLTtaQ5y9GpfwI/p4218zLcv99yrI1i30stIDh3MhvlBTeRSsylboomtL4f+ZHEF62lXqCiV1jy80pH0rqyfQ+9Jcv4kUTnbit4kRCuY/k0h7CfSnndy+rK9uHm3wzAjRpWYpMtgugeTwtHrO+1UYzINPqBIpvF2gUbS58MfHfADs1NUHv8XbodD2kUugGH2fWND7JnWDpGd4usd1NfQxmtKiLUldCEGUdQjXlqCQNfyKGcx2CNu/WGnP9Whbo3CNSFSERp2z39/YqNvtn7OdR0z9Fyty2zVwwpEBiXIELo+3K9BX8AGWMPuyaoiSN6qkqB/mjnSq28O9JoLko/oDedj/1AiqkbS++ZFutiNvROE5hDxRM9LhrakqkdlzSp9KIws5XfuvVQnu/Lq41/f9tWQaEiEvfiBxzMlL/D2k= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0a2ceafe-c592-4952-347f-08d80e513b40 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2020 21:48:52.3147 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: S/9W6IlG6EgSkFbJ2fQttZgsep7rw5OF7m+jqVw5825b+8n2N718QyHQ5ZMPsElg X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4589 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The following intercept is added for INVPCID instruction: Code Name Cause A2h VMEXIT_INVPCID INVPCID instruction The following bit is added to the VMCB layout control area to control intercept of INVPCID: Byte Offset Bit(s) Function 14h 2 intercept INVPCID For the guests with nested page table (NPT) support, the INVPCID feature works as running it natively. KVM does not need to do any special handling in this case. Interceptions are required in the following cases. 1. If the guest tries to disable the feature when the underlying hardware supports it. In this case hypervisor needs to report #UD. 2. When the guest is running with shadow page table enabled, in this case the hypervisor needs to handle the tlbflush based on the type of invpcid instruction type. AMD documentation for INVPCID feature is available at "AMD64 Architecture Programmer’s Manual Volume 2: System Programming, Pub. 24593 Rev. 3.34(or later)" The documentation can be obtained at the links below: Link: https://www.amd.com/system/files/TechDocs/24593.pdf Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/svm.h | 4 ++++ arch/x86/include/uapi/asm/svm.h | 2 ++ arch/x86/kvm/svm/svm.c | 42 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 62649fba8908..6488094f67fa 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -55,6 +55,10 @@ enum { INTERCEPT_RDPRU, }; +/* Extended Intercept bits */ +enum { + INTERCEPT_INVPCID = 2, +}; struct __attribute__ ((__packed__)) vmcb_control_area { u32 intercept_cr; diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/svm.h index 2e8a30f06c74..522d42dfc28c 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -76,6 +76,7 @@ #define SVM_EXIT_MWAIT_COND 0x08c #define SVM_EXIT_XSETBV 0x08d #define SVM_EXIT_RDPRU 0x08e +#define SVM_EXIT_INVPCID 0x0a2 #define SVM_EXIT_NPF 0x400 #define SVM_EXIT_AVIC_INCOMPLETE_IPI 0x401 #define SVM_EXIT_AVIC_UNACCELERATED_ACCESS 0x402 @@ -171,6 +172,7 @@ { SVM_EXIT_MONITOR, "monitor" }, \ { SVM_EXIT_MWAIT, "mwait" }, \ { SVM_EXIT_XSETBV, "xsetbv" }, \ + { SVM_EXIT_INVPCID, "invpcid" }, \ { SVM_EXIT_NPF, "npf" }, \ { SVM_EXIT_AVIC_INCOMPLETE_IPI, "avic_incomplete_ipi" }, \ { SVM_EXIT_AVIC_UNACCELERATED_ACCESS, "avic_unaccelerated_access" }, \ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 285e5e1ff518..82d974338f68 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -813,6 +813,11 @@ static __init void svm_set_cpu_caps(void) if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); + + /* Enable INVPCID if both PCID and INVPCID enabled */ + if (boot_cpu_has(X86_FEATURE_PCID) && + boot_cpu_has(X86_FEATURE_INVPCID)) + kvm_cpu_cap_set(X86_FEATURE_INVPCID); } static __init int svm_hardware_setup(void) @@ -1099,6 +1104,17 @@ static void init_vmcb(struct vcpu_svm *svm) clr_intercept(svm, INTERCEPT_PAUSE); } + /* + * Intercept INVPCID instruction only if shadow page table is + * enabled. Interception is not required with nested page table. + */ + if (boot_cpu_has(X86_FEATURE_INVPCID)) { + if (!npt_enabled) + set_extended_intercept(svm, INTERCEPT_INVPCID); + else + clr_extended_intercept(svm, INTERCEPT_INVPCID); + } + if (kvm_vcpu_apicv_active(&svm->vcpu)) avic_init_vmcb(svm); @@ -2715,6 +2731,23 @@ static int mwait_interception(struct vcpu_svm *svm) return nop_interception(svm); } +static int invpcid_interception(struct vcpu_svm *svm) +{ + struct kvm_vcpu *vcpu = &svm->vcpu; + unsigned long type; + gva_t gva; + + /* + * For an INVPCID intercept: + * EXITINFO1 provides the linear address of the memory operand. + * EXITINFO2 provides the contents of the register operand. + */ + type = svm->vmcb->control.exit_info_2; + gva = svm->vmcb->control.exit_info_1; + + return kvm_handle_invpcid_types(vcpu, gva, type); +} + static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { [SVM_EXIT_READ_CR0] = cr_interception, [SVM_EXIT_READ_CR3] = cr_interception, @@ -2777,6 +2810,7 @@ static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = { [SVM_EXIT_MWAIT] = mwait_interception, [SVM_EXIT_XSETBV] = xsetbv_interception, [SVM_EXIT_RDPRU] = rdpru_interception, + [SVM_EXIT_INVPCID] = invpcid_interception, [SVM_EXIT_NPF] = npf_interception, [SVM_EXIT_RSM] = rsm_interception, [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception, @@ -3562,6 +3596,14 @@ static void svm_cpuid_update(struct kvm_vcpu *vcpu) svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) && guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS); + /* + * Intercept INVPCID instruction if the baremetal has the support + * but the guest doesn't claim the feature. + */ + if (boot_cpu_has(X86_FEATURE_INVPCID) && + !guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) + set_extended_intercept(svm, INTERCEPT_INVPCID); + if (!kvm_vcpu_apicv_active(vcpu)) return;