From patchwork Mon Jun 15 21:05:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605861 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C623618 for ; Mon, 15 Jun 2020 21:07:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2474020C09 for ; Mon, 15 Jun 2020 21:07:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aUUBpWle" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731476AbgFOVGS (ORCPT ); Mon, 15 Jun 2020 17:06:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731170AbgFOVGR (ORCPT ); Mon, 15 Jun 2020 17:06:17 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3361AC061A0E; Mon, 15 Jun 2020 14:06:17 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id gl26so18940875ejb.11; Mon, 15 Jun 2020 14:06:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=70CIEcja2iyHnz/U1cQIr7P6UHMVY2e5pchQ5AbwA7I=; b=aUUBpWlet8KP9y4RqVMd1KAiGNAaB8U+KEIa068xc0e9oUZd8fBfHPvXaLp2M3Q750 I4nz2LNF5t2WXAFcOvOk+KioXYc0pV461xQRArmz2DtfEpDgMvCMjHNqW/t0sKaF0ZPh 7vY9N/YXd7e6tWdejjLfqIt+K+wGZx672tQC2R+ht+FgTMtAA0Q+7iEcyVU1l5Gk8oss TQlfb6chlnO+6+HZU/tarSnXSf0L+Ds7SF4O0A2aNcEjcnWWK1TKDinXSQ3COeGU3N4Y YiWx0msSf30KIvQEYrAeDZUdF8Wwc0i8A0zjIo/BAaAlar+N403YV7QuSA9kcXSFNT5m A0/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=70CIEcja2iyHnz/U1cQIr7P6UHMVY2e5pchQ5AbwA7I=; b=BPKvGJJ+dNAsUlMtuBoRfM85nl55SNMwTp767ve0nA4W8JfRetHlbDUGsT0imn6t/W W9aM7mMkXGgnZ+WRyAXKvGSB+Q2vSBUX4+2PSHsfarMFcH2YZp7V716QRrsPGirwq9x5 XGSx1v2DQxju6a9iu5ILwLzrF72DfThmKojdUtnsfhKJoLTmgU1g7jn2mImtBk/8XMNP 5k49K+p0dZezXIOF4+HhvX6IJlH/n1NGHCo0/p1ADaaggBp0XDiynfaLDHeXrdOtdIAW tPtadQzgFxa5GO8tTqxSujhua9/ytMocuDWo8Ac84RdbIMU+0lXT26VRbKHaoua6WCCN dhCA== X-Gm-Message-State: AOAM531whbldT1zyG/7IZvuLLUzhmsmFlSqMZJuv9KzBm36KdWEH/44v hi5NgcWzaGjAZvrrrFoOpTA= X-Google-Smtp-Source: ABdhPJyRrjPzruVe1Gxw/CIlAVa1L7yOXOSXYZcwcm/+5ZYvmlysatqkcHsdszCM9Ngh9OxTvuARMg== X-Received: by 2002:a17:907:369:: with SMTP id rs9mr26749297ejb.187.1592255175887; Mon, 15 Jun 2020 14:06:15 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:15 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Sham Muthayyan , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 01/12] PCI: qcom: Add missing ipq806x clocks in PCIe driver Date: Mon, 15 Jun 2020 23:05:57 +0200 Message-Id: <20200615210608.21469-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Aux and Ref clk are missing in PCIe qcom driver. Add support for this optional clks for ipq8064/apq8064 SoC. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5ea527a6bd9f..4bf93ab8c7a7 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 { struct clk *iface_clk; struct clk *core_clk; struct clk *phy_clk; + struct clk *aux_clk; + struct clk *ref_clk; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_clk)) return PTR_ERR(res->phy_clk); + res->aux_clk = devm_clk_get_optional(dev, "aux"); + if (IS_ERR(res->aux_clk)) + return PTR_ERR(res->aux_clk); + + res->ref_clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(res->ref_clk)) + return PTR_ERR(res->ref_clk); + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) return PTR_ERR(res->pci_reset); @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_assert_ahb; } + ret = clk_prepare_enable(res->core_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable core clock\n"); + goto err_clk_core; + } + ret = clk_prepare_enable(res->phy_clk); if (ret) { dev_err(dev, "cannot prepare/enable phy clock\n"); goto err_clk_phy; } - ret = clk_prepare_enable(res->core_clk); + ret = clk_prepare_enable(res->aux_clk); if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; + dev_err(dev, "cannot prepare/enable aux clock\n"); + goto err_clk_aux; + } + + ret = clk_prepare_enable(res->ref_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable ref clock\n"); + goto err_clk_ref; } ret = reset_control_deassert(res->ahb_reset); @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; err_deassert_ahb: - clk_disable_unprepare(res->core_clk); -err_clk_core: + clk_disable_unprepare(res->ref_clk); +err_clk_ref: + clk_disable_unprepare(res->aux_clk); +err_clk_aux: clk_disable_unprepare(res->phy_clk); err_clk_phy: + clk_disable_unprepare(res->core_clk); +err_clk_core: clk_disable_unprepare(res->iface_clk); err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); From patchwork Mon Jun 15 21:05:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605857 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C514960D for ; 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:17 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 02/12] dt-bindings: PCI: qcom: Add missing clks Date: Mon, 15 Jun 2020 23:05:58 +0200 Message-Id: <20200615210608.21469-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document missing clks used in ipq8064 SoC. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 981b4de12807..becdbdc0fffa 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -90,6 +90,8 @@ Definition: Should contain the following entries - "core" Clocks the pcie hw block - "phy" Clocks the pcie PHY block + - "aux" Clocks the pcie AUX block + - "ref" Clocks the pcie ref block - clock-names: Usage: required for apq8084/ipq4019 Value type: @@ -277,8 +279,10 @@ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ clocks = <&gcc PCIE_A_CLK>, <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>; - clock-names = "core", "iface", "phy"; + <&gcc PCIE_PHY_CLK>, + <&gcc PCIE_AUX_CLK>, + <&gcc PCIE_ALT_REF_CLK>; + clock-names = "core", "iface", "phy", "aux", "ref"; resets = <&gcc PCIE_ACLK_RESET>, <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, From patchwork Mon Jun 15 21:05:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605851 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDDBD60D for ; Mon, 15 Jun 2020 21:07:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B442A2078E for ; Mon, 15 Jun 2020 21:07:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="VnCzQmlY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731642AbgFOVGY (ORCPT ); Mon, 15 Jun 2020 17:06:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730995AbgFOVGW (ORCPT ); Mon, 15 Jun 2020 17:06:22 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12729C061A0E; Mon, 15 Jun 2020 14:06:22 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id q19so18970821eja.7; Mon, 15 Jun 2020 14:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5eNioSzRAf4AQLGTb/kkvDjy6KEFEuRvm0x+F0ZbzF4=; b=VnCzQmlYctVsVQYjJ3axxM4glTS3Y57J4kX5qmIoNZsFFozHmBkfW4nEOA79JF3d9D 6fnR/CnokLIRnFZNx/dzHU+Gy9pxjy7VlYaMHxeNT+whVWqXj5BbIDQn4RsOnoSOE8Pa cKG8IU42NAf/obvMtS6Hxh02mU6M8JWZmFV4UbO/6GeiOJP9K9Y0m65i4qKbrAZLGOcM GTWOmH8DkbUSfcmRUgKj5Evr8sCpEfWAopHzxrlWSSidfraGW4rQ7berGqCjem0ifeZR 58dzU+6n37qCxwrHPnqUHwvU1k1UKz3RtNdLvm27kDa+cJCiFFCGjOs/nxH03/xlvOoa 1z/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5eNioSzRAf4AQLGTb/kkvDjy6KEFEuRvm0x+F0ZbzF4=; b=I77JeEUMFbHCC95oqlMSivEyfi6pFzitnNYzHmw1fT4VX/5Lm1lYq24H+KxeoExs9y z0KfBaqAHgtJiKi9JVenA1y8zLVk6XurUVs/wvGKY3gomlrkOKWTfk0U1cxj5AFwEw2h Uld4pNSeNxVNVZG64R3oqRGWyZ6/+8A/H27PXWpgyoi4YgFwuPhZA26N2iwgpj3WgV5B x8UvzZfc1o+/gtpFUM7vHTbXkHPqSDHIQ17Mw7YgmRamNSg3vwd8rzS6qwe69oLeTS2c cvZz03iglrzu0sPewktPVm44ze6Frj49E7X617GmzC0P4rleOrduEyoj8383H8l5XIhp wnNA== X-Gm-Message-State: AOAM5311M5TyFehqwftTAhM/G2YxoAXaRWdJELBdBnizDwT88Hd+djfW CUTSrNZKYUxaD6VYi7nJwcc= X-Google-Smtp-Source: ABdhPJx0w5iJ+psNKUBmKdjkP5rzWezGYq/1AKAJFRbM5LtcJzvH29cNOapLfGBx67eisahRPqxZKA== X-Received: by 2002:a17:906:fcb7:: with SMTP id qw23mr25865593ejb.229.1592255180585; Mon, 15 Jun 2020 14:06:20 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:19 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Abhishek Sahu , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 03/12] PCI: qcom: Change duplicate PCI reset to phy reset Date: Mon, 15 Jun 2020 23:05:59 +0200 Message-Id: <20200615210608.21469-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Abhishek Sahu The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Signed-off-by: Abhishek Sahu Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4bf93ab8c7a7..4512c2c5f61c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + clk_disable_unprepare(res->phy_clk); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); - reset_control_assert(res->pci_reset); + reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); clk_disable_unprepare(res->aux_clk); clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_clk_core; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); @@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_deassert_ahb; + } + /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) err_clk_ref: clk_disable_unprepare(res->aux_clk); err_clk_aux: - clk_disable_unprepare(res->phy_clk); -err_clk_phy: clk_disable_unprepare(res->core_clk); err_clk_core: clk_disable_unprepare(res->iface_clk); From patchwork Mon Jun 15 21:06:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605809 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9469E13B1 for ; Mon, 15 Jun 2020 21:06:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7DD6520C56 for ; Mon, 15 Jun 2020 21:06:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QdvSU7m/" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731716AbgFOVGZ (ORCPT ); Mon, 15 Jun 2020 17:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730995AbgFOVGY (ORCPT ); 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:22 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Rob Herring , Philipp Zabel , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 04/12] PCI: qcom: Add missing reset for ipq806x Date: Mon, 15 Jun 2020 23:06:00 +0200 Message-Id: <20200615210608.21469-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring Reviewed-by: Philipp Zabel --- drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4512c2c5f61c..4dab5ef630cc 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot deassert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0); From patchwork Mon Jun 15 21:06:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605849 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE47960D for ; Mon, 15 Jun 2020 21:07:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C2785208FE for ; Mon, 15 Jun 2020 21:07:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="A+VMjeDy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731106AbgFOVGa (ORCPT ); Mon, 15 Jun 2020 17:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731561AbgFOVG2 (ORCPT ); Mon, 15 Jun 2020 17:06:28 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4707C061A0E; Mon, 15 Jun 2020 14:06:26 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id g1so12562126edv.6; Mon, 15 Jun 2020 14:06:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9tnxzeLrebInQm8RJ3dhvveUmV0mvvYaTXd5mudNeVI=; b=A+VMjeDys94CDeGa8so1cw8SK6kOKajtWmtZo61PfDLIDos9vKPvMheTSEtwpPOMDq fOtAu1eaWEYYD+13Rj1HONQ0HzKBHo94pLkaRqApcbWqpgnMzGRQPRiFhPK+XOoH8nHR WOrKiWMvkdzY1Zk0uWXH/n9niJY4zCJL3o8hH6OBhFSwTbk4k8wRLoiY8Ea92htc6SzG 1KpSu4nRqa4yIKewL4CLxH62EHKSgifTk3w+44lmiWcW9UiJlfkDPJpUCjcy2L6vDSsU 6aKcp7+utM7lKOhdZHUDXOPagPy739DmtTcu56696qu7XFFrAXVyeEXrLvFHRul7sIAy vFHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9tnxzeLrebInQm8RJ3dhvveUmV0mvvYaTXd5mudNeVI=; b=Crca/0Qhz1pY+pVB0tH9OBytST4Kvqk2FJ9UA7phvLSbtI1Ldnz9gEIGrXJQFIUkRv jpYQ9X4bix91Qsk/4+RCBv6BKTowPYn59LNvXzOcW2e2fA9OTfBpNSaeNUB/5FT/M7u3 S10txvHaK7E6FS4YK/obyfQPI5UlL6+9ldeHsT3pMhbckfpJnUZV3hqno/P3b5+uSz27 9Yl5H/gvMildniyU9f2dXVzaLDD7hC2wTb+XMHmna4MOvoBJzrAjXX+IzEO/OYjjCc41 DN4Vc5l1+0K/JRfe3slD71KC9yLTpBEBwkLd07+CFfr8oFFiFcdFccyjiDHz2G47aGfL IRhA== X-Gm-Message-State: AOAM53276eBlvgvi0zhxUhX0Bgw4WxhKIyoaJytcQ2kRJztdd911pZTj P0BgMeX1Poj9VzBNC7PnTSc= X-Google-Smtp-Source: ABdhPJwycVWBkKUbT79y/6ixRAVaDmgCQO3Wcl78/yG0bB8Fs0uCTlcD0tWDy3ht0ECl+4iTADafXA== X-Received: by 2002:a05:6402:3c2:: with SMTP id t2mr25485628edw.361.1592255185458; Mon, 15 Jun 2020 14:06:25 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:24 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 05/12] dt-bindings: PCI: qcom: Add ext reset Date: Mon, 15 Jun 2020 23:06:01 +0200 Message-Id: <20200615210608.21469-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document ext reset used in ipq8064 SoC by qcom PCIe driver. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index becdbdc0fffa..6efcef040741 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,7 @@ - "pwr" PWR reset - "ahb" AHB reset - "phy_ahb" PHY AHB reset + - "ext" EXT reset - reset-names: Usage: required for ipq8074 @@ -287,8 +288,9 @@ <&gcc PCIE_HCLK_RESET>, <&gcc PCIE_POR_RESET>, <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy"; + <&gcc PCIE_PHY_RESET>, + <&gcc PCIE_EXT_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; pinctrl-0 = <&pcie_pins_default>; pinctrl-names = "default"; }; From patchwork Mon Jun 15 21:06:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605811 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA28C13B1 for ; Mon, 15 Jun 2020 21:06:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9D33820739 for ; Mon, 15 Jun 2020 21:06:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UFAgJGy1" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731729AbgFOVGa (ORCPT ); Mon, 15 Jun 2020 17:06:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730995AbgFOVG3 (ORCPT ); Mon, 15 Jun 2020 17:06:29 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C8F5C08C5C2; Mon, 15 Jun 2020 14:06:29 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id y13so18995494eju.2; Mon, 15 Jun 2020 14:06:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7DFifidWmIfqxPGThJs01uWYMYz3TIPc9ydTq8/XkuQ=; b=UFAgJGy1tM/qKFh3ShK0D4wmnZRDepfHos6eqaeYrVd62Ushgr8wWgoAFEi37bU5GP eRXjwiR/EHtON/BGWAy8+c/J69ibQJYAAGpFyK6eOfiitEYtH/lqlaCOyRdWSUlSRgxP zYQlUc4KPYPhHKQ61ECySddfCvIwJ3BdjIJBQuCmF/Z1vU924dbi5WnrEswd3mCQMY0n eq+Kp3j+Jd1KM5ksJYbMEj+5Yztc3kPhAl7fal+qScF/efPsG+YLdzsnJjv4bDCcJEx6 LgYgj5sMtmywKPfuUMO9AeHTPQmoC31sjvQ7ccbUgmYpnFE6yu861b0uFeMH19zQex+r fiFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7DFifidWmIfqxPGThJs01uWYMYz3TIPc9ydTq8/XkuQ=; b=YL8HPUCR3laqkakRGCbFkf3/smNSEPvYR7urvud7oqFnsgUkAxAhwlyAIohpsuERas QRbj90pwNDbdbNIOmFbXJJdMmb/4lPr14yBG8yOc6/hyBH13AtOkVL4fz1SSrfSb1QiB LnucMlGxeAhYSrfsnz0/hqE9uoPwGf294YO2rXSPSbNe5c3RHIL7ZWkLBQ3WteZZ1XfN ZrqhcnZ1wBKVZFeTngrYkquoXXahsjlza+7Sgz2EOOg58JGgocNOlaJ+4OwXft3Bd+vU 54bCbjD9n1t7aPotAFJMyIbBZfO6HZFveNomKvomTU884dUPg8Fx3LI1u/899WoyJ9Ag t4yg== X-Gm-Message-State: AOAM5308N/BSvus48roRW1xBNRV4apdKsYbvpd9/Yyq+O1gpPxzGIK31 NBmOSJ6YTneM+sBdqb6PemM= X-Google-Smtp-Source: ABdhPJw3HHMFLh4xhfQ7ZMs2l1XV85zKNqiYIvzLJbgCoC6GuQcgmwO8eVf9crBewi+yUUIbhGNMpw== X-Received: by 2002:a17:906:4d42:: with SMTP id b2mr26928156ejv.34.1592255187982; Mon, 15 Jun 2020 14:06:27 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:27 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 06/12] PCI: qcom: Use bulk clk api and assert on error Date: Mon, 15 Jun 2020 23:06:02 +0200 Message-Id: <20200615210608.21469-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++---------------- 1 file changed, 46 insertions(+), 85 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4dab5ef630cc..f2ea1ab6f584 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -84,12 +84,9 @@ #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; - struct clk *aux_clk; - struct clk *ref_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; @@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (ret) return ret; - res->iface_clk = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface_clk)) - return PTR_ERR(res->iface_clk); - - res->core_clk = devm_clk_get(dev, "core"); - if (IS_ERR(res->core_clk)) - return PTR_ERR(res->core_clk); - - res->phy_clk = devm_clk_get(dev, "phy"); - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "core"; + res->clks[2].id = "phy"; + res->clks[3].id = "aux"; + res->clks[4].id = "ref"; - res->aux_clk = devm_clk_get_optional(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + /* iface, core, phy are required */ + ret = devm_clk_bulk_get(dev, 3, res->clks); + if (ret < 0) + return ret; - res->ref_clk = devm_clk_get_optional(dev, "ref"); - if (IS_ERR(res->ref_clk)) - return PTR_ERR(res->ref_clk); + /* aux, ref are optional */ + ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3); + if (ret < 0) + return ret; res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) @@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - clk_disable_unprepare(res->phy_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); reset_control_assert(res->pci_reset); reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->iface_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; - } - - ret = clk_prepare_enable(res->core_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_core; - } - - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; - } - - ret = clk_prepare_enable(res->ref_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ref clock\n"); - goto err_clk_ref; - } - ret = reset_control_deassert(res->ahb_reset); if (ret) { dev_err(dev, "cannot deassert ahb reset\n"); @@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) ret = reset_control_deassert(res->ext_reset); if (ret) { dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ahb; + goto err_deassert_ext; } - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - - /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - ret = reset_control_deassert(res->phy_reset); if (ret) { dev_err(dev, "cannot deassert phy reset\n"); - return ret; + goto err_deassert_phy; } ret = reset_control_deassert(res->pci_reset); if (ret) { dev_err(dev, "cannot deassert pci reset\n"); - return ret; + goto err_deassert_pci; } ret = reset_control_deassert(res->por_reset); if (ret) { dev_err(dev, "cannot deassert por reset\n"); - return ret; + goto err_deassert_por; } ret = reset_control_deassert(res->axi_reset); if (ret) { dev_err(dev, "cannot deassert axi reset\n"); - return ret; + goto err_deassert_axi; } - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_deassert_ahb; - } + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; + + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + + /* enable external reference clock */ + val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val |= BIT(16); + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ usleep_range(1000, 1500); @@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return 0; +err_clks: + reset_control_assert(res->axi_reset); +err_deassert_axi: + reset_control_assert(res->por_reset); +err_deassert_por: + reset_control_assert(res->pci_reset); +err_deassert_pci: + reset_control_assert(res->phy_reset); +err_deassert_phy: + reset_control_assert(res->ext_reset); +err_deassert_ext: + reset_control_assert(res->ahb_reset); err_deassert_ahb: - clk_disable_unprepare(res->ref_clk); -err_clk_ref: - clk_disable_unprepare(res->aux_clk); -err_clk_aux: - clk_disable_unprepare(res->core_clk); -err_clk_core: - clk_disable_unprepare(res->iface_clk); -err_assert_ahb: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret; From patchwork Mon Jun 15 21:06:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605841 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 328B160D for ; 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[95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:29 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , stable@vger.kernel.org, Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 07/12] PCI: qcom: Define some PARF params needed for ipq8064 SoC Date: Mon, 15 Jun 2020 23:06:03 +0200 Message-Id: <20200615210608.21469-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f2ea1ab6f584..85313493d51b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -77,6 +77,18 @@ #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 +/* PARF registers */ +#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +#define PCIE20_PARF_PCS_SWING 0x38 +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PHY_RX0_EQ(x) ((x) << 24) #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 @@ -293,6 +305,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + struct device_node *node = dev->of_node; u32 val; int ret; @@ -347,6 +360,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), + pcie->parf + PCIE20_PARF_PCS_DEEMPH); + writel(PCS_SWING_TX_SWING_FULL(120) | + PCS_SWING_TX_SWING_LOW(120), + pcie->parf + PCIE20_PARF_PCS_SWING); + writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); val |= BIT(16); From patchwork Mon Jun 15 21:06:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605837 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 058AF618 for ; Mon, 15 Jun 2020 21:07:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E1604207D3 for ; Mon, 15 Jun 2020 21:07:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Hh7ygWMI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731635AbgFOVGg (ORCPT ); Mon, 15 Jun 2020 17:06:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730995AbgFOVGe (ORCPT ); Mon, 15 Jun 2020 17:06:34 -0400 Received: from mail-ej1-x644.google.com (mail-ej1-x644.google.com [IPv6:2a00:1450:4864:20::644]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B676C08C5C2; Mon, 15 Jun 2020 14:06:34 -0700 (PDT) Received: by mail-ej1-x644.google.com with SMTP id l12so18936334ejn.10; Mon, 15 Jun 2020 14:06:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XXtSQJBIW6XHl2mmAvdBVlZsx0pGkGe1gW4agfhCEW4=; b=Hh7ygWMI54L92HxNwNvnIIekrr9bNGN4aOX4EvV/CRXkpF3cAAHXTCW7/C28HIL9TN 2NixDLCUilIJAE8JO4S/ymAgVgzmccHOxHi+05kzq0uSqOSSj9OJy60M0i/Q9Tvckn66 YfxGNZmq2CdKSLItbQnKB0z/dsyCXTcdxaFYVCPkHS6snrrbxqDRZK91n1QCeRoWLMVX 8+LhsnBKFbXIPhDgU2rCh8RhQPNFr0gHyl8bHTS786ra8Ezkv0U6hDlcwRMb0jag0/A0 D47DfyA0T8xIjWTG+g6dJscZdhr6fx8sdT5BpIHqLpECFxqOEJ2Igon5cocekEe8RGv/ qowg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XXtSQJBIW6XHl2mmAvdBVlZsx0pGkGe1gW4agfhCEW4=; b=UdZ5UxrGmkyCETif1BXAnRtIR3cePk33sPRXRLKauwjaHKNLLoFuycW57QQB+/1u0F 2jrLvWGkOQ5V+XlzzRyAVIOeNAn07eVHaGc3+f2SNQ8oINWWwud5Jtko6wHNc+cSvlDO pEgKLz05kCykoj5yDG5wmRtcziC850JBUfJr1/U5IiFJu2/O4G5+ouLkroxrvcdDPqBn bZjLDo55hIxdjBVxPp5DF5vxMNAIEAQXOLli3YHQgnTsJ3XgCvEVq57E+ZdvnJOsO+wZ FtxyYfN+mWA/pzPxzcfNPhs68r6fp6Ymc14H1UVZqlU+/7I+odR9hN5p/pn7M7MagQQp qS0g== X-Gm-Message-State: AOAM532ZxVrL4EWmbPGivvsk8hI1thhfIT228MYoDC7oyAMXfRd63ky9 65wzWjroA8bfKBiq2p/3tcA= X-Google-Smtp-Source: ABdhPJySz+Kup6XcqBB5A5BBhr4P7TC2i+Q/m8tdRaHGIqWCNS4e+uCUvk0CGqtGxKqb3EL9CIE+QA== X-Received: by 2002:a17:906:470b:: with SMTP id y11mr28271687ejq.182.1592255192688; Mon, 15 Jun 2020 14:06:32 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:32 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Sham Muthayyan , stable@vger.kernel.org, Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 08/12] PCI: qcom: Add support for tx term offset for rev 2.1.0 Date: Mon, 15 Jun 2020 23:06:04 +0200 Message-Id: <20200615210608.21469-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 needs tx term offset set to 7. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Cc: stable@vger.kernel.org # v4.5+ --- drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 85313493d51b..2cd6d1456210 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,7 +45,13 @@ #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 #define PCIE20_PARF_PHY_CTRL 0x40 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) + #define PCIE20_PARF_PHY_REFCLK 0x4C +#define PHY_REFCLK_SSP_EN BIT(16) +#define PHY_REFCLK_USE_PAD BIT(12) + #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 @@ -371,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); } + if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + /* set TX termination offset */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; + val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + } + /* enable external reference clock */ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); - val |= BIT(16); + val &= ~PHY_REFCLK_USE_PAD; + val |= PHY_REFCLK_SSP_EN; writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); /* wait for clock acquisition */ From patchwork Mon Jun 15 21:06:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605835 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 165B8618 for ; Mon, 15 Jun 2020 21:07:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F1C0A207D3 for ; Mon, 15 Jun 2020 21:07:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qcDOZ3hg" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731661AbgFOVHC (ORCPT ); Mon, 15 Jun 2020 17:07:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731154AbgFOVGi (ORCPT ); Mon, 15 Jun 2020 17:06:38 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A813FC061A0E; Mon, 15 Jun 2020 14:06:36 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id e12so12578360eds.2; Mon, 15 Jun 2020 14:06:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CF5K9ujAQuucHml86IAG1dkKBBk45BbB1oezTy06myY=; b=qcDOZ3hgr1ADhgAZm2QtCmAX4qKpx6GAkHuhohZHSLphx2nrfVaQQgths0J4JahMr8 cC/03iW0ZUh4S7M7etRijN8maAclSzhRXRfPHhTIu5wZB3Hw0zEC2oWS39CJIq6h2PM+ takVWPXZAMfTojJgngfKSZVtS2B+H0Cot7w3eiQDb+Dvqfk0fHijdWs9p+2KpqbzJdM4 Otv5fyNmiSZBO3alybYR2OjeeUu2SENeqOcPs06cbU/QPzCQ2LPdRdFoiNH6iquTdYeN EHWhxSGP9Z7yDQYsfYMgNLTTfkYah9c7QZAWHCfFULRh5FESkXFZB80yy2obOqRaYSdG ljLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CF5K9ujAQuucHml86IAG1dkKBBk45BbB1oezTy06myY=; b=pTM0WJ7b+aihBvX+D7UrJtiuugooX3RpMFi49mzBTf02xcbBzGP/GJxludgUtoYVNr OvaOlgWXP/A4NDemwMnDjr7fZrmdVlwQNuw5QWg4X1CPImgjDcbsDKP5H8MiN5lPtqnL y9dx/Kexy3iZiDSAusXTFAPE5+VdQJ4J2o+yolgcn8mTztEjVEzYozzXkF2ev/QdlMCk cJ52L0AEkWqfIehKowmT6jUHxAtXCxmgfpD6QQTjhjg6m7QIHqrEuY7URbWrwnG7rkW6 8hC4x9f+V7tOe4flzmqu/FHhMLvya7Io5u/ea7Gzi2QLuI9sRP0cwMUfjz1DsWQiRCSV OZEA== X-Gm-Message-State: AOAM533qRrVd5nqNHBhuACrlUXcmYLtfXGT3TDi3D3Yu4212Yz890dxu eUYfELnX1H7yj0Idk2SFLbo= X-Google-Smtp-Source: ABdhPJwxom631KPO65yeC0E53jnW34L2PrhaWBP5j08rh3VRYuvgUuKzW3MonC3t1bKFQHLZCenhGQ== X-Received: by 2002:a50:cd56:: with SMTP id d22mr24844238edj.374.1592255195340; Mon, 15 Jun 2020 14:06:35 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:34 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 09/12] PCI: qcom: Add ipq8064 rev2 variant Date: Mon, 15 Jun 2020 23:06:05 +0200 Message-Id: <20200615210608.21469-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2cd6d1456210..259b627bf890 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -366,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) val &= ~BIT(0); writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); - if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { + if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || + of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), @@ -1464,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, From patchwork Mon Jun 15 21:06:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605815 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3BCF313B1 for ; Mon, 15 Jun 2020 21:06:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 240FD208C3 for ; Mon, 15 Jun 2020 21:06:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FNs0CRYt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731648AbgFOVGl (ORCPT ); Mon, 15 Jun 2020 17:06:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731436AbgFOVGj (ORCPT ); Mon, 15 Jun 2020 17:06:39 -0400 Received: from mail-ed1-x543.google.com (mail-ed1-x543.google.com [IPv6:2a00:1450:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09859C08C5C2; Mon, 15 Jun 2020 14:06:39 -0700 (PDT) Received: by mail-ed1-x543.google.com with SMTP id x93so12565686ede.9; Mon, 15 Jun 2020 14:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Bh2m7yBBFpphGSLnQ2t1Jsojy/ZnrrVmbVXPSEiIJns=; b=FNs0CRYtsNATVl4vdOR9CODEwIZN1Vx9CWZ5LlImi+2sYEsQTsqPd9RFmHQfhC+UCE qtR3JUHFUUaod2cYXXZfgCHzrpX8YekVGwIkJo+fWwKPJUUyrqZdgePpz0nqz9vLr/Ln 3SKXSFAzF2yXbzld3jvYv2qELiOeE3CFEqHbfq2GQXxg+woR0qSD4id0CcnbtAkEP1iP g2LjPdgK9m/OMHDIM14qa12aBsAd+ar8rFJ8Vb1A1FPU5hrMFaLltDfT9YUfTpb/FdjT AcvZZVBXteHIr8xK8+NaKbsxAMVB5s7z3b5B9mB67RNx1lPhKcDAf/ooKS4B0Ik6eXa6 LPyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bh2m7yBBFpphGSLnQ2t1Jsojy/ZnrrVmbVXPSEiIJns=; b=DvPWZLo683JJ9GArA9J7iRpw2DT7g5KlHMUNzRtR8t9QMhqhNZo5Q/LNd+k9b+wt6I MZooq9D66XIPOivZ0uRJZsqFeG/KN12IlVrURTN7bCusH3JuFi4X/qqBhJJ6sxaO+n5L zCKPHVxA2uChmSW+8aLb73QfhNbZiM0woghwltWRnl+bQDgsyuGfjE52W1ugZd5juDvW SfjFbB65FVgg7DMU2VFf1eoDLcXTYztBVPYEGOkszwmKeByd5cyb3GpZ4RQgRtbUgDAH 2JjxnnDS34K55szldhf/3ZgxK80gJgNrBt1/3p4xDU+/WMFSBNatzzQtcyC8z86DduyX cFfg== X-Gm-Message-State: AOAM533eoCJMlN+8xZsQlyqIwL1OTX9K6GgHmTvBQtmUD+YHNUeefwPU 1LilJnvAV4KzPsGOyWL9luk= X-Google-Smtp-Source: ABdhPJxnkeg+c6UmESzTHYxMxZgx+zykL2kfHKyWujkTe2BOlg5tGkinMQAAdEEVKgCMK2Gc5eoCBA== X-Received: by 2002:aa7:db51:: with SMTP id n17mr24696770edt.241.1592255197657; Mon, 15 Jun 2020 14:06:37 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:37 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 10/12] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant Date: Mon, 15 Jun 2020 23:06:06 +0200 Message-Id: <20200615210608.21469-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset. In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0 by default. Signed-off-by: Ansuel Smith Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 6efcef040741..02bc81bb8b2d 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -5,6 +5,7 @@ Value type: Definition: Value should contain - "qcom,pcie-ipq8064" for ipq8064 + - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - "qcom,pcie-apq8064" for apq8064 - "qcom,pcie-apq8084" for apq8084 - "qcom,pcie-msm8996" for msm8996 or apq8096 From patchwork Mon Jun 15 21:06:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605829 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44578618 for ; Mon, 15 Jun 2020 21:07:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2CBDB20DD4 for ; Mon, 15 Jun 2020 21:07:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dkzP8Jq0" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731779AbgFOVG4 (ORCPT ); Mon, 15 Jun 2020 17:06:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731661AbgFOVGl (ORCPT ); Mon, 15 Jun 2020 17:06:41 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B885C061A0E; Mon, 15 Jun 2020 14:06:41 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id o15so18949132ejm.12; Mon, 15 Jun 2020 14:06:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qk9kJyl6xBs7NFHSty0oErpx4zGo0ReUFZlbaqRNYPs=; b=dkzP8Jq0x2fUTU2b/tFozk9+Wun/+haYoHAexmI0WJHmv809aW5/yvxZ1GypsufitD 3NlVoyV5/l61fORMPFRcytjQykeS5IAHtjgHdqgb8DNVhwiKGUWcsHOzex5bKPrELkmj lD1AzH70nmiAYLOF+Kmn6mL2NOXaIWX8xc5YCYpWUhFStBfMO96BovNv2rwBRjTSGo6r HnaxRnnkD/JyGYvYT15MQN8UNI8uL/9npOHFQH/NH0Uh9mteI+ayy+JT3gAQP7+TscCK HoSA6Lfu2WlKWkIsPhNwxULBoJH7Ixf4fVEwQVnkaKM6qpBWfsLbkw+lB1NTPrZdFrQF BOLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qk9kJyl6xBs7NFHSty0oErpx4zGo0ReUFZlbaqRNYPs=; b=t3PcV21CO6atk3WmJMEfPEl86rexizePn06bPnKPLEU/Vr6nRqk+fcBCTx1dPxHFcu nasgEPtLOoqSQbagE5cQy1EyWuFSAa7BU66A+rTvi8xdiO7vEXGu/4MawvI4+3+yDdMc VeMqvJrCbHAAKcsT/axGSr3rftxFeud6aFDActaFM5HJTb+wMuvIgyGms0cwyN+kV1Wm sninM8CNqCArn3VshSHxjg8oTdlthuFWX3Qv2i0uZrxiwUPUqrDYP5RRZfnWOhxOjswG DCHcVyWKwGysJgvPNYgZM/p3xIk1QSGW8z0X18H9u5KgA1hsPXXjgu0W7Jdg7kQFj4ad C7AA== X-Gm-Message-State: AOAM533t78lwLak31uj+EOLWNzFHrsF6yXWrPTJlfKzTWVUcgqZrg2pW HlXMWDjQbRIiqcFr7vWDdgw= X-Google-Smtp-Source: ABdhPJyc4yxO4q5FGFJ0IFqE2jFCbHKF/8kBv0fGSC41jRkaEwAla+s9I7WWysulTAldPZOp6frCsA== X-Received: by 2002:a17:906:2581:: with SMTP id m1mr8061904ejb.89.1592255199974; Mon, 15 Jun 2020 14:06:39 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:39 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Sham Muthayyan , Ansuel Smith , Rob Herring , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 11/12] PCI: qcom: Support pci speed set for ipq806x Date: Mon, 15 Jun 2020 23:06:07 +0200 Message-Id: <20200615210608.21469-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sham Muthayyan Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to some hardware limitations. Add support for speed setting defined by the max-link-speed binding. If not defined the max speed is set to GEN2 by default. Signed-off-by: Sham Muthayyan Signed-off-by: Ansuel Smith Reviewed-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 259b627bf890..c40921589122 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -27,6 +27,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE20_PARF_SYS_CTRL 0x00 @@ -99,6 +100,8 @@ #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 +#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 + #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -195,6 +198,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; const struct qcom_pcie_ops *ops; + int gen; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) /* wait for clock acquisition */ usleep_range(1000, 1500); + if (pcie->gen == 1) { + val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + val |= PCI_EXP_LNKSTA_CLS_2_5GB; + writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); + } /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, @@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); + if (pcie->gen < 0) + pcie->gen = 2; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); pcie->parf = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->parf)) { From patchwork Mon Jun 15 21:06:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11605817 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F25B360D for ; Mon, 15 Jun 2020 21:06:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D78E5208C7 for ; Mon, 15 Jun 2020 21:06:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Z4pY9opf" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731668AbgFOVGs (ORCPT ); Mon, 15 Jun 2020 17:06:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731436AbgFOVGp (ORCPT ); Mon, 15 Jun 2020 17:06:45 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81864C08C5C5; Mon, 15 Jun 2020 14:06:43 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id q19so18972308eja.7; Mon, 15 Jun 2020 14:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q1JV3CXtWnCDf52pi6FDmUEpTUr0tLhuu541saxjHEI=; b=Z4pY9opfhhvGea/MOsllxIaNmvyJGxZq48BRu+78lWmOHGt/CRLVSdJBc5pNAjpXHX MTK1X+UC3oq+jADFPxMw3RFixQoVxqGxyEV2myuabTpGQusza9gKTzLR8GaYxtqpobJ/ N/Xn/fYAiIP3dh8FrcXpTxpkIYQ3apCrpRjDrpXdCMOjbj5fi5jzIhU7pLr+X2Au9JIX w33lHhOY0nztFZ7cOZvH8xmY8SAvDWz+4j67n4D7xfRoY93MdZd1flfl0X+nCHtM4Hsi 0VELaneQkb88GPsN5ruEpfY1Q/3gBdsK4HG5HGXpsw2rf56C8rupaCLjvZMPyFQzVpeo GyUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q1JV3CXtWnCDf52pi6FDmUEpTUr0tLhuu541saxjHEI=; b=ucNswi4DtA+0UrdGlBckvTGLZoXptfumHeCCs2lXQZhFO22KmFhJR3IBv/425G9tjO 0xDhq2Wmzno19TLvoM+2YbZdkXfatoYKAnEFnHR7a0uVzW+5IlGRHqBTj1VjmssOpQUm JePHlfqBZtBSbh8WXH28BPuGxXTNq9dU6abfFoWD+3EWM0xXXHk+PmUNuO8qsSBk5zXA aft++8/DcyU45IXAsec9drTCmxOR8s5P6rU67raZFzeHT3PyVyIwJA3fBliOa+C9/tIs hKe3YNN8oDBHG4EqcCZvToVF+EzffQlYuoNEGVTJhD22QmmU5Ly7jSmDXy9cmrcRvzHc CuEQ== X-Gm-Message-State: AOAM530TUrHR9DwMIx3lED/lAmc8YVrfMuAayLYQHbz0qFAUBACMOJ+P J0/SKYelXq0QjjcnOskHSWE= X-Google-Smtp-Source: ABdhPJxlXYUjd15RFk8CBG6UIc9d/yo7kuVUtZIdTWjh+B9ECG73/qaJPjEYy/EXD89DLyDCtK6blQ== X-Received: by 2002:a17:906:1184:: with SMTP id n4mr5224874eja.115.1592255202187; Mon, 15 Jun 2020 14:06:42 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-95-238-254-39.retail.telecomitalia.it. [95.238.254.39]) by smtp.googlemail.com with ESMTPSA id d5sm9662226ejr.78.2020.06.15.14.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2020 14:06:41 -0700 (PDT) From: Ansuel Smith To: Rob Herring Cc: Vinod Koul , Ansuel Smith , Andy Gross , Bjorn Andersson , Bjorn Helgaas , Mark Rutland , Stanimir Varbanov , Lorenzo Pieralisi , Andrew Murray , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 12/12] PCI: qcom: Replace define with standard value Date: Mon, 15 Jun 2020 23:06:08 +0200 Message-Id: <20200615210608.21469-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0.rc0 In-Reply-To: <20200615210608.21469-1-ansuelsmth@gmail.com> References: <20200615210608.21469-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Signed-off-by: Ansuel Smith --- drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index c40921589122..a23d3d886479 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -40,11 +40,6 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_COMMAND_STATUS 0x04 -#define CMD_BME_VAL 0x4 -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - #define PCIE20_PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) @@ -73,8 +68,8 @@ #define CFG_BRIDGE_SB_INIT BIT(0) #define PCIE20_CAP 0x70 -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) +#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2) +#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP) #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F @@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PCIE20_PARF_SYS_CTRL); writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; + val &= ~PCI_EXP_LNKCAP_ASPMS; writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + PCIE20_DEVICE_CONTROL2_STATUS2); return 0;