From patchwork Wed Jun 17 07:05:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 741F9138C for ; Wed, 17 Jun 2020 07:15:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D9B8206F1 for ; Wed, 17 Jun 2020 07:15:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AvSDUFIT"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MET7TKhf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D9B8206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RRC5AM7mW6mzE90yA1IqUbGE+UMZAxqHFEMaywDBBJU=; b=AvSDUFITUBBfcy o2MbZsaYI2boOBs0py6hYLkT9mIiZa/2osoVLKpSTBhMQaWs6MPUxmCwSbQ34mbBmUPsXlT8Z9gGq d1meSgpa8ZcNbscl5ui9K596fUiCZjZZSY+FZNIY8BPX5fT3mMdIc6/adlOL8hN1i7Sqsn5GdDP9W yM2tgfUAbclC98VDyVrA6baZ4AWo/hdnsh+aqutcE2KY1ZeIh64lYdgkcxbEs3ikjO91x6iPUlRIM 9v+JJmJ4VGbtiz6TRQI5a2SC30x1BS7UiHR2blPtJ9yQhaaVFIq3D2P3CaydvZj0wjhzYttJHQ+2j Kdik6F3KeLmw78zFl8aA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIF-0002Lm-L6; Wed, 17 Jun 2020 07:15:31 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSID-0002Jo-6V; Wed, 17 Jun 2020 07:15:30 +0000 X-UUID: 76dc28f19efe437891a5be126773aaea-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dGXGiunHjZndJ6cHTy/bVaVcZvEJmUdgQt8u80wNGMc=; b=MET7TKhfpBhF5XHsrDOXFi56IE4aN8q4SZyjYvKxBJ4d4020JxdSogDIFN0m+c5Ea5EnFHjWf7NN5+r4z7oGqH/oHYjrVL6WLRegA5dGrH4pKpvHLL+hrQeGPJ89ZNdX2fTDX27jdH/w5lDARluzL6W6xXXVHwrA3zo7px6SBgs=; X-UUID: 76dc28f19efe437891a5be126773aaea-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 472515419; Tue, 16 Jun 2020 23:15:14 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:23 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:21 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:22 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 01/11] dt-bindings: mediatek: Add property to mt8183 smi-common Date: Wed, 17 Jun 2020 15:05:07 +0800 Message-ID: <1592377517-14817-2-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001529_250649_89EEA63C X-CRM114-Status: UNSURE ( 9.71 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org For scpsys driver using regmap based syscon driver API. Signed-off-by: Weiyi Lu Acked-by: Rob Herring --- .../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt index b478ade..01744ec 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt @@ -20,7 +20,7 @@ Required properties: "mediatek,mt2712-smi-common" "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" "mediatek,mt8173-smi-common" - "mediatek,mt8183-smi-common" + "mediatek,mt8183-smi-common", "syscon" - reg : the register and size of the SMI block. - power-domains : a phandle to the power domain of this local arbiter. - clocks : Must contain an entry for each entry in clock-names. From patchwork Wed Jun 17 07:05:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B0715138C for ; Wed, 17 Jun 2020 07:18:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8E88F206F1 for ; Wed, 17 Jun 2020 07:18:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cTnQhUnB"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XtjICMZj" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8E88F206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v03oC5e8HmXrXS8Go1v2LI/Cu8GI9CdIX6y0X/M6eOo=; b=cTnQhUnBDdIh5P UGgeScnRwoWFv4Z7aYMs990rqYxTb7LuIqJm/KdMxdEtl4ecx7t2UcHDZIcNVNDJkl6EjZ9a44LZc Mzl4B1kkbmnLR6soeO/J712BRfGHBkfpX2wNopWuQ/Wc8qEKvO6H8B/02poFC/EcGEofAw/XX85fE OfRqUDhPKU7RiIhwqdNuIBUQOzu/GVZtz8OJx+3I9eB1TW55a7f1/A74hQa7ZYaYpe2tveG9IOP43 bOL+hTQ+pbNulx/0Dicw+WSKifg2HF5ec7PjBpY13Q51JfJhp+ECuiaBL1PqEyBMKGR1rLpl7lgb6 oMxxCpkYn+zO2AfhfF0Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSKb-0004bA-Rx; Wed, 17 Jun 2020 07:17:57 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIP-0002T1-Ia; Wed, 17 Jun 2020 07:15:45 +0000 X-UUID: 0d11a758e28f488c8aac759045a1c607-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=sFJmN4Wh3vZM8/oU/VtnNpfoEznKzEY3P9YuUgNgScc=; b=XtjICMZjnbkm9fYuyaZvuCRE8CsRh7bSIqqgkXWfsHPj3u39UUDERrVWrGR3ZC7ut62DQLU7eBQjFiR0SYW9SldEfOssOQ8a5o31nAa4+LWa3bHsbyly9/DKZXwpNJeHLD2UC9eic+Eo4iQOczoUUQmBiumrJgPCyM/MHVw5Iv8=; X-UUID: 0d11a758e28f488c8aac759045a1c607-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1928822789; Tue, 16 Jun 2020 23:15:21 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:31 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:22 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 02/11] dt-bindings: soc: Add MT8183 power dt-bindings Date: Wed, 17 Jun 2020 15:05:08 +0800 Message-ID: <1592377517-14817-3-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0AF6C61D160782B90D753CEF63B0F93B7E3504FF64E2CD5137561A2921C7035B2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001541_755931_7FF7992B X-CRM114-Status: GOOD ( 12.51 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add power dt-bindings of MT8183 and introduces "BASIC" and "SUBSYS" clock types in binding document. The "BASIC" type is compatible to the original power control with clock name [a-z]+[0-9]*, e.g. mm, vpu1. The "SUBSYS" type is used for bus protection control with clock name [a-z]+-[0-9]+, e.g. isp-0, cam-1. And add an optional "mediatek,smi" property for phandle to smi-common node. Signed-off-by: Weiyi Lu Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 21 ++++++++++++++--- include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++ 2 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 include/dt-bindings/power/mt8183-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 2bc3677..8e0b9f2 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -15,6 +15,7 @@ power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt2701-power.h - include/dt-bindings/power/mt2712-power.h - include/dt-bindings/power/mt7622-power.h +- include/dt-bindings/power/mt8183-power.h Required properties: - compatible: Should be one of: @@ -27,12 +28,16 @@ Required properties: - "mediatek,mt7623a-scpsys": For MT7623A SoC - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC - "mediatek,mt8173-scpsys" + - "mediatek,mt8183-scpsys" - #power-domain-cells: Must be 1 - reg: Address range of the SCPSYS unit - infracfg: must contain a phandle to the infracfg controller -- clock, clock-names: clocks according to the common clock binding. - These are clocks which hardware needs to be - enabled before enabling certain power domains. +- clock, clock-names: Clocks according to the common clock binding. + Some SoCs have to groups of clocks. + BASIC clocks need to be enabled before enabling the + corresponding power domain. + SUBSYS clocks need to be enabled before releasing the + bus protection. Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif" Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec" Required clocks for MT6765: MUX: "mm", "mfg" @@ -43,6 +48,15 @@ Required properties: Required clocks for MT7622 or MT7629: "hif_sel" Required clocks for MT7623A: "ethif" Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt" + Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp", + "vpu", "vpu1", "vpu2", "vpu3" + SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3", + "mm-4", "mm-5", "mm-6", "mm-7", + "mm-8", "mm-9", "isp-0", "isp-1", + "cam-0", "cam-1", "cam-2", "cam-3", + "cam-4", "cam-5", "cam-6", "vpu-0", + "vpu-1", "vpu-2", "vpu-3", "vpu-4", + "vpu-5" Optional properties: - vdec-supply: Power supply for the vdec power domain @@ -55,6 +69,7 @@ Optional properties: - mfg_async-supply: Power supply for the mfg_async power domain - mfg_2d-supply: Power supply for the mfg_2d power domain - mfg-supply: Power supply for the mfg power domain +- mediatek,smi : A phandle to the smi_common node Example: diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h new file mode 100644 index 0000000..d1ab387 --- /dev/null +++ b/include/dt-bindings/power/mt8183-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu + */ + +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H +#define _DT_BINDINGS_POWER_MT8183_POWER_H + +#define MT8183_POWER_DOMAIN_AUDIO 0 +#define MT8183_POWER_DOMAIN_CONN 1 +#define MT8183_POWER_DOMAIN_MFG_ASYNC 2 +#define MT8183_POWER_DOMAIN_MFG 3 +#define MT8183_POWER_DOMAIN_MFG_CORE0 4 +#define MT8183_POWER_DOMAIN_MFG_CORE1 5 +#define MT8183_POWER_DOMAIN_MFG_2D 6 +#define MT8183_POWER_DOMAIN_DISP 7 +#define MT8183_POWER_DOMAIN_CAM 8 +#define MT8183_POWER_DOMAIN_ISP 9 +#define MT8183_POWER_DOMAIN_VDEC 10 +#define MT8183_POWER_DOMAIN_VENC 11 +#define MT8183_POWER_DOMAIN_VPU_TOP 12 +#define MT8183_POWER_DOMAIN_VPU_CORE0 13 +#define MT8183_POWER_DOMAIN_VPU_CORE1 14 + +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ From patchwork Wed Jun 17 07:05:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609189 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C40E912 for ; Wed, 17 Jun 2020 07:17:44 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26C7A206F1 for ; Wed, 17 Jun 2020 07:17:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lNmFAN4S"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Z6wa0iW+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 26C7A206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7I/0pAFva9jz6ZGFuBGIA6wG/i8mHr7Q5afSWC19gyg=; b=lNmFAN4SgQaUdP HT+6lcOziZdTpu2SdmIOrfUspm/21f6byhINFlDO3NrNOyiltHlwP/Q4y07eMwLl74xvHAOhRFxWt BZTz+ZkZYiqdVyvJvGSjhrz0jBPTcH/g8EM8Yv6E76CwheZnKam/FtYsyA6ExgZga88HnzjhGVMl7 2kMaT5fKHgdO6C4CypbX+ENOMKXtdnxPFWKTcLQn/wOLSTyBw6401UaFvh/qYR0yXRrDGf/+Cm1Sf djniGGsTp+YCZeKJn0pVtc3AXiOByi0S5DQn/gi+Ux13tg20TfJXtXUqeXKamxNx6jBwQk8+Vz8tM ZtkeCzCuxtMGlevrN3Bw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSKL-0004Io-UE; Wed, 17 Jun 2020 07:17:41 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIG-0002JY-DV; Wed, 17 Jun 2020 07:15:35 +0000 X-UUID: 263780a574a341aca93afa0dd34dc600-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=X1NDBhTPonNFCyfn+Vu9nt4rKMEPznMllsnD3UGUKPo=; b=Z6wa0iW+F1Oypw71Ga/NKcdF0FIVhPCFeRR6tySFc2JnGCsKawGYNbN9EwqoHwR9lw0pQOsPWzF1P2mSzBA2GJsH3izMJYbUC0OXldj0xK/V1e6kiirGgq6Rn7sAeJ64bz3jMS9W2XZ0F9uJMJOGbyEJ1M5aKT9n+/eCFxb4oVY=; X-UUID: 263780a574a341aca93afa0dd34dc600-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1639753361; Tue, 16 Jun 2020 23:15:14 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:23 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:22 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 03/11] soc: mediatek: Add basic_clk_name to scp_power_data Date: Wed, 17 Jun 2020 15:05:09 +0800 Message-ID: <1592377517-14817-4-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001532_541646_2A799385 X-CRM114-Status: GOOD ( 12.45 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Try to stop extending the clk_id or clk_names if there are more and more new BASIC clocks. To get its own clocks by the basic_clk_name of each power domain. And then use basic_clk_name strings for all compatibles, instead of mixing clk_id and clk_name. Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 134 ++++++++++++-------------------------- 1 file changed, 41 insertions(+), 93 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f669d37..c9c3cf7 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -78,34 +78,6 @@ #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ #define PWR_STATUS_WB BIT(27) /* MT7622 */ -enum clk_id { - CLK_NONE, - CLK_MM, - CLK_MFG, - CLK_VENC, - CLK_VENC_LT, - CLK_ETHIF, - CLK_VDEC, - CLK_HIFSEL, - CLK_JPGDEC, - CLK_AUDIO, - CLK_MAX, -}; - -static const char * const clk_names[] = { - NULL, - "mm", - "mfg", - "venc", - "venc_lt", - "ethif", - "vdec", - "hif_sel", - "jpgdec", - "audio", - NULL, -}; - #define MAX_CLKS 3 /** @@ -116,7 +88,7 @@ enum clk_id { * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @bus_prot_mask: The mask for single step bus protection. - * @clk_id: The basic clocks required by this power domain. + * @basic_clk_name: The basic clocks required by this power domain. * @caps: The flag for active wake-up action. */ struct scp_domain_data { @@ -126,7 +98,7 @@ struct scp_domain_data { u32 sram_pdn_bits; u32 sram_pdn_ack_bits; u32 bus_prot_mask; - enum clk_id clk_id[MAX_CLKS]; + const char *basic_clk_name[MAX_CLKS]; u8 caps; }; @@ -411,12 +383,19 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) return ret; } -static void init_clks(struct platform_device *pdev, struct clk **clk) +static int init_basic_clks(struct platform_device *pdev, struct clk **clk, + const char * const *name) { int i; - for (i = CLK_NONE + 1; i < CLK_MAX; i++) - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]); + for (i = 0; i < MAX_CLKS && name[i]; i++) { + clk[i] = devm_clk_get(&pdev->dev, name[i]); + + if (IS_ERR(clk[i])) + return PTR_ERR(clk[i]); + } + + return 0; } static struct scp *init_scp(struct platform_device *pdev, @@ -426,9 +405,8 @@ static struct scp *init_scp(struct platform_device *pdev, { struct genpd_onecell_data *pd_data; struct resource *res; - int i, j; + int i, ret; struct scp *scp; - struct clk *clk[CLK_MAX]; scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); if (!scp) @@ -481,8 +459,6 @@ static struct scp *init_scp(struct platform_device *pdev, pd_data->num_domains = num; - init_clks(pdev, clk); - for (i = 0; i < num; i++) { struct scp_domain *scpd = &scp->domains[i]; struct generic_pm_domain *genpd = &scpd->genpd; @@ -493,17 +469,9 @@ static struct scp *init_scp(struct platform_device *pdev, scpd->data = data; - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) { - struct clk *c = clk[data->clk_id[j]]; - - if (IS_ERR(c)) { - dev_err(&pdev->dev, "%s: clk unavailable\n", - data->name); - return ERR_CAST(c); - } - - scpd->clk[j] = c; - } + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name); + if (ret) + return ERR_PTR(ret); genpd->name = data->name; genpd->power_off = scpsys_power_off; @@ -560,7 +528,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_CONN_PWR_CON, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | MT2701_TOP_AXI_PROT_EN_CONN_S, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_DISP] = { @@ -568,7 +535,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -578,7 +545,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_VDEC] = { @@ -587,7 +554,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_ISP] = { @@ -596,7 +563,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_BDP] = { @@ -604,7 +571,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sta_mask = PWR_STATUS_BDP, .ctl_offs = SPM_BDP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_ETH] = { @@ -613,7 +579,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETH_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_HIF] = { @@ -622,14 +588,13 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_IFR_MSC] = { .name = "ifr_msc", .sta_mask = PWR_STATUS_IFR_MSC, .ctl_offs = SPM_IFR_MSC_PWR_CON, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -644,7 +609,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_VDEC] = { @@ -653,7 +618,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM, CLK_VDEC}, + .basic_clk_name = {"mm", "vdec"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_VENC] = { @@ -662,7 +627,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC}, + .basic_clk_name = {"mm", "venc", "jpgdec"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_ISP] = { @@ -671,7 +636,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_AUDIO] = { @@ -680,7 +645,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_AUDIO_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_AUDIO}, + .basic_clk_name = {"audio"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_USB] = { @@ -689,7 +654,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB_PWR_CON, .sram_pdn_bits = GENMASK(10, 8), .sram_pdn_ack_bits = GENMASK(14, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_USB2] = { @@ -698,7 +662,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB2_PWR_CON, .sram_pdn_bits = GENMASK(10, 8), .sram_pdn_ack_bits = GENMASK(14, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG] = { @@ -707,7 +670,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -717,7 +680,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x02c0, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG_SC2] = { @@ -726,7 +688,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x02c4, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG_SC3] = { @@ -735,7 +696,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x01f8, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -760,7 +720,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x300, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_VDEC}, + .basic_clk_name = {"vdec"}, }, [MT6797_POWER_DOMAIN_VENC] = { .name = "venc", @@ -768,7 +728,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x304, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_ISP] = { .name = "isp", @@ -776,7 +735,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x308, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_MM] = { .name = "mm", @@ -784,7 +742,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x30C, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = (BIT(1) | BIT(2)), }, [MT6797_POWER_DOMAIN_AUDIO] = { @@ -793,7 +751,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x314, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT6797_POWER_DOMAIN_MFG_ASYNC] = { .name = "mfg_async", @@ -801,7 +758,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x334, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, }, [MT6797_POWER_DOMAIN_MJC] = { .name = "mjc", @@ -809,7 +766,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = 0x310, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_NONE}, }, }; @@ -834,7 +790,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETHSYS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -844,7 +799,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF0_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_HIFSEL}, + .basic_clk_name = {"hif_sel"}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -854,7 +809,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF1_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_HIFSEL}, + .basic_clk_name = {"hif_sel"}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, @@ -864,7 +819,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_WB_PWR_CON, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .clk_id = {CLK_NONE}, .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB, .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM, }, @@ -881,7 +835,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_CONN_PWR_CON, .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | MT2701_TOP_AXI_PROT_EN_CONN_S, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_ETH] = { @@ -890,7 +843,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETH_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_HIF] = { @@ -899,14 +852,13 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_HIF_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_ETHIF}, + .basic_clk_name = {"ethif"}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_IFR_MSC] = { .name = "ifr_msc", .sta_mask = PWR_STATUS_IFR_MSC, .ctl_offs = SPM_IFR_MSC_PWR_CON, - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, }; @@ -922,7 +874,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VDE_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, }, [MT8173_POWER_DOMAIN_VENC] = { .name = "venc", @@ -930,7 +882,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC}, + .basic_clk_name = {"mm", "venc"}, }, [MT8173_POWER_DOMAIN_ISP] = { .name = "isp", @@ -938,7 +890,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ISP_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, }, [MT8173_POWER_DOMAIN_MM] = { .name = "mm", @@ -946,7 +898,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .clk_id = {CLK_MM}, + .basic_clk_name = {"mm"}, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | MT8173_TOP_AXI_PROT_EN_MM_M1, }, @@ -956,7 +908,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_VEN2_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_MM, CLK_VENC_LT}, + .basic_clk_name = {"mm", "venc_lt"}, }, [MT8173_POWER_DOMAIN_AUDIO] = { .name = "audio", @@ -964,7 +916,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_AUDIO_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, }, [MT8173_POWER_DOMAIN_USB] = { .name = "usb", @@ -972,7 +923,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_USB_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .clk_id = {CLK_NONE}, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT8173_POWER_DOMAIN_MFG_ASYNC] = { @@ -981,7 +931,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, - .clk_id = {CLK_MFG}, + .basic_clk_name = {"mfg"}, }, [MT8173_POWER_DOMAIN_MFG_2D] = { .name = "mfg_2d", @@ -989,7 +939,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_2D_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), - .clk_id = {CLK_NONE}, }, [MT8173_POWER_DOMAIN_MFG] = { .name = "mfg", @@ -997,7 +946,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .clk_id = {CLK_NONE}, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | MT8173_TOP_AXI_PROT_EN_MFG_M0 | MT8173_TOP_AXI_PROT_EN_MFG_M1 | From patchwork Wed Jun 17 07:05:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16DB2912 for ; Wed, 17 Jun 2020 07:16:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B16932073E for ; Wed, 17 Jun 2020 07:16:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="b5fJSFzb"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="TnqTZ/mn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B16932073E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=//UZ9zB3X/fS75NmCIBVJKNgC8dF0XKEE8edzBzs2RE=; b=b5fJSFzbOTuL5B koaS84yM+Oa5n8tIqcQUhzei7cyNyfHcnud+2X/yw0vI0uJtNrurjEepK00v5vEZpWCbVQKiZXZpl +a7hm84LwISdd6sLMSZZr+2VlaK1Ff6pCbqMDLnEbzMmNVUFV2cv1JrVRDqRCg/mLXvD8CmY/ykZz D1jFOE3tGWNJk6kB+HZDy0I/HwiJLbcOVAplDx8fRQ1oLhv11ffnUCpfovVvpmvYlLGfWcPUhYH6Q iGBTLCgWSRXhKz8XoZZBOtOlOHti6Fruipm0TZzfHZBcMa1lFy8v8zb6DLTOVgbuHnkhMvgHfWh1o JafvUY7+28qoRlT3iCwQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSJ3-00030U-LX; Wed, 17 Jun 2020 07:16:21 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIE-0002Jo-FO; Wed, 17 Jun 2020 07:15:32 +0000 X-UUID: 8135f109b8d24cdea7d7ebc1866ad1cf-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=N9zW6nHMcVwWczAyCUbbBCog+k835P3aP5/dg5DKEwM=; b=TnqTZ/mnLLMB+OK6kghHivqPYMbuoMlLNEDTw2AnGusl+fraL0LEuDQUEiwy07OR2RzM90Kt1I0q/Hm28vED42oRv4KTPercMQntaPsCwc1R1lnqDMmtfQLP7PWX3VqGNqzcXvapryGPokTvDCHFVkGPbSiMoD5g7KrA1rldwuo=; X-UUID: 8135f109b8d24cdea7d7ebc1866ad1cf-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 639674753; Tue, 16 Jun 2020 23:15:14 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:23 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:22 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 04/11] soc: mediatek: Remove infracfg misc driver support Date: Wed, 17 Jun 2020 15:05:10 +0800 Message-ID: <1592377517-14817-5-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001530_535202_4A2C9983 X-CRM114-Status: GOOD ( 17.82 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org The functions provided by infracfg misc driver have no other user except the scpsys driver so move those into scpsys driver directly. And then, remove infracfg misc driver which is no longer being used. BTW, in next patch, we're going to extend the bus protection functions with more customized arguments. Signed-off-by: Weiyi Lu Reviewed-by: Enric Balletbo i Serra --- drivers/soc/mediatek/Kconfig | 10 ----- drivers/soc/mediatek/Makefile | 1 - drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- drivers/soc/mediatek/mtk-scpsys.c | 66 +++++++++++++++++++++++++---- include/linux/soc/mediatek/infracfg.h | 39 ----------------- 5 files changed, 57 insertions(+), 138 deletions(-) delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c delete mode 100644 include/linux/soc/mediatek/infracfg.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 59a56cd..3f5e5cb 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -10,21 +10,12 @@ config MTK_CMDQ depends on ARCH_MEDIATEK || COMPILE_TEST select MAILBOX select MTK_CMDQ_MBOX - select MTK_INFRACFG help Say yes here to add support for the MediaTek Command Queue (CMDQ) driver. The CMDQ is used to help read/write registers with critical time limitation, such as updating display configuration during the vblank. -config MTK_INFRACFG - bool "MediaTek INFRACFG Support" - select REGMAP - help - Say yes here to add support for the MediaTek INFRACFG controller. The - INFRACFG controller contains various infrastructure registers not - directly associated to any device. - config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" depends on RESET_CONTROLLER @@ -38,7 +29,6 @@ config MTK_SCPSYS bool "MediaTek SCPSYS Support" default ARCH_MEDIATEK select REGMAP - select MTK_INFRACFG select PM_GENERIC_DOMAINS if PM help Say yes here to add support for the MediaTek SCPSYS power domain diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f87..2afa7b9 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,6 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c deleted file mode 100644 index 341c7ac..0000000 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 Pengutronix, Sascha Hauer - */ - -#include -#include -#include -#include -#include - -#define MTK_POLL_DELAY_US 10 -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) - -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - -/** - * mtk_infracfg_set_bus_protection - enable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be enabled. - * @reg_update: The boolean flag determines to set the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with set register(PROTECTEN_SET). - * - * This function enables the bus protection bits for disabled power - * domains so that the system does not hang when some unit accesses the - * bus while in power down. - */ -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - u32 val; - int ret; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, - mask); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, (val & mask) == mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} - -/** - * mtk_infracfg_clear_bus_protection - disable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be disabled. - * @reg_update: The boolean flag determines to clear the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with clear register(PROTECTEN_CLR). - * - * This function disables the bus protection bits previously enabled with - * mtk_infracfg_set_bus_protection. - */ - -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - int ret; - u32 val; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index c9c3cf7..b603af7 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -10,8 +10,8 @@ #include #include #include +#include #include -#include #include #include @@ -78,6 +78,29 @@ #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ #define PWR_STATUS_WB BIT(27) /* MT7622 */ +#define INFRA_TOPAXI_PROTECTEN 0x0220 +#define INFRA_TOPAXI_PROTECTSTA1 0x0228 +#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 +#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 + +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) + +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ + BIT(28)) +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ + BIT(7) | BIT(8)) + +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) + #define MAX_CLKS 3 /** @@ -251,25 +274,50 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) static int scpsys_bus_protect_enable(struct scp_domain *scpd) { struct scp *scp = scpd->scp; + struct regmap *infracfg = scp->infracfg; + u32 mask = scpd->data->bus_prot_mask; + bool reg_update = scp->bus_prot_reg_update; + u32 val; + int ret; - if (!scpd->data->bus_prot_mask) + if (!mask) return 0; - return mtk_infracfg_set_bus_protection(scp->infracfg, - scpd->data->bus_prot_mask, - scp->bus_prot_reg_update); + if (reg_update) + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, + mask); + else + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); + + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, + val, (val & mask) == mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + + return ret; } static int scpsys_bus_protect_disable(struct scp_domain *scpd) { struct scp *scp = scpd->scp; + struct regmap *infracfg = scp->infracfg; + u32 mask = scpd->data->bus_prot_mask; + bool reg_update = scp->bus_prot_reg_update; + u32 val; + int ret; - if (!scpd->data->bus_prot_mask) + if (!mask) return 0; - return mtk_infracfg_clear_bus_protection(scp->infracfg, - scpd->data->bus_prot_mask, - scp->bus_prot_reg_update); + if (reg_update) + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); + else + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); + + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, + val, !(val & mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + + return ret; } static int scpsys_power_on(struct generic_pm_domain *genpd) diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h deleted file mode 100644 index fd25f01..0000000 --- a/include/linux/soc/mediatek/infracfg.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __SOC_MEDIATEK_INFRACFG_H -#define __SOC_MEDIATEK_INFRACFG_H - -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) - -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) - -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ - BIT(28)) -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ - BIT(7) | BIT(8)) - -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -#endif /* __SOC_MEDIATEK_INFRACFG_H */ From patchwork Wed Jun 17 07:05:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7ABA8138C for ; Wed, 17 Jun 2020 07:16:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB528206F1 for ; Wed, 17 Jun 2020 07:16:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="L6ckKQMx"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iKmH3buq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB528206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=g6lmbmiDbXijQT0TTbcqixsRMKEfY+sy1shjLKXHdto=; b=L6ckKQMxicSNt9 4kTKSmEh8PFN8s8MuTXWLDmnILpk1pBiEx4JoKvi8bFke12bcak+slje4zVqSmsfAbq67O2/Qv+b7 tU0nPhkJRR/QTnyPGqDJGGCl6s+T5qRRPBggotXh49ERLqeO02+ipzhyOXIh2qHQyeeXFRafxVww5 1WKGBFrGyAFYq/XvjnPNAJSbtEGgYl7rj+s2yHYZJ5hQg+GGVl1iZsDtHWtuasAwxNO1t/zPppGfP Hg+SQA4Yqt9ZTnUrxM8codnaurBpL7ARZkw+YZGC+pWVlkvKp8Vo3WIGGJ/hDmjnja28zmtFrnxo2 mfcVVhAZRiRcn9mf6GJQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSJW-0003VM-4v; Wed, 17 Jun 2020 07:16:50 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIG-0002KJ-1I; Wed, 17 Jun 2020 07:15:35 +0000 X-UUID: 0542e332eef04b7589f7765ceadbbd21-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kKoPuuM3tPCNIWaBDJk8jsXvzDmvWQKPB2JtN+tCnAA=; b=iKmH3buqdlD89yQY4+HENskl8teRrh6jJMXKAPYcMMXQsEKnY8CTU+eYZcm7qI5iZSs+MxohvSqFC5FVZDGj0/HuroosXheH8K5ZdN3yrkdmLVRsLaiJbJ0Q9BvmRbjwlcUFxP9vuhzA9afvU7xDNQ9FYRreOlvRi/rou7AtVCY=; X-UUID: 0542e332eef04b7589f7765ceadbbd21-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1422043672; Tue, 16 Jun 2020 23:15:14 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:23 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 05/11] soc: mediatek: Add multiple step bus protection control Date: Wed, 17 Jun 2020 15:05:11 +0800 Message-ID: <1592377517-14817-6-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001532_132285_ACB13B9C X-CRM114-Status: GOOD ( 15.53 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Both MT8183 & MT6765 have more control steps of bus protection than previous project. And there add more bus protection registers reside at infracfg & smi-common. Extend function to support multiple step bus protection control with more customized arguments. And then use bp_table for bus protection of all compatibles, instead of mixing bus_prot_mask and bus_prot_reg_update. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 235 +++++++++++++++++++++++++++----------- 1 file changed, 168 insertions(+), 67 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index b603af7..59a525a 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -78,11 +78,6 @@ #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ #define PWR_STATUS_WB BIT(27) /* MT7622 */ -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - #define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) #define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) #define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) @@ -103,6 +98,45 @@ #define MAX_CLKS 3 +#define MAX_STEPS 4 + +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \ + .type = _type, \ + .set_ofs = _set_ofs, \ + .clr_ofs = _clr_ofs, \ + .en_ofs = _en_ofs, \ + .sta_ofs = _sta_ofs, \ + .mask = _mask, \ + .ignore_clr_ack = _ignore_clr_ack, \ + } + +#define BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask) \ + _BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask, false) + +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask) \ + _BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask, true) + +enum regmap_type { + INVALID_TYPE = 0, + IFR_TYPE, + SMI_TYPE, +}; + +struct bus_prot { + enum regmap_type type; + u32 set_ofs; + u32 clr_ofs; + u32 en_ofs; + u32 sta_ofs; + u32 mask; + bool ignore_clr_ack; +}; + /** * struct scp_domain_data - scp domain data for power on/off flow * @name: The domain name. @@ -110,9 +144,9 @@ * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. - * @bus_prot_mask: The mask for single step bus protection. * @basic_clk_name: The basic clocks required by this power domain. * @caps: The flag for active wake-up action. + * @bp_table: The mask table for multiple step bus protection. */ struct scp_domain_data { const char *name; @@ -120,9 +154,9 @@ struct scp_domain_data { int ctl_offs; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; - u32 bus_prot_mask; const char *basic_clk_name[MAX_CLKS]; u8 caps; + struct bus_prot bp_table[MAX_STEPS]; }; struct scp; @@ -146,8 +180,8 @@ struct scp { struct device *dev; void __iomem *base; struct regmap *infracfg; + struct regmap *smi_common; struct scp_ctrl_reg ctrl_reg; - bool bus_prot_reg_update; }; struct scp_subdomain { @@ -161,7 +195,6 @@ struct scp_soc_data { const struct scp_subdomain *subdomains; int num_subdomains; const struct scp_ctrl_reg regs; - bool bus_prot_reg_update; }; static int scpsys_domain_is_on(struct scp_domain *scpd) @@ -271,53 +304,87 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } +static int set_bus_protection(struct regmap *map, const struct bus_prot *bp) +{ + u32 val; + + if (bp->set_ofs) + regmap_write(map, bp->set_ofs, bp->mask); + else + regmap_update_bits(map, bp->en_ofs, bp->mask, bp->mask); + + return regmap_read_poll_timeout(map, bp->sta_ofs, + val, (val & bp->mask) == bp->mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int clear_bus_protection(struct regmap *map, const struct bus_prot *bp) +{ + u32 val; + + if (bp->clr_ofs) + regmap_write(map, bp->clr_ofs, bp->mask); + else + regmap_update_bits(map, bp->en_ofs, bp->mask, 0); + + if (bp->ignore_clr_ack) + return 0; + + return regmap_read_poll_timeout(map, bp->sta_ofs, + val, !(val & bp->mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + static int scpsys_bus_protect_enable(struct scp_domain *scpd) { struct scp *scp = scpd->scp; + const struct bus_prot *bp_table = scpd->data->bp_table; struct regmap *infracfg = scp->infracfg; - u32 mask = scpd->data->bus_prot_mask; - bool reg_update = scp->bus_prot_reg_update; - u32 val; - int ret; + struct regmap *smi_common = scp->smi_common; + struct regmap *map; + int i, ret; - if (!mask) - return 0; + for (i = 0; i < MAX_STEPS; i++) { + if (bp_table[i].type == IFR_TYPE) + map = infracfg; + else if (bp_table[i].type == SMI_TYPE) + map = smi_common; + else + break; - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, - mask); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); + ret = set_bus_protection(map, &bp_table[i]); - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, (val & mask) == mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret) + return ret; + } - return ret; + return 0; } static int scpsys_bus_protect_disable(struct scp_domain *scpd) { struct scp *scp = scpd->scp; + const struct bus_prot *bp_table = scpd->data->bp_table; struct regmap *infracfg = scp->infracfg; - u32 mask = scpd->data->bus_prot_mask; - bool reg_update = scp->bus_prot_reg_update; - u32 val; - int ret; + struct regmap *smi_common = scp->smi_common; + struct regmap *map; + int i, ret; - if (!mask) - return 0; + for (i = MAX_STEPS - 1; i >= 0; i--) { + if (bp_table[i].type == IFR_TYPE) + map = infracfg; + else if (bp_table[i].type == SMI_TYPE) + map = smi_common; + else + continue; - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); + ret = clear_bus_protection(map, &bp_table[i]); - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret) + return ret; + } - return ret; + return 0; } static int scpsys_power_on(struct generic_pm_domain *genpd) @@ -448,8 +515,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk, static struct scp *init_scp(struct platform_device *pdev, const struct scp_domain_data *scp_domain_data, int num, - const struct scp_ctrl_reg *scp_ctrl_reg, - bool bus_prot_reg_update) + const struct scp_ctrl_reg *scp_ctrl_reg) { struct genpd_onecell_data *pd_data; struct resource *res; @@ -463,8 +529,6 @@ static struct scp *init_scp(struct platform_device *pdev, scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs; scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs; - scp->bus_prot_reg_update = bus_prot_reg_update; - scp->dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -492,6 +556,17 @@ static struct scp *init_scp(struct platform_device *pdev, return ERR_CAST(scp->infracfg); } + scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "mediatek,smi"); + + if (scp->smi_common == ERR_PTR(-ENODEV)) { + scp->smi_common = NULL; + } else if (IS_ERR(scp->smi_common)) { + dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n", + PTR_ERR(scp->smi_common)); + return ERR_CAST(scp->smi_common); + } + for (i = 0; i < num; i++) { struct scp_domain *scpd = &scp->domains[i]; const struct scp_domain_data *data = &scp_domain_data[i]; @@ -574,8 +649,11 @@ static void mtk_register_power_domains(struct platform_device *pdev, .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | - MT2701_TOP_AXI_PROT_EN_CONN_S, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT2701_TOP_AXI_PROT_EN_CONN_M | + MT2701_TOP_AXI_PROT_EN_CONN_S), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_DISP] = { @@ -584,7 +662,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .basic_clk_name = {"mm"}, - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT2701_TOP_AXI_PROT_EN_MM_M0), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2701_POWER_DOMAIN_MFG] = { @@ -719,7 +800,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(16, 16), .basic_clk_name = {"mfg"}, - .bus_prot_mask = BIT(14) | BIT(21) | BIT(23), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228, + BIT(14) | BIT(21) | BIT(23)), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT2712_POWER_DOMAIN_MFG_SC1] = { @@ -791,7 +875,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .basic_clk_name = {"mm"}, - .bus_prot_mask = (BIT(1) | BIT(2)), + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + BIT(1) | BIT(2)), + }, }, [MT6797_POWER_DOMAIN_AUDIO] = { .name = "audio", @@ -838,7 +925,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_ETHSYS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT7622_TOP_AXI_PROT_EN_ETHSYS), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7622_POWER_DOMAIN_HIF0] = { @@ -848,7 +938,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .basic_clk_name = {"hif_sel"}, - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT7622_TOP_AXI_PROT_EN_HIF0), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7622_POWER_DOMAIN_HIF1] = { @@ -858,7 +951,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .basic_clk_name = {"hif_sel"}, - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT7622_TOP_AXI_PROT_EN_HIF1), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7622_POWER_DOMAIN_WB] = { @@ -867,7 +963,10 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_WB_PWR_CON, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, - .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT7622_TOP_AXI_PROT_EN_WB), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM, }, }; @@ -881,8 +980,11 @@ static void mtk_register_power_domains(struct platform_device *pdev, .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, - .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M | - MT2701_TOP_AXI_PROT_EN_CONN_S, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT2701_TOP_AXI_PROT_EN_CONN_M | + MT2701_TOP_AXI_PROT_EN_CONN_S), + }, .caps = MTK_SCPD_ACTIVE_WAKEUP, }, [MT7623A_POWER_DOMAIN_ETH] = { @@ -947,8 +1049,11 @@ static void mtk_register_power_domains(struct platform_device *pdev, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .basic_clk_name = {"mm"}, - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), + }, }, [MT8173_POWER_DOMAIN_VENC_LT] = { .name = "venc_lt", @@ -994,10 +1099,13 @@ static void mtk_register_power_domains(struct platform_device *pdev, .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, + .bp_table = { + BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228, + MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), + }, }, }; @@ -1013,7 +1121,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND }, - .bus_prot_reg_update = true, }; static const struct scp_soc_data mt2712_data = { @@ -1025,7 +1132,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND }, - .bus_prot_reg_update = false, }; static const struct scp_soc_data mt6797_data = { @@ -1037,7 +1143,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS_MT6797, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797 }, - .bus_prot_reg_update = true, }; static const struct scp_soc_data mt7622_data = { @@ -1047,7 +1152,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND }, - .bus_prot_reg_update = true, }; static const struct scp_soc_data mt7623a_data = { @@ -1057,7 +1161,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND }, - .bus_prot_reg_update = true, }; static const struct scp_soc_data mt8173_data = { @@ -1069,7 +1172,6 @@ static void mtk_register_power_domains(struct platform_device *pdev, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND }, - .bus_prot_reg_update = true, }; /* @@ -1110,8 +1212,7 @@ static int scpsys_probe(struct platform_device *pdev) soc = of_device_get_match_data(&pdev->dev); - scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs, - soc->bus_prot_reg_update); + scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs); if (IS_ERR(scp)) return PTR_ERR(scp); From patchwork Wed Jun 17 07:05:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609159 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CECBE912 for ; Wed, 17 Jun 2020 07:15:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3844206F1 for ; Wed, 17 Jun 2020 07:15:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="McvB7mAY"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UQuFKEjh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3844206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Nm/NjA3cNuOf5julZ+ioCj6/G8ZggQWCemz/QYlOTME=; b=McvB7mAYcCAXQy jCEL2d36xa/RUpKvr6RRGOCsEpoPWj/6izITMbMXtw/+kNJNmHHi21PRzj4h2gULDlOUn9qtKfXO8 +ygLUci2XgPGX/IMz1xMz9EQLTjckW6OF/Io4yzlfWClCWtpmxSWO9bkQu7J7dxleyYer0MFUSzih 1iLBLib4JYQMBXHFvUVO5+CVyTjvL33KYEsRvFb98Bl7IVmDSFGDR+ObGCNH7wCz1pamr9x+vsIlr Z7hb+kyVdvwtB/lRepJt/B6n6aIkVmjcsGJRab91Fvxu1Tj6iRG5QMs9e6SGraQ3SFJu31lwADdFR vuArfjFaMe+FqzqBSFZg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIH-0002NM-1v; Wed, 17 Jun 2020 07:15:33 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSID-0002JY-5y; Wed, 17 Jun 2020 07:15:30 +0000 X-UUID: fc014813c4f6451897d9ac5735f1d6c0-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oknxkN93lM10p7H+ZOPQmB3ANyUU8TNjZxsOq9hhIMc=; b=UQuFKEjhqAh7OKPmv4EzqpQgbAqDbCBfh8HRf+sHmkOvhP3U649f++4Lkfz+arz1GsS8pRFDFE0/FW8vIhURkcOWKs/9P9+kBmiyZz6h118K4xvA3crQ7lKsCFYd1rx7Xpvh0LaxaLqIf17jS97XWRaIc1+Oy+U5qMmiKI9QL1U=; X-UUID: fc014813c4f6451897d9ac5735f1d6c0-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 447947076; Tue, 16 Jun 2020 23:15:14 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:24 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 06/11] soc: mediatek: Add subsys clock control for bus protection Date: Wed, 17 Jun 2020 15:05:12 +0800 Message-ID: <1592377517-14817-7-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001529_239360_62ED8345 X-CRM114-Status: GOOD ( 15.62 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org For the bus protection operations, some subsys clocks need to be enabled before releasing the protection, and vice versa. But those subsys clocks could only be controlled once its corresponding power domain is turned on first. In this patch, we add the subsys clock control into its relevant steps. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 58 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 59a525a..a567346 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -97,6 +97,7 @@ #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) #define MAX_CLKS 3 +#define MAX_SUBSYS_CLKS 10 #define MAX_STEPS 4 @@ -145,6 +146,8 @@ struct bus_prot { * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @basic_clk_name: The basic clocks required by this power domain. + * @subsys_clk_prefix: The prefix name of the clocks need to be enabled + * before releasing bus protection. * @caps: The flag for active wake-up action. * @bp_table: The mask table for multiple step bus protection. */ @@ -155,6 +158,7 @@ struct scp_domain_data { u32 sram_pdn_bits; u32 sram_pdn_ack_bits; const char *basic_clk_name[MAX_CLKS]; + const char *subsys_clk_prefix; u8 caps; struct bus_prot bp_table[MAX_STEPS]; }; @@ -165,6 +169,7 @@ struct scp_domain { struct generic_pm_domain genpd; struct scp *scp; struct clk *clk[MAX_CLKS]; + struct clk *subsys_clk[MAX_SUBSYS_CLKS]; const struct scp_domain_data *data; struct regulator *supply; }; @@ -425,16 +430,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) val |= PWR_RST_B_BIT; writel(val, ctl_addr); - ret = scpsys_sram_enable(scpd, ctl_addr); + ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS); if (ret < 0) goto err_pwr_ack; + ret = scpsys_sram_enable(scpd, ctl_addr); + if (ret < 0) + goto err_sram; + ret = scpsys_bus_protect_disable(scpd); if (ret < 0) - goto err_pwr_ack; + goto err_sram; return 0; +err_sram: + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS); err_pwr_ack: scpsys_clk_disable(scpd->clk, MAX_CLKS); err_clk: @@ -461,6 +472,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) goto out; + scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS); + /* subsys power off */ val = readl(ctl_addr); val |= PWR_ISO_BIT; @@ -498,6 +511,39 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) return ret; } +static int init_subsys_clks(struct platform_device *pdev, + const char *prefix, struct clk **clk) +{ + struct device_node *node = pdev->dev.of_node; + u32 prefix_len, sub_clk_cnt = 0; + struct property *prop; + const char *clk_name; + + prefix_len = strlen(prefix); + + of_property_for_each_string(node, "clock-names", prop, clk_name) { + if (!strncmp(clk_name, prefix, prefix_len) && + (clk_name[prefix_len] == '-')) { + if (sub_clk_cnt >= MAX_SUBSYS_CLKS) { + dev_err(&pdev->dev, + "subsys clk out of range %d\n", + sub_clk_cnt); + return -EINVAL; + } + + clk[sub_clk_cnt] = devm_clk_get(&pdev->dev, + clk_name); + + if (IS_ERR(clk[sub_clk_cnt])) + return PTR_ERR(clk[sub_clk_cnt]); + + sub_clk_cnt++; + } + } + + return sub_clk_cnt; +} + static int init_basic_clks(struct platform_device *pdev, struct clk **clk, const char * const *name) { @@ -596,6 +642,14 @@ static struct scp *init_scp(struct platform_device *pdev, if (ret) return ERR_PTR(ret); + if (data->subsys_clk_prefix) { + ret = init_subsys_clks(pdev, + data->subsys_clk_prefix, + scpd->subsys_clk); + if (ret < 0) + return ERR_PTR(ret); + } + genpd->name = data->name; genpd->power_off = scpsys_power_off; genpd->power_on = scpsys_power_on; From patchwork Wed Jun 17 07:05:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9B9D7138C for ; Wed, 17 Jun 2020 07:16:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A0B7206F1 for ; Wed, 17 Jun 2020 07:16:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="RH9APHjk"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="XbaFIHaU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7A0B7206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tuxsPR3KLq31M14HlLbaJhdX00rDDyJvc1WP86P/NJk=; b=RH9APHjkboMuol Zyq4W43tJuSiRBfjJnX5CVS7G1AWtOW8Nee4Ad56kSLn+qw8lnJCCa0q/DjXYDTp8QZjGqU/9UrUj wf376U3xRMsZgPfZPjWUj8yxvBY8U9lSfSCPfac8Wu3yFGB2W4ogACYlgC8fOihFg1SB77c5yUxN1 wDQzpuFkjPikaZV5R8Ik7ayCdYcyjpZFTs+SweDs5GQl8p83CRG5vwi6BYD6s2R7A6/EW2QMeGq54 uqb5D+QaFmBIpEgzsZDLSqj+Da5XV/r0mkLUR/uoeEywsbI4tM192TKHbRnV7Wuwyb8Wg+XS7ubQk ntCoDjceIaItN9IoevCg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSJ1-0002xY-3J; Wed, 17 Jun 2020 07:16:19 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIE-0002JY-Ng; Wed, 17 Jun 2020 07:15:32 +0000 X-UUID: d6a11b0bf2f9463ebbfb16873fa6bf46-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ERBWBQKk5eOWSM1XMJj30bh4UNq1SbvG0GoU5eyQTK8=; b=XbaFIHaUaneTuNN9l8BlamQmfDUFUM7j6GSvIobwfegNkky1Z+pMirPOd4HDvWHnsaCr9gmWpNmqr8Q1Dz5hX8KKCfw0yAoy1ZG50tRyLqImT5j6xLyPdKXb/siFL6W2RR16L0PY1Gf6FR59LhucpbNVA3DMiMs+szpYSQjhCrM=; X-UUID: d6a11b0bf2f9463ebbfb16873fa6bf46-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1693696315; Tue, 16 Jun 2020 23:15:14 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:24 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 07/11] soc: mediatek: Add extra sram control Date: Wed, 17 Jun 2020 15:05:13 +0800 Message-ID: <1592377517-14817-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001530_778880_05CD0783 X-CRM114-Status: GOOD ( 10.81 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index a567346..360d559 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -25,6 +25,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -56,6 +57,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) @@ -290,6 +293,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr) return ret; } + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + } + return 0; } @@ -299,8 +310,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr) u32 pdn_ack = scpd->data->sram_pdn_ack_bits; int tmp; - val = readl(ctl_addr); - val |= scpd->data->sram_pdn_bits; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val = readl(ctl_addr) | PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + val &= ~PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + } + + val = readl(ctl_addr) | scpd->data->sram_pdn_bits; writel(val, ctl_addr); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ From patchwork Wed Jun 17 07:05:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 01952912 for ; Wed, 17 Jun 2020 07:18:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D2561206F1 for ; Wed, 17 Jun 2020 07:18:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rsNu9/UW"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="DE6QHGHk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D2561206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7NEDwN+oqTEiIXTJ255Wc6XY4SVgCeL7Wusnl2FbtzA=; b=rsNu9/UWMUP3hz Mvf+sVNvsVay63i8Ar35dHoleQQmgJoiDF338PNSTECPh6V/yaMjX87/Lm61oPPvpi/rVL4fZCxpI sfHLhRdc5GW2208JW34KGAXKWXM4z69Zh9wi2FJbUFL4ckv80YZk1J2tKz1c9qO+nKIAnvPx3c724 ufxJw/mf1jZYKF4DzkeKpGe6AShDEfJrx5c28I9/0RHrbAhZVAFZNxp8Dtgtst/H69m2EJ14RB746 ezYCJ4KL+LEpoQQyBQXNpJ3prV71/8r1+1Bq0Su0NGw0Fbeb7POG5yI7ps+KVFTcBJc/xxm5/KpLp uHi+jiP/gvjusDbUwexg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSKg-0004hj-R3; Wed, 17 Jun 2020 07:18:02 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIQ-0002SX-VJ; Wed, 17 Jun 2020 07:15:45 +0000 X-UUID: cf808bd546bb4dc3b2ae9446020b1048-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nMiaB+wp95PlwSKkvOR/IQt11hprLc2FY3shehBi0Eg=; b=DE6QHGHkMye0v/Ev+Mk5V888sQpFiZLlqd0wy4xNuBQsTtTSBZdPgI2T/byZ1VUPPlLP13aDNj68gvskayqC6oV0D472yCbwlzJ8MVKMCEcW1QlpnT/DkgvyhWT8wUHu3TWmE4hw7rhCMZReL3IEwppLvjLWHAr1LK5WoaKoaJY=; X-UUID: cf808bd546bb4dc3b2ae9446020b1048-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 657674747; Tue, 16 Jun 2020 23:15:21 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:32 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 08/11] soc: mediatek: Add MT8183 scpsys support Date: Wed, 17 Jun 2020 15:05:14 +0800 Message-ID: <1592377517-14817-9-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4D12B881769B9FFD39BD51FF810AC2685EDD229115B4DC69510F9928CD92982F2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001543_429712_08B053F7 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add scpsys driver for MT8183 Signed-off-by: Weiyi Lu Reviewed-by: Nicolas Boichat --- drivers/soc/mediatek/mtk-scpsys.c | 249 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 249 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 360d559..abdbab4 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -19,6 +19,7 @@ #include #include #include +#include #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -99,6 +100,34 @@ #define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) +#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14)) +#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22)) +#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28) +#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27) +#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17)) +#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8)) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \ + BIT(9) | BIT(13)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \ + BIT(12)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \ + BIT(4)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \ + BIT(5)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7) +#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0) +#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1) +#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2) +#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7) + #define MAX_CLKS 3 #define MAX_SUBSYS_CLKS 10 @@ -1186,6 +1215,212 @@ static void mtk_register_power_domains(struct platform_device *pdev, {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; +/* + * MT8183 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .basic_clk_name = {"audio", "audio1", "audio2"}, + }, + [MT8183_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_CONN), + }, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .name = "mfg_async", + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_name = {"mfg"}, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .name = "mfg_core0", + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .name = "mfg_core1", + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .name = "mfg_2d", + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + MT8183_TOP_AXI_PROT_EN_1_MFG), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_MFG), + }, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"mm"}, + .subsys_clk_prefix = "mm", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258, + MT8183_TOP_AXI_PROT_EN_1_DISP), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_DISP), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_DISP), + }, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"cam"}, + .subsys_clk_prefix = "cam", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_CAM), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_CAM), + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_CAM), + }, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"isp"}, + .subsys_clk_prefix = "isp", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_ISP), + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_ISP), + }, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VDEC), + }, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_table = { + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VENC), + }, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .name = "vpu_top", + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"vpu", "vpu1"}, + .subsys_clk_prefix = "vpu", + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228, + MT8183_TOP_AXI_PROT_EN_VPU_TOP), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec, + MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND), + BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0, + MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .name = "vpu_core0", + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"vpu2"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .name = "vpu_core1", + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .basic_clk_name = {"vpu3"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1), + BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4, + MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8183[] = { + {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0}, + {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC}, + {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0}, + {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1}, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -1246,6 +1481,17 @@ static void mtk_register_power_domains(struct platform_device *pdev, }, }; +static const struct scp_soc_data mt8183_data = { + .domains = scp_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8183), + .subdomains = scp_subdomain_mt8183, + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183), + .regs = { + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 + } +}; + /* * scpsys driver init */ @@ -1270,6 +1516,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt8173-scpsys", .data = &mt8173_data, }, { + .compatible = "mediatek,mt8183-scpsys", + .data = &mt8183_data, + }, { /* sentinel */ } }; From patchwork Wed Jun 17 07:05:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609135 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9ED32138C for ; Wed, 17 Jun 2020 07:05:33 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7527A208D5 for ; Wed, 17 Jun 2020 07:05:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="iMfofIWD"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="UMXRRiIS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7527A208D5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KOZzPQYXk4lRdkmzfr3Ab36gqblpuXk4X9PbOrhaQ/8=; b=iMfofIWDHo/O1w kJbkGal3isDhw2IAoeU+bB7dvLfkGdmlAufd08YWcj9Tl0JnXaXvvAxeVdLu84sMQUW4WdCEtfXJf ef7sbYAqYaupDnulOn6dKifz151g1u0C/iuWasNvF4AW7JlXmRGIjZJElKYt7DGGoAkbqwzOEJPHv V78JR8Ujd9JO9gJ/io2OY09g0Yy1nspKo/tZYX+UcDgPpo7AjIVbfclKhKsZthcCKnCR5a8EpGoEk b5sFtAQT0GaPd9RtcrNFaUAWMYjLbIMQMyqA4xj+P0WeAoaSR4oAu7NT8FMXtIcXRYWOJMKufJbD9 Icj5AFrpJH1p7rslclRw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlS8a-0002qL-CO; Wed, 17 Jun 2020 07:05:32 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlS8Y-0002ox-MC; Wed, 17 Jun 2020 07:05:32 +0000 X-UUID: 25d9be4e02b04cccabebb63b59fc6a90-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=OBPtD1tbN5OV8vnvCeCNDHHxC6o81b/X9CvevB+bOCk=; b=UMXRRiIS1Zw0twgr0iU3FrzT+pTpbZotUbCNvZJPfuKttG4gMqwN0aXRcMJGmHexGYeb6ZConK+hxyEzB/bUT/ID3nHkF/ORANjl4ghrmU/YPJFNX+1PJkvOjd9kOTCMe8FBGpFNHEL8lZN3zpg8BuaBjqOltyuiM8Hvjx1td0M=; X-UUID: 25d9be4e02b04cccabebb63b59fc6a90-20200616 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 957038197; Tue, 16 Jun 2020 23:05:15 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:26 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 09/11] soc: mediatek: Add a comma at the end Date: Wed, 17 Jun 2020 15:05:15 +0800 Message-ID: <1592377517-14817-10-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F9D2535231E86EDD4072917BE38EC826236484326466FD89AC619CA89CE359B92000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_000530_734284_DD6F73D7 X-CRM114-Status: UNSURE ( 8.30 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org A minor coding style fix Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/mtk-scpsys.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index abdbab4..5bfe58a 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -1426,7 +1426,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }, }; @@ -1437,7 +1437,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }, }; @@ -1448,7 +1448,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797), .regs = { .pwr_sta_offs = SPM_PWR_STATUS_MT6797, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797 + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797, }, }; @@ -1457,7 +1457,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_domains = ARRAY_SIZE(scp_domain_data_mt7622), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }, }; @@ -1466,7 +1466,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }, }; @@ -1477,7 +1477,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173), .regs = { .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }, }; @@ -1488,7 +1488,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183), .regs = { .pwr_sta_offs = 0x0180, - .pwr_sta2nd_offs = 0x0184 + .pwr_sta2nd_offs = 0x0184, } }; From patchwork Wed Jun 17 07:05:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609165 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0ED1A138C for ; Wed, 17 Jun 2020 07:16:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E0EAD206F1 for ; Wed, 17 Jun 2020 07:16:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="QYjAtkl3"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="RwZkx60X" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E0EAD206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=B5q20rC0RAi7DLJgJ5YzYOcYT9C00GjdCVBw3RtxNLA=; b=QYjAtkl3g8+ghq 0KyXxCA5nmyPNZq+ziNz0HeH9rVBnbmO42iyCkHS0xJZYrcpU8iMqmC7nJ+0czHDxjt5WEyjs63+b KnHgOr0HZI/QTaYIw+AjLkiOV/IVQMgtCQtYP20ec7SEjn2Sm1hJQt4cX0cUmBpAjTsIXClXDfVKp w1CpZl395ctR0BKGloPcw/Cm0SaSTi4PVu8HEMoSwVy9WtbTNwr42O3yF+4mJhUopbYaHOaUk2JHE tZ/UJMuSdqApPAzbokIZrlUrTio6vnggKv/mpYASAhlzVkwqL7QZh3kLjJf/yDHRdVGOjQRmkfoxM ncFz2AUQ64UwZDm5nVbw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIy-0002vQ-81; Wed, 17 Jun 2020 07:16:16 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIE-0002KJ-CL; Wed, 17 Jun 2020 07:15:32 +0000 X-UUID: 1d193512d96a4fe1ab8056aae21fd819-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=J6PkgKbPUDbilo/J8y2lejIVLu5Hr7UYF5ePvMS/4r4=; b=RwZkx60XGP/l1roAw4lyCgziumcXsOzWQ1iYRAcbZ4IqWPTG+GRf8LVNCD6ZHC36NMjjAkAp7Oe4/5Fk2Oapb+efkShfhHJTcxgvlWO13CzGxpENeIxDjU/y13InF5RBCtzrSfH8Zjn+I6vNs1l3wSKNeUYmWoSDBBQBRlxi4H4=; X-UUID: 1d193512d96a4fe1ab8056aae21fd819-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 587052734; Tue, 16 Jun 2020 23:15:14 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:24 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:23 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 10/11] arm64: dts: Add power controller device node of MT8183 Date: Wed, 17 Jun 2020 15:05:16 +0800 Message-ID: <1592377517-14817-11-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001530_420757_465BD829 X-CRM114-Status: UNSURE ( 8.19 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org Add power controller node and smi-common node for MT8183 In scpsys node, it contains clocks and regmapping of infracfg and smi-common for bus protection. Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1e03c84..5b25471 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mt8183-pinfunc.h" @@ -309,6 +310,62 @@ #interrupt-cells = <2>; }; + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8183-scpsys", "syscon"; + #power-domain-cells = <1>; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_MM>, + <&topckgen CLK_TOP_MUX_CAM>, + <&topckgen CLK_TOP_MUX_IMG>, + <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&topckgen CLK_TOP_MUX_DSP1>, + <&topckgen CLK_TOP_MUX_DSP2>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>, + <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>, + <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>, + <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + clock-names = "audio", "audio1", "audio2", + "mfg", "mm", "cam", + "isp", "vpu", "vpu1", + "vpu2", "vpu3", "mm-0", + "mm-1", "mm-2", "mm-3", + "mm-4", "mm-5", "mm-6", + "mm-7", "mm-8", "mm-9", + "isp-0", "isp-1", "cam-0", + "cam-1", "cam-2", "cam-3", + "cam-4", "cam-5", "cam-6", + "vpu-0", "vpu-1", "vpu-2", + "vpu-3", "vpu-4", "vpu-5"; + infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt", "mediatek,mt6589-wdt"; @@ -690,6 +747,11 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; From patchwork Wed Jun 17 07:05:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11609195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3D52B912 for ; Wed, 17 Jun 2020 07:18:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C1D3206F1 for ; Wed, 17 Jun 2020 07:18:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ihaaVoQP"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YzDmlKWW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C1D3206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nWR23w+g7g2bheD7wcokfhOavxI9ZTwHz600XnmcSdg=; b=ihaaVoQPAHU6iL LKmhwNmGBfVvTiB9QOTmH8J/XjAIdEMU38QZ0wOziu6QW0RMaYt2qAtMcOhwaQHv/tZvmoZSqegI8 pRqM9sMUE6qbK/UaHI0OhNkE5O4+qNVb+0tn3Yb+r1xXvKb9bBZxqIMlbjjvTJMB+wkpEGUkakpSk UpSVgp6xZWZTWncNKYVRtW6YyprFylDssHfd0WiweEy25kYtIuXz9letChOg01T2i27XD9yDVifZU zjcksJ1Lvjj/HK3p2E4mv8WDllrtBZBHa9vb51Z48Y4uRARCj3uO1zDqDW3Eg5G2RG9cgjZARhOCE jEdt4kCO3oDgG5QXTMeA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSKe-0004ev-Mb; Wed, 17 Jun 2020 07:18:00 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jlSIP-0002SX-20; Wed, 17 Jun 2020 07:15:42 +0000 X-UUID: 94f63ff9126a4e299cd81ec2a0d9a4cd-20200616 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EOcdF6c4lxh325Yf6ca/i0y7GzdPS61sJIDefIc6ekI=; b=YzDmlKWWV3iAl1Gx32D6Xo6DYQTb0Um2ZySFZUw9X11N+sKNsaTQyYKt76ebZN/BWDMpznrtqLcCTF96PqYXalmOxxkhQ03Ji1d0GzCN1NmHKpMk7kgU7lSPd7QbH7dXiG4fMxNuHyN5FObkU6y4T/BMFWkDbJJHzFKLJQHkrKQ=; X-UUID: 94f63ff9126a4e299cd81ec2a0d9a4cd-20200616 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1433291236; Tue, 16 Jun 2020 23:15:21 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 00:05:32 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 17 Jun 2020 15:05:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 17 Jun 2020 15:05:24 +0800 From: Weiyi Lu To: Enric Balletbo Serra , Matthias Brugger , Nicolas Boichat , "Rob Herring" , Sascha Hauer Subject: [PATCH v16 11/11] arm64: dts: Add power-domains property to mfgcfg Date: Wed, 17 Jun 2020 15:05:17 +0800 Message-ID: <1592377517-14817-12-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> References: <1592377517-14817-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E0538E3445DC83D05EAF78A941CB9151499653928802EA4C4C3F1D032245AF612000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200617_001541_250986_F3DC1F28 X-CRM114-Status: UNSURE ( 8.23 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, Wendell Lin , linux-arm-kernel@lists.infradead.org Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org mfgcfg clock is under MFG_ASYNC power domain Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5b25471..377f28d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -739,6 +739,7 @@ compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; #clock-cells = <1>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>; }; mmsys: syscon@14000000 {