From patchwork Fri Jun 19 12:57:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614123 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33ECA90 for ; Fri, 19 Jun 2020 12:59:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1144F20DD4 for ; Fri, 19 Jun 2020 12:59:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="PDUXpxru" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732563AbgFSM6a (ORCPT ); Fri, 19 Jun 2020 08:58:30 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55340 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728081AbgFSM63 (ORCPT ); Fri, 19 Jun 2020 08:58:29 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwAWU058249; Fri, 19 Jun 2020 07:58:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571490; bh=d4x8ogqFfDH2kB8gVKWGAaXg2kq+h2ME/W7y4f5BO40=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PDUXpxrukOrtOJBTvzXesACfJgIGJOjQdYY8SY1CAYHpMc5/9W5OSq41IGJ3F8bDs OSK25zdAkCupMQQ4zJQK4ON2mj5DqhJiVskH9f3DdDtcyU6Im+QSopHJucjDeaaS0e ZLORPMgTMWNRy3PTw+3h6VVWtRaKOY9rxZ4Z8WC4= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwAvC007140; Fri, 19 Jun 2020 07:58:10 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:10 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:10 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hl015675; Fri, 19 Jun 2020 07:58:07 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 1/7] dt-bindings: mmc: sdhci-am654: Add ti,clkbuf-sel binding Date: Fri, 19 Jun 2020 18:27:55 +0530 Message-ID: <20200619125801.9530-2-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add documentation for the clock buffer select phy property in the am654x and j721e 4 bit IP Signed-off-by: Faiz Abbas --- Documentation/devicetree/bindings/mmc/sdhci-am654.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt index c6ccecb9ae5a..6d202f4d9249 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -39,6 +39,7 @@ Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit): Valid values are 33, 40, 50, 66 and 100 ohms. Optional Properties: - ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0. + - ti,clkbuf-sel: Clock Delay Buffer Select Example: From patchwork Fri Jun 19 12:57:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614107 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 73D2D1746 for ; Fri, 19 Jun 2020 12:58:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5A3FF2083B for ; Fri, 19 Jun 2020 12:58:31 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="zCPXUfb3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732590AbgFSM6a (ORCPT ); Fri, 19 Jun 2020 08:58:30 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51676 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732495AbgFSM6a (ORCPT ); Fri, 19 Jun 2020 08:58:30 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwEZk082648; Fri, 19 Jun 2020 07:58:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571494; bh=1yyZ02rdUuurElexq779NNOoFqWvEfOJ8Vx4K01CaMQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zCPXUfb33ipipjCsbHs074rbzD6imzHxj+jvtm9s9hOx63ZR4eX80uUnwrq4GyTZR pH9dUrN1fJQQyb56D98ERrxE7SSuS2CmZNp/qts1kgrrgigIoobK6je0BTNyifqaue iJhXPf2aEGDpL2kxlZbHtQscelfeBM2pcFieRuns= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JCwEYN105675 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 07:58:14 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:14 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:14 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hm015675; Fri, 19 Jun 2020 07:58:11 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 2/7] mmc: sdhci_am654: Add flag for PHY calibration Date: Fri, 19 Jun 2020 18:27:56 +0530 Message-ID: <20200619125801.9530-3-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same. Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 061b4398a4f1..85a05344f825 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -97,6 +97,7 @@ struct sdhci_am654_driver_data { #define FREQSEL_2_BIT (1 << 1) #define STRBSEL_4_BIT (1 << 2) #define DLL_PRESENT (1 << 3) +#define DLL_CALIB (1 << 4) }; struct timing_data { @@ -325,7 +326,8 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = { static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { .pdata = &sdhci_am654_pdata, - .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | + DLL_CALIB, }; static struct sdhci_ops sdhci_j721e_8bit_ops = { @@ -348,7 +350,7 @@ static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { .pdata = &sdhci_j721e_8bit_pdata, - .flags = DLL_PRESENT, + .flags = DLL_PRESENT | DLL_CALIB, }; static struct sdhci_ops sdhci_j721e_4bit_ops = { @@ -469,7 +471,7 @@ static int sdhci_am654_init(struct sdhci_host *host) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); - if (sdhci_am654->flags & DLL_PRESENT) { + if (sdhci_am654->flags & DLL_CALIB) { regmap_read(sdhci_am654->base, PHY_STAT1, &val); if (~val & CALDONE_MASK) { /* Calibrate IO lines */ From patchwork Fri Jun 19 12:57:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614115 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CB6EF14B7 for ; Fri, 19 Jun 2020 12:58:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B3ADA208C7 for ; Fri, 19 Jun 2020 12:58:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="OaAhax4t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732703AbgFSM6j (ORCPT ); Fri, 19 Jun 2020 08:58:39 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35030 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732660AbgFSM6f (ORCPT ); Fri, 19 Jun 2020 08:58:35 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwJen076832; Fri, 19 Jun 2020 07:58:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571499; bh=PwbBrS5/93qfz/ERIiFrMFJ9ufsq6vvpld5u8B1rVWw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OaAhax4tGjxQR/5gRuR3ZACaUwao+J3cPA03IImLNm1YndigT5RpiG4soy/Yhh2// RjWaqVqnOBC/4zrN4jVl1GUaydtoduXTq1y2YbISCyhFaJ3VoQWApN/H1x7EM3HcVU 8a6Qxv8CBIFNPKRQOm+rSteo/v+l5rn5D23sMDQk= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JCwI94081089 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 07:58:19 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:18 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:18 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hn015675; Fri, 19 Jun 2020 07:58:15 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 3/7] mmc: sdhci_am654: Add Support for SR2.0 Date: Fri, 19 Jun 2020 18:27:57 +0530 Message-ID: <20200619125801.9530-4-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the driver data and skip do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 85a05344f825..365eb2819dd9 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "cqhci.h" #include "sdhci-pltfm.h" @@ -324,12 +325,17 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = { .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, }; -static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { +static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { .pdata = &sdhci_am654_pdata, .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | DLL_CALIB, }; +static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { + .pdata = &sdhci_am654_pdata, + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, +}; + static struct sdhci_ops sdhci_j721e_8bit_ops = { .get_max_clock = sdhci_pltfm_clk_get_max_clock, .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, @@ -376,6 +382,14 @@ static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { .flags = IOMUX_PRESENT, }; +static const struct soc_device_attribute sdhci_am654_devices[] = { + { .family = "AM65X", + .revision = "SR1.0", + .data = &sdhci_am654_sr1_drvdata + }, + {/* sentinel */} +}; + static void sdhci_am654_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -587,6 +601,7 @@ static const struct of_device_id sdhci_am654_of_match[] = { static int sdhci_am654_probe(struct platform_device *pdev) { const struct sdhci_am654_driver_data *drvdata; + const struct soc_device_attribute *soc; struct sdhci_pltfm_host *pltfm_host; struct sdhci_am654_data *sdhci_am654; const struct of_device_id *match; @@ -598,6 +613,12 @@ static int sdhci_am654_probe(struct platform_device *pdev) match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); drvdata = match->data; + + /* Update drvdata based on SoC revision */ + soc = soc_device_match(sdhci_am654_devices); + if (soc && soc->data) + drvdata = soc->data; + host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); if (IS_ERR(host)) return PTR_ERR(host); From patchwork Fri Jun 19 12:57:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8AF0014B7 for ; Fri, 19 Jun 2020 12:59:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72B5E21556 for ; Fri, 19 Jun 2020 12:59:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ebdgNmPH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732611AbgFSM6c (ORCPT ); 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Fri, 19 Jun 2020 07:58:22 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:22 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Ho015675; Fri, 19 Jun 2020 07:58:19 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 4/7] mmc: sdhci_am654: Fix conditions for enabling dll Date: Fri, 19 Jun 2020 18:27:58 +0530 Message-ID: <20200619125801.9530-5-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The clock > CLOCK_TOO_SLOW_HZ condition gating phy configuration is only required because dll should not be enabled at too low a clock frequency or too low timing. Make sure that this condition only gates dll enablement. Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 42 ++++++++++++++++------------------ 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 365eb2819dd9..8b0f69012d09 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -204,34 +204,32 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); - if (clock > CLOCK_TOO_SLOW_HZ) { - /* Setup DLL Output TAP delay */ - if (sdhci_am654->legacy_otapdly) - otap_del_sel = sdhci_am654->otap_del_sel[0]; - else - otap_del_sel = sdhci_am654->otap_del_sel[timing]; + /* Setup DLL Output TAP delay */ + if (sdhci_am654->legacy_otapdly) + otap_del_sel = sdhci_am654->otap_del_sel[0]; + else + otap_del_sel = sdhci_am654->otap_del_sel[timing]; - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; + otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; - mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (otap_del_ena << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + val = (otap_del_ena << OTAPDLYENA_SHIFT) | + (otap_del_sel << OTAPDLYSEL_SHIFT); - /* Write to STRBSEL for HS400 speed mode */ - if (timing == MMC_TIMING_MMC_HS400) { - if (sdhci_am654->flags & STRBSEL_4_BIT) - mask |= STRBSEL_4BIT_MASK; - else - mask |= STRBSEL_8BIT_MASK; + /* Write to STRBSEL for HS400 speed mode */ + if (timing == MMC_TIMING_MMC_HS400) { + if (sdhci_am654->flags & STRBSEL_4_BIT) + mask |= STRBSEL_4BIT_MASK; + else + mask |= STRBSEL_8BIT_MASK; - val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; - } + val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; + } - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25) - sdhci_am654_setup_dll(host, clock); - } + if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) + sdhci_am654_setup_dll(host, clock); } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, From patchwork Fri Jun 19 12:57:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614119 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A87614B7 for ; Fri, 19 Jun 2020 12:59:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F23320DD4 for ; Fri, 19 Jun 2020 12:59:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VCEh6Zra" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732696AbgFSM6j (ORCPT ); Fri, 19 Jun 2020 08:58:39 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:51696 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732677AbgFSM6g (ORCPT ); Fri, 19 Jun 2020 08:58:36 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwRex082673; Fri, 19 Jun 2020 07:58:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571507; bh=gGgeNDrwJZDmhTBHIA/rEns/YYGEnKJCgBn0VXHZTQg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VCEh6ZraffXfp5+42J0kt9MPgGJyWtMrXIQr6UBcA4kXsJy/r1QMxUoq/04fBOgoS aBEYk65lorUnsMSG8M+Upns3K3IewUPkFw8OM//PUUB0H0RqJcNGYi44y+4qLe+NiN gzc9e2cJXeeVwVfI2wGRJW+kRLEx6OPIBTiVwS7w= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JCwRbB105835 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 07:58:27 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:27 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:26 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hp015675; Fri, 19 Jun 2020 07:58:23 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 5/7] mmc: sdhci_am654: Update delay chain configuration Date: Fri, 19 Jun 2020 18:27:59 +0530 Message-ID: <20200619125801.9530-6-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org For speed modes where DLL is not enabled write to TXDLYCLK to enable transmitter delay chain mode. Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8b0f69012d09..f7535ee3a232 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -61,6 +61,8 @@ #define CALDONE_MASK BIT(CALDONE_SHIFT) #define RETRIM_SHIFT 17 #define RETRIM_MASK BIT(RETRIM_SHIFT) +#define SELDLYTXCLK_SHIFT 17 +#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) #define DRIVER_STRENGTH_50_OHM 0x0 #define DRIVER_STRENGTH_33_OHM 0x1 @@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) + if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) { + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, + SELDLYTXCLK_MASK, 0); sdhci_am654_setup_dll(host, clock); + } else { + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, + SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); + } } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, From patchwork Fri Jun 19 12:58:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614117 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8915B14B7 for ; Fri, 19 Jun 2020 12:59:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70591208C7 for ; Fri, 19 Jun 2020 12:59:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="u0X/Sjdy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732785AbgFSM66 (ORCPT ); Fri, 19 Jun 2020 08:58:58 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:35048 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732690AbgFSM6j (ORCPT ); Fri, 19 Jun 2020 08:58:39 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwVfe076871; Fri, 19 Jun 2020 07:58:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571511; bh=aJnKA0kudzVvE8QWCNmxRFasKDl7kSmbWoXmdq3ovjY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=u0X/SjdyEzBsGZpN3q+7L6C5HO6Kzh0yj1ImbJGdQrMXTj5m912uYchbK+7mQ69o0 pTmLJLwBdqnYQwzJ5yqeeROZKYZyOjbKeL3bbQf4vAMs2kHgKbAJGZ9A1ERhR4cfIK 5RzeUEJzr/IVremsfEDg3uB2pZBC8rj0991a2Yyk= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JCwVGB105882 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 07:58:31 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:31 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:31 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hq015675; Fri, 19 Jun 2020 07:58:27 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 6/7] mmc: sdhci_am654: Add support for clkbuf_sel property Date: Fri, 19 Jun 2020 18:28:00 +0530 Message-ID: <20200619125801.9530-7-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support for writing new clkbuf_sel property for the J721e 4 bit IP. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori --- drivers/mmc/host/sdhci_am654.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index f7535ee3a232..f9d24af12396 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -47,6 +47,8 @@ #define SEL100_MASK BIT(SEL100_SHIFT) #define FREQSEL_SHIFT 8 #define FREQSEL_MASK GENMASK(10, 8) +#define CLKBUFSEL_SHIFT 0 +#define CLKBUFSEL_MASK GENMASK(2, 0) #define DLL_TRIM_ICP_SHIFT 4 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) #define DR_TY_SHIFT 20 @@ -86,6 +88,7 @@ struct sdhci_am654_data { struct regmap *base; bool legacy_otapdly; int otap_del_sel[11]; + int clkbuf_sel; int trm_icp; int drv_strength; bool dll_on; @@ -238,6 +241,9 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); } + + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, + sdhci_am654->clkbuf_sel); } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, @@ -260,6 +266,9 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, (otap_del_sel << OTAPDLYSEL_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, + sdhci_am654->clkbuf_sel); + sdhci_set_clock(host, clock); } @@ -582,6 +591,8 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev, } device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); + device_property_read_u32(dev, "ti,clkbuf-sel", + &sdhci_am654->clkbuf_sel); sdhci_get_of_property(pdev); From patchwork Fri Jun 19 12:58:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 11614113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5142890 for ; Fri, 19 Jun 2020 12:58:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A35E20DD4 for ; Fri, 19 Jun 2020 12:58:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="H7zJqw4J" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732742AbgFSM6q (ORCPT ); Fri, 19 Jun 2020 08:58:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55424 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732660AbgFSM6n (ORCPT ); Fri, 19 Jun 2020 08:58:43 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 05JCwZSv058358; Fri, 19 Jun 2020 07:58:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1592571515; bh=VgzXtbEPK3BZf4YNOTbshjleKAPVz3hmnBNiNTgI/zo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=H7zJqw4J394jESjLoLpCTIRcxQ3THnu16UGGA0JLjWpKvYH6W2FJh49k8LBlgF4yC Jbujo8GyR9XPxL5FSTrtz5W1ng/UW2fuZ/dSZHVvt8VBLKfvxlXHSIWnHJk1K6GH9K 0dw8poqah9BCNbsk6JtFNvGZMDqc0vlmdjn8DJxc= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 05JCwZ8b081271 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 19 Jun 2020 07:58:35 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 19 Jun 2020 07:58:35 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 19 Jun 2020 07:58:35 -0500 Received: from a0230074-Latitude-E7470.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 05JCw2Hr015675; Fri, 19 Jun 2020 07:58:31 -0500 From: Faiz Abbas To: , , , , , , , , CC: Subject: [PATCH 7/7] arm64: defconfig: Enable AM654x SDHCI controller Date: Fri, 19 Jun 2020 18:28:01 +0530 Message-ID: <20200619125801.9530-8-faiz_abbas@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200619125801.9530-1-faiz_abbas@ti.com> References: <20200619125801.9530-1-faiz_abbas@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Enable CONFIG_SDHCI_AM654 to Support AM65x sdhci controller. Signed-off-by: Faiz Abbas --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8bace3ed..40dd13e0adc5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -731,6 +731,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SUNXI=y CONFIG_MMC_BCM2835=y CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y