From patchwork Fri Jun 19 21:11:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Modem, Bhanuprakash" X-Patchwork-Id: 11614195 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 816A4618 for ; Fri, 19 Jun 2020 13:15:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 69489208C7 for ; Fri, 19 Jun 2020 13:15:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 69489208C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9718C6EC57; Fri, 19 Jun 2020 13:14:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 559B26EC57; Fri, 19 Jun 2020 13:14:57 +0000 (UTC) IronPort-SDR: Hxw/y9Oj8nntXmOpErirPbIfEgmuljBVl3umCpKjHuiCuB+GhO161FDXlhcrJ2pJDvuggWrKQ+ s0V0dXAB8e/w== X-IronPort-AV: E=McAfee;i="6000,8403,9656"; a="130318721" X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="130318721" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2020 06:14:57 -0700 IronPort-SDR: iFbi5Xm2l6q8il58HIgBAxV4YFfYMsUYHjW2THcw7/SqGbyErRfizZl0kCqGkkkYe4jZGPb23i DAjkKdD2RhlA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,255,1589266800"; d="scan'208";a="277995705" Received: from bhanu-nuc8i7beh.iind.intel.com ([10.145.162.210]) by orsmga006.jf.intel.com with ESMTP; 19 Jun 2020 06:14:55 -0700 From: Bhanuprakash Modem To: bhanuprakash.modem@intel.com, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Sat, 20 Jun 2020 02:41:04 +0530 Message-Id: <20200619211106.19207-2-bhanuprakash.modem@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200612230444.10121-1-manasi.d.navare@intel.com> References: <20200612230444.10121-1-manasi.d.navare@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [v6 1/3] drm/dp: DRM DP helper for reading Ignore MSA from DPCD X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Manasi Navare DP sink device sets the Ignore MSA bit in its DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to ignore the MSA video timing parameters and its ability to support seamless video timing change over a range of timing exposed by DisplayID and EDID. This is required for the sink to indicate that it is Adaptive sync capable. v3: * Fi the typo in commit message (Manasi) v2: * Rename to describe what the function does (Jani Nikula) Cc: Jani Nikula Cc: Ville Syrjälä Cc: Harry Wentland Cc: Nicholas Kazlauskas Signed-off-by: Manasi Navare Reviewed-by: Harry Wentland --- include/drm/drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1165ec105638..e47dc22ebf50 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1457,6 +1457,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) DP_ALTERNATE_SCRAMBLER_RESET_CAP; } +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + /* * DisplayPort AUX channel */