From patchwork Sun Jun 21 21:37:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616773 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0006D912 for ; Sun, 21 Jun 2020 21:38:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DCDB82529D for ; Sun, 21 Jun 2020 21:38:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZfRvOks8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730782AbgFUVic (ORCPT ); Sun, 21 Jun 2020 17:38:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725985AbgFUVib (ORCPT ); Sun, 21 Jun 2020 17:38:31 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B89AC061794; Sun, 21 Jun 2020 14:38:30 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id dp18so15988291ejc.8; Sun, 21 Jun 2020 14:38:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vOaD65bKJPMimt94w6Iz9NW+9a5Iv3mlmDas8EqB+QU=; b=ZfRvOks8x4eZKFmfE5Tv5fnxiJyIVChgDMdjNtBw12PjfWwrFldU8WqcrGpDwf+/WL hfKvZ7u9Xq8/pA5lCLtCqR6hXy9YlrBhOyDyOu3O5EIYJkjpGsdJT6o4r7Wo4tdb+uYZ Z3NgGjV7qrxHLoiaxg4rO7R0s4XPFr4mh5uztKCQiac2ngKnfVMkdDwMig8ROS9tU5mY Nm3kROG6j4afGYwIYjBmM8+b/RW7y2Vya1e7WtCpm7sNlpOwGhEdjW0urESHGmqJyTyt SropEABhi92hQescEeipy6QdeJ6n9qNViix04s0BNxsqcyi3g7THxe5OWaOZ9+Svp1lT Bviw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vOaD65bKJPMimt94w6Iz9NW+9a5Iv3mlmDas8EqB+QU=; b=LxK2pEOr44AzV1JEZIfCt8ArRpllgLxlW9HEWAibwcH8IgpVece0jJrSvBSg0BbGkF 3CP+Sj1JmfN+Bwsi2AzDk1HAyeySrnQW6Pinv/gM/dQ5X9awO915sQmOnjRCONMM/TNd ypbh0ea4uzU2xutSaFKbYLp89FTLclRkqXrAD3ODALs6HL0CbRB1x3rbo3BkQ929DZb+ SGvDtptSYcZV0MX+k9VxwT7sJ8VOOAgFBIUmaOti2PcojspEAi0QzV0lHTTDyDHOUYWk Qywvs6ZDd87kYX4lqdUr9My82Eusn627z2KEkhwLRAtoe4KQjMTxTEU0/klI9LiiRZ/L PcjA== X-Gm-Message-State: AOAM530dlkYtF2iq9NpO8J49g8e5LspGYDQvGZqHNZ9N8GIsjyLQ62hN TL9eTEjg2m/sbnvxu6ZOBew= X-Google-Smtp-Source: ABdhPJz/nnnl5zmqsFoq4flJnMi5EIIlb4LFRwTyHnFT3p6gshsTe31aCKAx09uZGFUoGUTAL9JkCA== X-Received: by 2002:a17:906:73db:: with SMTP id n27mr12915388ejl.16.1592775508804; Sun, 21 Jun 2020 14:38:28 -0700 (PDT) Received: from localhost.localdomain (abag196.neoplus.adsl.tpnet.pl. [83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:28 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 1/8] pinctrl: qcom: spmi-gpio: Add pm660(l) compatibility Date: Sun, 21 Jun 2020 23:37:57 +0200 Message-Id: <20200621213806.551879-2-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add support for pm660(l) SPMI GPIOs. The PMICs feature 13 and 12 GPIOs respectively, though with a lot of holes inbetween. Signed-off-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index fe0be8a6ebb7..95ca66e24e7c 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1118,6 +1118,10 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, + /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */ + { .compatible = "qcom,pm660-gpio", .data = (void *) 13 }, + /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */ + { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 }, /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ From patchwork Sun Jun 21 21:37:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616801 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 94574912 for ; Sun, 21 Jun 2020 21:39:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7CD74252AD for ; Sun, 21 Jun 2020 21:39:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="rNfu7qiK" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730821AbgFUVih (ORCPT ); Sun, 21 Jun 2020 17:38:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725985AbgFUVie (ORCPT ); Sun, 21 Jun 2020 17:38:34 -0400 Received: from mail-ej1-x641.google.com (mail-ej1-x641.google.com [IPv6:2a00:1450:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64DE3C061794; Sun, 21 Jun 2020 14:38:33 -0700 (PDT) Received: by mail-ej1-x641.google.com with SMTP id k11so15982853ejr.9; Sun, 21 Jun 2020 14:38:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uFrjNrpCN3ztWJ49/VIXZ9CeZ4er+je0BNmpNUdRSbU=; b=rNfu7qiKTJJSH0ANM2WHzbxQWPd5FdX/xJ6Y86oxTEGkKLzHdN86vJwXKgpoIuvMgI cS/dBT+kF7VJWZanMRL/DhnDiLUc92Rs8nPH0/3zIZ4cv9GitDs3qrb0f4ZujXTzD0MZ 9GbthKrt9yXUwrgepFH46to6y7HkjM3rMU3JNwych9184N3YFoOztIx+6+bM/uXoy714 0UfpHSGuF0u6HagF6Pha/uQSPfqFXMSJaE0cEe8jU0ouOU6ilH+wbVjT33JpntieLCPd F1jhHmfEqOXSfx4qYrrRJ0EFuuR4vyCDASk4NfnJbBFiUcL2pfsPMd38fbxIesZrewqE NL3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uFrjNrpCN3ztWJ49/VIXZ9CeZ4er+je0BNmpNUdRSbU=; b=ZRfAEFElQ0RTUwXIUNOmxqaWqsyDqiyXZQemllgkvpoJCGxy0aa5YNx78nYZj4x8ZL 3M44o4W4Y0o88CW6tUf5/9f4eossSpfvtEf5DGSGOohLD/oqQuVBnqdGAQv9I6uDRmvV EyTABDQuei9idtyEq4p4IIbRHn8FAVjNwkMSpcNcb/xnKUxEoHqKUewsL9P1QXecChKI b+EoeSROMFRhHA/mcVAlDEhnSJIcaFGyaxz2z+P6LQJW+l/qC9HQhAkiFKe3jedZAFpc vk2djFjxwASSxPerTj8TTa4u4tehlR1gUrgJKGScv3s1gnfUu9c+oSfInTOEPD6FXJb2 XRkg== X-Gm-Message-State: AOAM531wtT5j5/C9yp63r21bkMXg/WWMLdVtcSXdKS9kiTyMoPEuOC1k e1PYHFsGFg2W/fZlafE05OY= X-Google-Smtp-Source: ABdhPJzhbtgPKBwQP3mdVsb8YNWW9GjVLl+AoA8Q5+r/UfaMFeD4kHOmdaI5odtS1yW+9FlhQKZTPw== X-Received: by 2002:a17:906:b292:: with SMTP id q18mr9241459ejz.253.1592775512176; Sun, 21 Jun 2020 14:38:32 -0700 (PDT) Received: from localhost.localdomain (abag196.neoplus.adsl.tpnet.pl. [83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:31 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 2/8] Documentation: Document pm660(l) SPMI GPIOs compatible Date: Sun, 21 Jun 2020 23:37:58 +0200 Message-Id: <20200621213806.551879-3-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 7be5de8d253f..f8a5651d498a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -23,6 +23,8 @@ PMIC's from Qualcomm. "qcom,pmi8994-gpio" "qcom,pmi8998-gpio" "qcom,pms405-gpio" + "qcom,pm660-gpio" + "qcom-pm660l-gpio" "qcom,pm8150-gpio" "qcom,pm8150b-gpio" "qcom,pm6150-gpio" From patchwork Sun Jun 21 21:37:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616797 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F2F0138C for ; Sun, 21 Jun 2020 21:39:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 160AA252BC for ; Sun, 21 Jun 2020 21:39:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Nyj911si" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730836AbgFUVii (ORCPT ); Sun, 21 Jun 2020 17:38:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730811AbgFUVih (ORCPT ); Sun, 21 Jun 2020 17:38:37 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA7D7C061795; Sun, 21 Jun 2020 14:38:36 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id e22so1393379edq.8; Sun, 21 Jun 2020 14:38:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nzouIcqNeHmwTME7jVaUjFBAtS8z2sOjc/dsKSoeppE=; b=Nyj911siu9dLwcURrkAGn8AqGDBMLdun4vj2BO/+KSR92oT2+Hjb+qpgcV5QiyPP1q DknOejgADOjn8caVmy43xurt9daEIASfezTqBfvJv3JbJpAD00ynFHLIZ+RKfsi2ne6Q WsTsSJI6BCJZGVrOyWT6Lxp1PTq8kN93os0moLZPhh9sbSg7ig5IAPzwRCsykKm/QYu6 LMKax/+FnHxRsYU2MPrL2SzUZGWt9NIHYmYFmyobP2NJ05GD38b+2eBDh51Skk4nZwGt tfvNuIzzts9MjbXV8hym12GmOQifY5mtROndR8E5oHKjBoiLBTpKVMzGPuXigb7CmCvz pejg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nzouIcqNeHmwTME7jVaUjFBAtS8z2sOjc/dsKSoeppE=; b=Zm9lW/mWDSwrRsnsCK88t5+q3yGZlK5qxSYHACtYaJZxRXaYdfRwM8VLtGt0Cd+Fr6 Kof1Onh7UWmWBn5fg/5uiteBFF2/YLtMooi6NozeNKS5Dh2BLxTdlFKTfTHwPBLlUPPL 3vPSSE6r+MZ/m27zzLZ7FpoVZL9r9lFpmf3DkK+YSYYcj3VWOdoOVjHwetESm6O/Ba9f PsCDUmo6WdIOcyRylnI6TVfFyP6b4m6VmgwajHKqhR5hw5UkbZWHtYDPi6PCIDVRqcy+ S+wss2Gbcncp4Hn45lb0mwpE39RVfgg1GRa4zWEUXI1OJ955/Od5SU1xT3RegY3VXlJu 89dg== X-Gm-Message-State: AOAM533oC/xMHg/njmJ5QKxJavVz9g6rsMUENjYrtQwOs0mCSxo5U5ag lMC9w2oOAWtOMp4mAViCDeY= X-Google-Smtp-Source: ABdhPJzYlHqpU5x74Vh8tehIGsqfJ9Wl0CPmHi1JaJTn0+q8U/bOPRdCkausY0w6VsejRnLMi+qWNA== X-Received: by 2002:a05:6402:206e:: with SMTP id bd14mr14246042edb.105.1592775515544; Sun, 21 Jun 2020 14:38:35 -0700 (PDT) Received: from localhost.localdomain (abag196.neoplus.adsl.tpnet.pl. [83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:35 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 3/8] soc: qcom: socinfo: Add socinfo entry for SDM630 Date: Sun, 21 Jun 2020 23:37:59 +0200 Message-Id: <20200621213806.551879-4-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This patch adds missing soc ID for SDM630. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 5983c6ffb078..705f142ee588 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -202,6 +202,7 @@ static const struct soc_id soc_id[] = { { 310, "MSM8996AU" }, { 311, "APQ8096AU" }, { 312, "APQ8096SG" }, + { 318, "SDM630" }, { 321, "SDM845" }, { 341, "SDA845" }, }; From patchwork Sun Jun 21 21:38:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616795 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A05913B1 for ; Sun, 21 Jun 2020 21:39:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F574252BF for ; Sun, 21 Jun 2020 21:39:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S9shq/p+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730848AbgFUVim (ORCPT ); Sun, 21 Jun 2020 17:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730811AbgFUVik (ORCPT ); Sun, 21 Jun 2020 17:38:40 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69E9FC061794; Sun, 21 Jun 2020 14:38:40 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id e22so1393460edq.8; Sun, 21 Jun 2020 14:38:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BTo8uc0DYv2Bq0tjWRFArUn+9wBNnrYsgKoGspnCgNA=; b=S9shq/p+tHa5o1hO8iRarQLe2oLh8FyBZztLApJJmpGI6ER+i+KUODYkT6EdRLu+lN R4zi4jx7wDojWGuM/0zQvPF4mM+7CfbsVXNhQSnYFAJ9wjlKr7WxTfj1zgxRwZ3jpSG7 4VGoAYblmFG9wp+22281lZ87HGajjcX6sj/wedhCfCpOCDWmfomRL890KxHaeAB1qTbe THW/RpAKEnwZPqcQE26Nfiar61uCKZ1HkLsXcYefO+LAi+MrFnVC9WGIFIh2Cz/PiqRG wnDYExPgSSQaKngJ/Rau00ZN+Y81xFdRtsFyROXDGemhqdkraU9Guo07Lwl7EGv2+Afp D8lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BTo8uc0DYv2Bq0tjWRFArUn+9wBNnrYsgKoGspnCgNA=; b=KO5z8IJx/oH/pXMtpUgmDB7swOpZTeYbD5rqcBP/Lu+AGZFFeZNPYW95HdEWvQjhJ9 n8AjE6B4UtZ14Fpf4ePa8bhSAeWkJlxh5ZWS7lwPuPeifsKwqQ5sYJLdhP2Kth5e/izS bTedRE6iIemsOItimE1MZghCpKC3HmZlyHrB/CoSojRQZTDWSwBoAlcAghCVALBHJbkk 0N/T41gj2qVVV2XCPDdand/M/ogrTuiOxqUjYPN8Bno0RSTPAkyLrbkJmkH0LDrfENDk MFJm+yIH7rxSK93qWjb6aNo0o/ygjDW5WAuDMhwoEcYX/ToNcnIlGHYrG7f9iOQcscYV SzLg== X-Gm-Message-State: AOAM530hFkdq/mofOOi7z7taDW1XCBJrJQ/c0lcLwRU3CF1x18c0Aou2 sRRsuYjKsJU3DXYPYQtr5ng= X-Google-Smtp-Source: ABdhPJwIG9iG6gsPSxcc/ifYLuxxl5RA0b9FTHomz/VLJQuyoqsxHbs9+77gXN1cGD1Qh+ymbzNSCw== X-Received: by 2002:aa7:c714:: with SMTP id i20mr9048213edq.215.1592775519157; Sun, 21 Jun 2020 14:38:39 -0700 (PDT) Received: from localhost.localdomain (abag196.neoplus.adsl.tpnet.pl. [83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:38 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 4/8] clk: qcom: smd: Add support for SDM660 rpm clocks Date: Sun, 21 Jun 2020 23:38:00 +0200 Message-Id: <20200621213806.551879-5-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add rpm smd clocks, PMIC and bus clocks which are required on SDM630/660 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio Tested-by: Alexey Minnekhanov --- .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 + drivers/clk/qcom/clk-smd-rpm.c | 77 +++++++++++++++++++ include/dt-bindings/clock/qcom,rpmcc.h | 10 +++ 3 files changed, 88 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index 90a1349bc713..2ced7807d574 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -20,6 +20,7 @@ Required properties : "qcom,rpmcc-msm8996", "qcom,rpmcc" "qcom,rpmcc-msm8998", "qcom,rpmcc" "qcom,rpmcc-qcs404", "qcom,rpmcc" + "qcom,rpmcc-sdm660", "qcom,rpmcc" - #clock-cells : shall contain 1 diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 52f63ad787ba..2f1881d8bd48 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -766,15 +766,92 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { .num_clks = ARRAY_SIZE(msm8998_clks), }; +/* sdm660 */ +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, + 19200000); +DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, + QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, + QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, + QCOM_SMD_RPM_AGGR_CLK, 2); +DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, + QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, + ln_bb_clk1_pin_a, 1); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, + ln_bb_clk2_pin_a, 2); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, + ln_bb_clk3_pin_a, 3); +static struct clk_smd_rpm *sdm660_clks[] = { + [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk, + [RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk, + [RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk, + [RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk, + [RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk, + [RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk, + [RPM_SMD_IPA_CLK] = &sdm660_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &sdm660_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &sdm660_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a, + [RPM_SMD_DIV_CLK1] = &sdm660_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a, + [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a, + [RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a, + [RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a, + [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin, + [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a, +}; + +static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { + .clks = sdm660_clks, + .num_clks = ARRAY_SIZE(sdm660_clks), +}; + static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 }, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 }, { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 }, + { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 }, { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 }, { } }; + MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index ae74c43c485d..d1afa634b58d 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -133,5 +133,15 @@ #define RPM_SMD_RF_CLK3_A 87 #define RPM_SMD_RF_CLK3_PIN 88 #define RPM_SMD_RF_CLK3_A_PIN 89 +#define RPM_SMD_MMSSNOC_AXI_CLK 90 +#define RPM_SMD_MMSSNOC_AXI_CLK_A 91 +#define RPM_SMD_CNOC_PERIPH_CLK 92 +#define RPM_SMD_CNOC_PERIPH_A_CLK 93 +#define RPM_SMD_LN_BB_CLK3 94 +#define RPM_SMD_LN_BB_CLK3_A 95 +#define RPM_SMD_LN_BB_CLK1_PIN 96 +#define RPM_SMD_LN_BB_CLK1_A_PIN 97 +#define RPM_SMD_LN_BB_CLK2_PIN 98 +#define RPM_SMD_LN_BB_CLK2_A_PIN 99 #endif From patchwork Sun Jun 21 21:38:01 2020 Content-Type: text/plain; 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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:42 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 5/8] arm64: dts: qcom: pm660(l): Add base dts files Date: Sun, 21 Jun 2020 23:38:01 +0200 Message-Id: <20200621213806.551879-6-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add base DTS files for pm660(l) along with GPIOs, power-on and rtc nodes. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm660.dtsi | 60 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/pm660l.dtsi | 45 +++++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm660.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm660l.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi new file mode 100644 index 000000000000..94eca5a1cf0b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +#include +#include +#include + +&spmi_bus { + + pmic@0 { + compatible = "qcom,pm660", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pon: pon@800 { + compatible = "qcom,pm8916-pon"; + + reg = <0x800>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + + }; + + pm660_gpios: gpios@c000 { + compatible = "qcom,pm660-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, + <0 0xc1 0 IRQ_TYPE_NONE>, + <0 0xc2 0 IRQ_TYPE_NONE>, + <0 0xc3 0 IRQ_TYPE_NONE>, + <0 0xc4 0 IRQ_TYPE_NONE>, + <0 0xc5 0 IRQ_TYPE_NONE>, + <0 0xc6 0 IRQ_TYPE_NONE>, + <0 0xc7 0 IRQ_TYPE_NONE>, + <0 0xc8 0 IRQ_TYPE_NONE>, + <0 0xc9 0 IRQ_TYPE_NONE>, + <0 0xca 0 IRQ_TYPE_NONE>, + <0 0xcb 0 IRQ_TYPE_NONE>, + <0 0xcc 0 IRQ_TYPE_NONE>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi new file mode 100644 index 000000000000..6de56b220c56 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +#include +#include +#include + +&spmi_bus { + + pmic@2 { + compatible = "qcom,pm660l", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm660l_gpios: gpios@c000 { + compatible = "qcom,pm660l-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>, + <0x2 0xc1 0x0 IRQ_TYPE_NONE>, + <0x2 0xc2 0x0 IRQ_TYPE_NONE>, + <0x2 0xc3 0x0 IRQ_TYPE_NONE>, + <0x2 0xc4 0x0 IRQ_TYPE_NONE>, + <0x2 0xc5 0x0 IRQ_TYPE_NONE>, + <0x2 0xc6 0x0 IRQ_TYPE_NONE>, + <0x2 0xc7 0x0 IRQ_TYPE_NONE>, + <0x2 0xc8 0x0 IRQ_TYPE_NONE>, + <0x2 0xc9 0x0 IRQ_TYPE_NONE>, + <0x2 0xca 0x0 IRQ_TYPE_NONE>, + <0x2 0xcb 0x0 IRQ_TYPE_NONE>; + }; + }; + + pmic@3 { + compatible = "qcom,pm660l", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; \ No newline at end of file From patchwork Sun Jun 21 21:38:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616777 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 618C4138C for ; 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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:46 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 6/8] arm64: dts: qcom: sdm630: Add sdm630 dts file Date: Sun, 21 Jun 2020 23:38:02 +0200 Message-Id: <20200621213806.551879-7-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add devicetree files for SDM630 SoC and its pin configuration. This commit adds basic nodes like cpu, psci and other required configuration for booting up from eMMC to the serial console. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm630-pins.dtsi | 268 ++++++ arch/arm64/boot/dts/qcom/sdm630.dtsi | 991 ++++++++++++++++++++++ 2 files changed, 1259 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm630-pins.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sdm630.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm630-pins.dtsi b/arch/arm64/boot/dts/qcom/sdm630-pins.dtsi new file mode 100644 index 000000000000..55d80458f447 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-pins.dtsi @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + + &tlmm { + blsp1_uart1_default: blsp1_uart1_default { + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + config { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2_default: blsp1_uart2_default { + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_tx_active: blsp2_uart1_tx_active { + config { + pins = "gpio16"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_tx_sleep: blsp2_uart1_tx_sleep { + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp2_uart1_rxcts_active: blsp2_uart1_rxcts_active { + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_rxcts_sleep: blsp2_uart1_rxcts_sleep { + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + blsp2_uart1_rfr_active: blsp2_uart1_rfr_active { + config { + pins = "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp2_uart1_rfr_sleep: blsp2_uart1_rfr_sleep { + config { + pins = "gpio19"; + drive-strength = <2>; + bias-no-pull; + }; + }; + + i2c1_default: i2c1_default { + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c1_sleep: i2c1_sleep { + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c2_sleep: i2c2_sleep { + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c3_default: i2c3_default { + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c3_sleep: i2c3_sleep { + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c4_default: i2c4_default { + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c4_sleep: i2c4_sleep { + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c5_default: i2c5_default { + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c5_sleep: i2c5_sleep { + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c6_default: i2c6_default { + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c6_sleep: i2c6_sleep { + config { + pins = "gpio22", "gpio23"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c7_default: i2c7_default { + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c7_sleep: i2c7_sleep { + config { + pins = "gpio26", "gpio27"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c8_default: i2c8_default { + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c8_sleep: i2c8_sleep { + config { + pins = "gpio30", "gpio31"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <8>; + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi new file mode 100644 index 000000000000..4d714b52e3ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -0,0 +1,991 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +#include +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SDM630"; + compatible = "qcom,sdm630"; + + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + wlan_msa_guard: wlan_msa_guard@85600000 { + reg = <0x0 0x85600000 0x0 0x100000>; + no-map; + }; + + wlan_msa_mem: wlan_msa_mem@85700000 { + reg = <0x0 0x85700000 0x0 0x100000>; + no-map; + }; + + qhee_code: qhee_code@85800000 { + reg = <0x0 0x85800000 0x0 0x3700000>; + no-map; + }; + + smem_region: smem-mem@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + tz_mem: memory@86200000 { + reg = <0x0 0x86200000 0x0 0x3300000>; + no-map; + }; + + modem_fw_mem: modem_fw_region@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0x7e00000>; + no-map; + }; + + adsp_fw_mem: adsp_fw_region@92a00000 { + reg = <0x0 0x92a00000 0x0 0x1e00000>; + no-map; + }; + + pil_mba_mem: pil_mba_region@94800000 { + reg = <0x0 0x94800000 0x0 0x200000>; + no-map; + }; + + buffer_mem: buffer_region@94a00000 { + reg = <0x0 0x94a00000 0x0 0x100000>; + no-map; + }; + + venus_fw_mem: venus_fw_region@9f800000 { + reg = <0x0 0x9f800000 0x0 0x800000>; + no-map; + }; + + secure_region2: secure_region2@f7c00000 { + reg = <0x0 0xf7c00000 0x0 0x5c00000>; + no-map; + }; + + adsp_mem: adsp_region@f6000000 { + reg = <0x0 0xf6000000 0x0 0x800000>; + no-map; + }; + + qseecom_ta_mem: qseecom_ta_region@fec00000 { + reg = <0x0 0xfec00000 0x0 0x1000000>; + no-map; + }; + + qseecom_mem: qseecom_region@f6800000 { + reg = <0x0 0xf6800000 0x0 0x1400000>; + no-map; + }; + + secure_display_memory: secure_region@f5c00000 { + reg = <0x0 0xf5c00000 0x0 0x5c00000>; + no-map; + }; + + cont_splash_mem: cont_splash_region@9d400000 { + reg = <0x0 0x9d400000 0x0 0x23ff000>; + no-map; + }; + }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&PERF_CPU_SLEEP_0 + &PERF_CPU_SLEEP_1 + &PERF_CLUSTER_SLEEP_0 + &PERF_CLUSTER_SLEEP_1 + &PERF_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1126>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&PERF_CPU_SLEEP_0 + &PERF_CPU_SLEEP_1 + &PERF_CLUSTER_SLEEP_0 + &PERF_CLUSTER_SLEEP_1 + &PERF_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1126>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&PERF_CPU_SLEEP_0 + &PERF_CPU_SLEEP_1 + &PERF_CLUSTER_SLEEP_0 + &PERF_CLUSTER_SLEEP_1 + &PERF_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1126>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&PERF_CPU_SLEEP_0 + &PERF_CPU_SLEEP_1 + &PERF_CLUSTER_SLEEP_0 + &PERF_CLUSTER_SLEEP_1 + &PERF_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1126>; + #cooling-cells = <2>; + next-level-cache = <&L2_1>; + }; + + CPU4: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&PWR_CPU_SLEEP_0 + &PWR_CPU_SLEEP_1 + &PWR_CLUSTER_SLEEP_0 + &PWR_CLUSTER_SLEEP_1 + &PWR_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU5: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&PWR_CPU_SLEEP_0 + &PWR_CPU_SLEEP_1 + &PWR_CLUSTER_SLEEP_0 + &PWR_CLUSTER_SLEEP_1 + &PWR_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + }; + + CPU6: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&PWR_CPU_SLEEP_0 + &PWR_CPU_SLEEP_1 + &PWR_CLUSTER_SLEEP_0 + &PWR_CLUSTER_SLEEP_1 + &PWR_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + }; + + CPU7: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&PWR_CPU_SLEEP_0 + &PWR_CPU_SLEEP_1 + &PWR_CLUSTER_SLEEP_0 + &PWR_CLUSTER_SLEEP_1 + &PWR_CLUSTER_SLEEP_2>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + PWR_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "pwr-retention"; + arm,psci-suspend-param = <0x40000002>; + entry-latency-us = <338>; + exit-latency-us = <423>; + min-residency-us = <200>; + }; + + PWR_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "pwr-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <515>; + exit-latency-us = <1821>; + min-residency-us = <1000>; + local-timer-stop; + }; + + PERF_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "perf-retention"; + arm,psci-suspend-param = <0x40000002>; + entry-latency-us = <154>; + exit-latency-us = <87>; + min-residency-us = <200>; + }; + + PERF_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "perf-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <262>; + exit-latency-us = <301>; + min-residency-us = <1000>; + local-timer-stop; + }; + + PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "pwr-cluster-dynamic-retention"; + arm,psci-suspend-param = <0x400000F2>; + entry-latency-us = <284>; + exit-latency-us = <384>; + min-residency-us = <9987>; + local-timer-stop; + }; + + PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "pwr-cluster-retention"; + arm,psci-suspend-param = <0x400000F3>; + entry-latency-us = <338>; + exit-latency-us = <423>; + min-residency-us = <9987>; + local-timer-stop; + }; + + PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { + compatible = "arm,idle-state"; + idle-state-name = "pwr-cluster-retention"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <515>; + exit-latency-us = <1821>; + min-residency-us = <9987>; + local-timer-stop; + }; + + PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "perf-cluster-dynamic-retention"; + arm,psci-suspend-param = <0x400000F2>; + entry-latency-us = <272>; + exit-latency-us = <329>; + min-residency-us = <9987>; + local-timer-stop; + }; + + PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "perf-cluster-retention"; + arm,psci-suspend-param = <0x400000F3>; + entry-latency-us = <332>; + exit-latency-us = <368>; + min-residency-us = <9987>; + local-timer-stop; + }; + + PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { + compatible = "arm,idle-state"; + idle-state-name = "perf-cluster-retention"; + arm,psci-suspend-param = <0x400000F4>; + entry-latency-us = <545>; + exit-latency-us = <1609>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-msm8998", "qcom,scm"; + }; + }; + + tcsr_mutex: hwlock { + compatible = "qcom,tcsr-mutex"; + syscon = <&tcsr_mutex_block 0 0x1000>; + #hwlock-cells = <1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sdm660"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + }; + + smem: smem { + compatible = "qcom,smem"; + memory-region = <&smem_region>; + hwlocks = <&tcsr_mutex 3>; + }; + + tcsr_mutex_block: syscon@1f40000 { + compatible = "syscon"; + reg = <0 0x1f40000 0 0x20000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm630"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x100000 0x94000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, + <&sleep_clk>; + }; + + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0x793000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17b00000 0x100000>; /* GICR * 8 */ + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + + restart@10ac000 { + compatible = "qcom,pshold"; + reg = <0x10ac000 0x4>; + }; + + tcsr_mutex_regs: syscon@1f40000 { + compatible = "syscon"; + reg = <0x01f40000 0x20000>; + }; + + rpm_msg_ram: memory@778000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x778000 0x7000>; + }; + + qfprom: qfprom@780000 { + compatible = "qcom,qfprom"; + reg = <0x780000 0x621c>; + #address-cells = <1>; + #size-cells = <1>; + }; + + apcs_glb: mailbox@17911000 { + compatible = "qcom,msm8998-apcs-hmss-global"; + reg = <0x17911000 0x1000>; + + #mbox-cells = <1>; + }; + + tlmm: pinctrl@3000000 { + compatible = "qcom,sdm630-pinctrl"; + reg = <0x3000000 0xc00000>; + interrupts = ; + gpio-controller; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + spmi_bus: spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + clock-frequency = <19200000>; + + frame@17921000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + sdhc_1: sdhci@c0c4000 { + compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; + reg = <0xc0c4000 0x1000>, + <0xc0c5000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + bus-width = <8>; + non-removable; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + + status = "disabled"; + }; + + anoc2_smmu: iommu@16c0000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0x016c0000 0x40000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + lpass_smmu: iommu@5100000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0x5100000 0x40000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + mmss_smmu: iommu@cd00000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0xcd00000 0x40000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = + , + , + + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + kgsl_smmu: iommu@5040000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = + , + , + + , + , + , + , + , + , + , + ; + }; + + blsp1_dma: dma@c144000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0c144000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <18>; + qcom,num-ees = <4>; + }; + + blsp2_dma: dma@c184000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0xc184000 0x1f000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <18>; + qcom,num-ees = <4>; + }; + + blsp_i2c1: i2c@c175000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c175000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c2: i2c@c176000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c176000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c3: i2c@c177000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c177000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_default>; + pinctrl-1 = <&i2c3_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c4: i2c@c178000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c178000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_default>; + pinctrl-1 = <&i2c4_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c5: i2c@c1b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b5000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c6: i2c@c1b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b6000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_default>; + pinctrl-1 = <&i2c6_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c7: i2c@c1b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b7000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c7_default>; + pinctrl-1 = <&i2c7_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp_i2c8: i2c@c1b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x0c1b8000 0x600>; + interrupts = ; + + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + clock-frequency = <400000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c8_default>; + pinctrl-1 = <&i2c8_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + blsp1_uart1: serial@c16f000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc16f000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + status = "disabled"; + }; + + blsp1_uart2: serial@c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart2_default>; + status = "disabled"; + }; + + blsp2_uart1: serial@c1af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc1af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active + &blsp2_uart1_rfr_active>; + pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep + &blsp2_uart1_rfr_sleep>; + status = "disabled"; + }; + }; +}; + +#include "sdm630-pins.dtsi" From patchwork Sun Jun 21 21:38:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 11616781 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9660213B1 for ; Sun, 21 Jun 2020 21:38:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7E8BB252B6 for ; Sun, 21 Jun 2020 21:38:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PYGDtEvZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730861AbgFUViy (ORCPT ); Sun, 21 Jun 2020 17:38:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730887AbgFUViv (ORCPT ); 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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:49 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 7/8] arm64: dts: qcom: Add support for Sony Xperia XA2/Plus/Ultra (Nile platform) Date: Sun, 21 Jun 2020 23:38:03 +0200 Message-Id: <20200621213806.551879-8-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add device tree support for the Sony Xperia XA2, XA2 Plus and XA2 Ultra smartphones. They are all based on the Sony Nile platform (sdm630) and share a lot of common code. The differences are really minor, so a Nile-common DTSI has been created to reduce clutter. XA2 - Pioneer XA2 Plus - Voyager XA2 Ultra - Discovery The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../sdm630-sony-xperia-nile-discovery.dts | 13 ++ .../qcom/sdm630-sony-xperia-nile-pioneer.dts | 13 ++ .../qcom/sdm630-sony-xperia-nile-voyager.dts | 20 +++ .../dts/qcom/sdm630-sony-xperia-nile.dtsi | 136 ++++++++++++++++++ 5 files changed, 185 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0f2c33d611df..1cad7cb07574 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts new file mode 100644 index 000000000000..2d7f0ceca4aa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm630-sony-xperia-nile.dtsi" + +/ { + model = "SoMC Discovery-RoW"; + compatible = "sony,discovery-row", "qcom,sdm630", "qcom,sdm630-mtp"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts new file mode 100644 index 000000000000..45f794440d19 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm630-sony-xperia-nile.dtsi" + +/ { + model = "SoMC Pioneer-RoW"; + compatible = "sony,pioneer-row", "qcom,sdm630", "qcom,sdm630-mtp"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts new file mode 100644 index 000000000000..4c2b7fa9d0a4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm630-sony-xperia-nile.dtsi" + +/ { + model = "SoMC Voyager-RoW"; + compatible = "sony,voyager-row", "qcom,sdm630", "qcom,sdm630-mtp"; + + chosen { + framebuffer@9d400000 { + reg = <0 0x9d400000 0 (2160 * 1080 * 4)>; + height = <2160>; + }; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi new file mode 100644 index 000000000000..39f1cffe9853 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "sdm630.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" +#include +#include +#include + +/ { + /* required for bootloader to select correct board */ + qcom,msm-id = <318 0>; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00>; + + /* This part enables graphical output via bootloader-enabled display */ + chosen { + bootargs = "earlycon=tty0 console=tty0"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; + width = <1080>; + height = <1920>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + status= "okay"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + status = "okay"; + }; + + debug_region@ffb00000 { + reg = <0x00 0xffb00000 0x00 0x100000>; + no-map; + }; + + removed_region@85800000 { + reg = <0x00 0x85800000 0x00 0x3700000>; + no-map; + }; + }; + + soc { + gpio_keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + camera_focus { + label = "Camera Focus"; + gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "Camera Snapshot"; + gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + vol_down { + label = "Volume Down"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + sdhci@c0c4000 { + status = "okay"; + + /* SoMC Nile platform's eMMC doesn't support HS200 mode */ + /delete-property/ mmc-hs200-1_8v; + }; + + i2c@c175000 { + status = "okay"; + + /* Synaptics touchscreen */ + }; + + i2c@c176000 { + status = "okay"; + + /* SMB1351 charger */ + }; + + /* I2C3, 4, 5, 7 and 8 are disabled on this board. */ + + i2c@c1b6000 { + status = "okay"; + + /* NXP NFC */ + }; + + serial@c1af000 { + status = "okay"; + }; + }; + +}; \ No newline at end of file From patchwork Sun Jun 21 21:38:04 2020 Content-Type: text/plain; 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[83.6.170.196]) by smtp.googlemail.com with ESMTPSA id w3sm10130012ejn.87.2020.06.21.14.38.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2020 14:38:53 -0700 (PDT) From: Konrad Dybcio To: skrzynka@konradybcio.pl Cc: Konrad Dybcio , Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Linus Walleij , Kees Cook , Anton Vorontsov , Colin Cross , Tony Luck , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Martin Botka Subject: [PATCH 8/8] arm64: dts: qcom: Add support for Sony Xperia 10/10 Plus (Ganges platform) Date: Sun, 21 Jun 2020 23:38:04 +0200 Message-Id: <20200621213806.551879-9-konradybcio@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200621213806.551879-1-konradybcio@gmail.com> References: <20200621213806.551879-1-konradybcio@gmail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Martin Botka Add device tree support for the Sony Xperia 10 and 10 Plus smartphones. They are all based on the Sony Ganges platform (sdm630/636) and share a lot of common code. The differences are really minor, so a Ganges-common DTSI has been created to reduce clutter. 10 - Kirin 10 Plus - Mermaid This platform is based on SoMC Nile, but there are some major differences when it comes to pin configuration and panel setup (among others). The boards currently support: * Screen console * SDHCI * I2C * pstore log dump * GPIO keys * PSCI idle states Signed-off-by: Martin Botka Signed-off-by: Konrad Dybcio Tested-by: Martin Botka Tested-by: Martin Botka --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sdm630-sony-xperia-ganges-kirin.dts | 13 +++++++ .../dts/qcom/sdm630-sony-xperia-ganges.dtsi | 39 +++++++++++++++++++ .../sdm636-sony-xperia-ganges-mermaid.dts | 19 +++++++++ 4 files changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1cad7cb07574..c98bafe03a96 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,9 +16,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts new file mode 100644 index 000000000000..5326e019db20 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Martin Botka + */ + +/dts-v1/; + +#include "sdm630-sony-xperia-ganges.dtsi" + +/ { + model = "SoMC Kirin-RoW"; + compatible = "sony,kirin-row", "qcom,sdm630", "qcom,sdm630-mtp"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi new file mode 100644 index 000000000000..6c4c30e4cd9d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Martin Botka + */ + +/dts-v1/; + +/* Ganges is very similar to Nile, but +there are some differences that will need +to be addresed when more peripherals are +enabled upstream. Hence the separate DTSI. */ +#include "sdm630-sony-xperia-nile.dtsi" + +/ { + chosen { + framebuffer@9d400000 { + reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; + height = <2520>; + }; + }; + + soc { + + i2c@c175000 { + status = "okay"; + + /* Novatek touchscreen */ + }; + + /* Yes, this is intentional. + Ganges devices only use gpio-keys for + Volume Down, but currently there's an + issue with it that has to be resolved. + Until then, let's not make the kernel panic + */ + /delete-node/ gpio-keys; + }; + +}; diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts new file mode 100644 index 000000000000..97dce64d0185 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Martin Botka + */ + +/dts-v1/; + +/* Mermaid uses sdm636, but it's different ever so slightly +that we can ignore it for the time being. Sony also commonizes +the Ganges platform as a whole in downstream kernels. */ +#include "sdm630-sony-xperia-ganges.dtsi" + +/ { + model = "SoMC Mermaid-RoW"; + compatible = "sony,mermaid-row", "qcom,sdm636", "qcom,sdm636-mtp"; + + qcom,msm-id = <345 0>; + qcom,pmic-id = <0x1001b 0x101011a 0x00 0x00 0x1001b 0x201011a 0x00 0x00 0x1001b 0x102001a 0x00 0x00>; +};