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Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 1dbe4e8b38ac..5d5ad9db549b 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2016-2017 Andreas Färber */ +#include #include #include @@ -70,6 +71,12 @@ hosc: hosc { #clock-cells = <0>; }; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -169,6 +176,13 @@ uart6: serial@b012c000 { status = "disabled"; }; + cmu: clock-controller@b0160000 { + compatible = "actions,s500-cmu"; + reg = <0xb0160000 0x8000>; + clocks = <&hosc>, <&losc>; + #clock-cells = <1>; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Thu Jun 25 23:34:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627193 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EE6556C1 for ; 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Thu, 25 Jun 2020 16:34:27 -0700 (PDT) Received: from localhost.localdomain ([188.24.137.55]) by smtp.gmail.com with ESMTPSA id u2sm13699184edq.29.2020.06.25.16.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 16:34:26 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 02/10] arm: dts: owl-s500: Set UART clock refs from CMU Date: Fri, 26 Jun 2020 02:34:14 +0300 Message-Id: <7b861eee0a83ccc2ad3c17319e06a175dc6e856c.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:641 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Enable using Clock Management Unit clocks for every UART node of the Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5d5ad9db549b..ac3d04c75dd5 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -131,6 +131,7 @@ uart0: serial@b0120000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0120000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART0>; status = "disabled"; }; @@ -138,6 +139,7 @@ uart1: serial@b0122000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0122000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART1>; status = "disabled"; }; @@ -145,6 +147,7 @@ uart2: serial@b0124000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0124000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART2>; status = "disabled"; }; @@ -152,6 +155,7 @@ uart3: serial@b0126000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0126000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART3>; status = "disabled"; }; @@ -159,6 +163,7 @@ uart4: serial@b0128000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb0128000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART4>; status = "disabled"; }; @@ -166,6 +171,7 @@ uart5: serial@b012a000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012a000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART5>; status = "disabled"; }; @@ -173,6 +179,7 @@ uart6: serial@b012c000 { compatible = "actions,s500-uart", "actions,owl-uart"; reg = <0xb012c000 0x2000>; interrupts = ; + clocks = <&cmu CLK_UART6>; status = "disabled"; }; From patchwork Thu Jun 25 23:34:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627337 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C613D14F6 for ; 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Note the Actions Semi Owl SoC's DMA driver seems to be fully compatible with the Actions Semi S500 SoC, even though this is not explicitly mentioned in the source code. Hence, for the moment, enable the DMA controller node using the "actions,s900-dma" compatible string. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index ac3d04c75dd5..0f4fc5487dad 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -205,5 +205,19 @@ sps: power-controller@b01b0100 { reg = <0xb01b0100 0x100>; #power-domain-cells = <1>; }; + + dma: dma-controller@b0260000 { + compatible = "actions,s900-dma"; + reg = <0xb0260000 0xd00>; + interrupts = , + , + , + ; + #dma-cells = <1>; + dma-channels = <12>; + dma-requests = <46>; + clocks = <&cmu CLK_DMAC>; + power-domains = <&sps S500_PD_DMA>; + }; }; }; From patchwork Thu Jun 25 23:34:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627197 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CE80B6C1 for ; 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Thu, 25 Jun 2020 16:34:29 -0700 (PDT) Received: from localhost.localdomain ([188.24.137.55]) by smtp.gmail.com with ESMTPSA id u2sm13699184edq.29.2020.06.25.16.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 16:34:29 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 04/10] arm: dts: owl-s500: Add Reset Controller support Date: Fri, 26 Jun 2020 02:34:16 +0300 Message-Id: <9fac12b305c4b4b79cbc9ffa874b1614ffc10dae.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add reset controller property and bindings header for the Actions Semi S500 SoC DTS. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 0f4fc5487dad..0b7ba2926f0e 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { compatible = "actions,s500"; @@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 { reg = <0xb0160000 0x8000>; clocks = <&hosc>, <&losc>; #clock-cells = <1>; + #reset-cells = <1>; }; timer: timer@b0168000 { From patchwork Thu Jun 25 23:34:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627223 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A04D292A for ; Fri, 26 Jun 2020 11:20:59 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75043206A1 for ; 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Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 0b7ba2926f0e..3b625358d786 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -208,6 +209,25 @@ sps: power-controller@b01b0100 { #power-domain-cells = <1>; }; + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, /* GPIO */ + <0xb01b0040 0x10>, + <0xb01b0060 0x18>, + <0xb01b0080 0xc>; + clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , /* GPIOA */ + , /* GPIOB */ + , /* GPIOC */ + , /* GPIOD */ + ; /* GPIOE */ + }; + dma: dma-controller@b0260000 { compatible = "actions,s900-dma"; reg = <0xb0260000 0xd00>; From patchwork Thu Jun 25 23:34:18 2020 Content-Type: text/plain; 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Thu, 25 Jun 2020 16:34:31 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 06/10] arm: dts: owl-s500: Add MMC nodes Date: Fri, 26 Jun 2020 02:34:18 +0300 Message-Id: <2a08075ab09975cbd1c3cee73d425e8f8fef6598.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:42b listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add MMC controller nodes for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 3b625358d786..778775ac42f7 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -241,5 +241,38 @@ dma: dma-controller@b0260000 { clocks = <&cmu CLK_DMAC>; power-domains = <&sps S500_PD_DMA>; }; + + mmc0: mmc@b0230000 { + compatible = "actions,owl-mmc"; + reg = <0xb0230000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD0>; + resets = <&cmu RESET_SD0>; + dmas = <&dma 2>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc1: mmc@b0234000 { + compatible = "actions,owl-mmc"; + reg = <0xb0234000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD1>; + resets = <&cmu RESET_SD1>; + dmas = <&dma 3>; + dma-names = "mmc"; + status = "disabled"; + }; + + mmc2: mmc@b0238000 { + compatible = "actions,owl-mmc"; + reg = <0xb0238000 0x38>; + interrupts = ; + clocks = <&cmu CLK_SD2>; + resets = <&cmu RESET_SD2>; + dmas = <&dma 4>; + dma-names = "mmc"; + status = "disabled"; + }; }; }; From patchwork Thu Jun 25 23:34:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627117 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 263441392 for ; Fri, 26 Jun 2020 10:37:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F243F20775 for ; Fri, 26 Jun 2020 10:37:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="r5D29vmX"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="jCeAz2Zc"; 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Note the Actions Semi Owl SoC's I2C driver seems to be fully compatible with the Actions Semi S500 SoC, even though this is not explicitly mentioned in the source code. Hence, for the moment, enable the I2C controller node via the "actions,s900-i2c" compatible string. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500.dtsi | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 778775ac42f7..15c11af530ea 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -193,6 +193,46 @@ cmu: clock-controller@b0160000 { #reset-cells = <1>; }; + i2c0: i2c@b0170000 { + compatible = "actions,s900-i2c"; + reg = <0xb0170000 0x4000>; + clocks = <&cmu CLK_I2C0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b0174000 { + compatible = "actions,s900-i2c"; + reg = <0xb0174000 0x4000>; + clocks = <&cmu CLK_I2C1>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b0178000 { + compatible = "actions,s900-i2c"; + reg = <0xb0178000 0x4000>; + clocks = <&cmu CLK_I2C2>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b017c000 { + compatible = "actions,s900-i2c"; + reg = <0xb017c000 0x4000>; + clocks = <&cmu CLK_I2C3>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer: timer@b0168000 { compatible = "actions,s500-timer"; reg = <0xb0168000 0x8000>; From patchwork Thu Jun 25 23:34:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627557 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DB5A2913 for ; Fri, 26 Jun 2020 13:06:39 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4DCA2081A for ; Fri, 26 Jun 2020 13:06:39 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 25 Jun 2020 16:34:34 -0700 (PDT) Received: from localhost.localdomain ([188.24.137.55]) by smtp.gmail.com with ESMTPSA id u2sm13699184edq.29.2020.06.25.16.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 16:34:33 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 08/10] arm: dts: owl-s500-roseapplepi: Use UART clock from CMU Date: Fri, 26 Jun 2020 02:34:20 +0300 Message-Id: <1a98f4f2a8cc5d0277b93dab00b2249cad22f507.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:541 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Remove the UART fixed clock for RoseapplePi SBC and switch to using the clock provided by CMU. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index a2087e617cb2..800edf5d2d12 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -25,12 +25,6 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; - - uart2_clk: uart2-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &twd_timer { @@ -43,5 +37,4 @@ &timer { &uart2 { status = "okay"; - clocks = <&uart2_clk>; }; From patchwork Thu Jun 25 23:34:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627173 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C0BA81392 for ; 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Thu, 25 Jun 2020 16:34:35 -0700 (PDT) Received: from localhost.localdomain ([188.24.137.55]) by smtp.gmail.com with ESMTPSA id u2sm13699184edq.29.2020.06.25.16.34.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 16:34:35 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 09/10] arm: dts: owl-s500-roseapplepi: Add uSD support Date: Fri, 26 Jun 2020 02:34:21 +0300 Message-Id: <521e5024f355c006d7abc8fe30d5cae63a9601f1.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:244 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add uSD support for RoseapplePi SBC using a fixed regulator as a temporary solution until PMIC support becomes available. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index 800edf5d2d12..0a916b6c83a8 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -14,6 +14,7 @@ / { model = "Roseapple Pi"; aliases { + mmc0 = &mmc0; serial2 = &uart2; }; @@ -25,6 +26,55 @@ memory@0 { device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; + + /* Fixed regulator used in the absence of PMIC */ + sd_vcc: sd-vcc { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.1V"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + }; +}; + +&pinctrl { + mmc0_default: mmc0_default { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv_pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias0_pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + + bias1_pinconf { + pins = "sd0_clk"; + bias-pull-down; + }; + }; +}; + +/* uSD */ +&mmc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_default>; + no-sdio; + no-mmc; + no-1-8-v; + cd-gpios = <&pinctrl 117 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <&sd_vcc>; + vqmmc-supply = <&sd_vcc>; }; &twd_timer { From patchwork Thu Jun 25 23:34:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 11627167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 54E5692A for ; Fri, 26 Jun 2020 10:56:46 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2D592206DD for ; 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Thu, 25 Jun 2020 16:34:36 -0700 (PDT) Received: from localhost.localdomain ([188.24.137.55]) by smtp.gmail.com with ESMTPSA id u2sm13699184edq.29.2020.06.25.16.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2020 16:34:36 -0700 (PDT) From: Cristian Ciocaltea To: Rob Herring , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam Subject: [PATCH 10/10] arm: dts: owl-s500-roseapplepi: Enable I2C0 Date: Fri, 26 Jun 2020 02:34:22 +0300 Message-Id: <564bbfeac8c1ed6f103bf1d9be0550856778244f.1593124368.git.cristian.ciocaltea@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:542 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [cristian.ciocaltea[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC. For the moment enable only I2C0, which is used by PMIC. Signed-off-by: Cristian Ciocaltea --- arch/arm/boot/dts/owl-s500-roseapplepi.dts | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index 0a916b6c83a8..f5d515ba9bdd 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -37,7 +37,50 @@ sd_vcc: sd-vcc { }; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; +}; + +&i2c1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_default>; +}; + &pinctrl { + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; + mmc0_default: mmc0_default { pinmux { groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",