From patchwork Tue Jun 30 12:32:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 11633895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D6783174A for ; Tue, 30 Jun 2020 12:36:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF7202073E for ; Tue, 30 Jun 2020 12:36:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WAd/IWzr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF7202073E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=xNDVG65RF+oMpoIglTpyy5LyPKXBhfx8KN6Rp/8MAUk=; b=WAd/IWzr+G/8e7mRgjhr9M/Ied NkUyRGMDiqphQFAOXv+YbQwZ6E5/n7H5WWF4u/3IaIppmCOvtJChNUdY5KMUnrT8XXCk9JHsdq8UJ /YlYkNDzuHs/sxc3UD1pPUrZapndkoqytRva1zr8jpu/aOR4hTE6Dh3BghjG+RDGOojJ1XJzlZoL/ S6Kj5N909HtP7kkp1dSMDGMHH2XrxpzAq3M8ggO5gZnxVUZ1HicYqpvuiPZKOmLmwDEJIwVD67vB5 d/EHwaoPLK5SjpmhfkITra77iNCDo1BsMJei0giy4eEYcKeGAjLFUk2470M+6hFpgxuKc97pn5mUS +vFs73gA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqFTD-00060q-Sk; Tue, 30 Jun 2020 12:34:39 +0000 Received: from szxga05-in.huawei.com ([45.249.212.191] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqFTA-0005zp-A8 for linux-arm-kernel@lists.infradead.org; Tue, 30 Jun 2020 12:34:37 +0000 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BF0B77CBE8A152486CD5; Tue, 30 Jun 2020 20:34:20 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Tue, 30 Jun 2020 20:34:07 +0800 From: Shaokun Zhang To: Subject: [PATCH] arm64: add support for Self-hosted trace Date: Tue, 30 Jun 2020 20:32:13 +0800 Message-ID: <1593520333-42241-1-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.191 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.191 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Anshuman Khandual , Catalin Marinas , Suzuki K Poulose , Shaokun Zhang , Will Deacon , Jonathan Zhou Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4 Self-hosted Trace Extensions. It provides control of exception levels and security states. Let's add this feature detection and enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is supported. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Anshuman Khandual Cc: Mark Rutland Signed-off-by: Shaokun Zhang Signed-off-by: Jonathan Zhou --- arch/arm64/Kconfig | 11 +++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/sysreg.h | 6 ++++++ arch/arm64/kernel/cpufeature.c | 25 ++++++++++++++++++++++++- 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a4a094bedcb2..328188f7962c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1596,6 +1596,17 @@ config ARM64_AMU_EXTN correctly reflect reality. Most commonly, the value read will be 0, indicating that the counter is not enabled. +config ARM64_SELF_HOSTED_TRACE + bool "Enable support for the Self-hosted Trace Extension" + default y + help + The Self-hosted Trace is introduced by ARMv8.4 CPU architecture. + It adds controls of trace in a self-hosted system through system + registers. + + Selecting this option will control trace filter and allow trace + at EL1 and EL0. + endmenu menu "ARMv8.5 architectural features" diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index d7b3bb0cb180..99ffd7b5117a 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -62,7 +62,8 @@ #define ARM64_HAS_GENERIC_AUTH 52 #define ARM64_HAS_32BIT_EL1 53 #define ARM64_BTI 54 +#define ARM64_HAS_SELF_HOSTED_TRACE 55 -#define ARM64_NCAPS 55 +#define ARM64_NCAPS 56 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 463175f80341..137e26bd3cc4 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -183,6 +183,7 @@ #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) @@ -755,6 +756,8 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40 +#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 #define ID_AA64DFR0_WRPS_SHIFT 20 @@ -875,6 +878,9 @@ #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) +#define TRFCR_EL1_E0TRE (BIT(0)) /* Trace is allowed at EL0 */ +#define TRFCR_EL1_E1TRE (BIT(1)) /* Trace is allowed at EL1 */ +#define TRFCR_EL1_TRE (TRFCR_EL1_E0TRE | TRFCR_EL1_E1TRE) /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4ae41670c2e6..6008f06ce2c4 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -368,7 +368,8 @@ static const struct arm64_ftr_bits ftr_id_mmfr0[] = { }; static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { - S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 36, 4, 0), + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 44, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_SELF_HOSTED_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), @@ -1655,6 +1656,15 @@ static void bti_enable(const struct arm64_cpu_capabilities *__unused) } #endif /* CONFIG_ARM64_BTI */ +#ifdef CONFIG_ARM64_SELF_HOSTED_TRACE +static void self_hosted_trace_enable(const struct arm64_cpu_capabilities *__unused) +{ + /* Enable E0TRE and E1TRE in TRFCR_EL1 */ + write_sysreg_s(read_sysreg_s(SYS_TRFCR_EL1) | TRFCR_EL1_TRE, SYS_TRFCR_EL1); + isb(); +} +#endif /* CONFIG_ARM64_SELF_HOSTED_TRACE */ + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2054,6 +2064,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sign = FTR_UNSIGNED, }, #endif +#ifdef CONFIG_ARM64_SELF_HOSTED_TRACE + { + .desc = "Self-hosted Trace", + .capability = ARM64_HAS_SELF_HOSTED_TRACE, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64DFR0_EL1, + .field_pos = ID_AA64DFR0_SELF_HOSTED_SHIFT, + .sign = FTR_UNSIGNED, + .min_field_value = 1, + .cpu_enable = self_hosted_trace_enable, + }, +#endif {}, };