From patchwork Thu Jul 9 21:51:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655179 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A33F13B6 for ; Thu, 9 Jul 2020 21:52:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E2C262084C for ; Thu, 9 Jul 2020 21:52:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kxo+kEZr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726777AbgGIVvs (ORCPT ); Thu, 9 Jul 2020 17:51:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726213AbgGIVvq (ORCPT ); Thu, 9 Jul 2020 17:51:46 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 323FAC08C5CE; Thu, 9 Jul 2020 14:51:46 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id dm19so2980871edb.13; Thu, 09 Jul 2020 14:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MapCcG3rDVQikXJqKbCdGCP4OroaHsdmgZ0eMywfhvo=; b=kxo+kEZr81rysbBpDW6FaEaWc84eFtf3WZtESLQTgJhmcioiOJNCN07LoVYtw3ty9m aOV8ViwYJs/ZYM1SFNxvCPP8rW/qI9Kt13Ij+ir4FaSMdgMNjT0ZSN+YNsEqGyPCZ7lb rZEYyGNCYc54RWDkk5qv8I1PlTL/QiyQoXxKS3wUPXHhESZ8w/RD6sLp6D5aOTU+mf2o EM0QWKmHG+T0u+blNHTf3mrJfLNvAG2WqJVyTCHb+qT8hE7eHc7zKnVZJpUjUctPMX70 tPWWWKMW7J5gpk4kMyGKv8nOCaSohIU+YEUS9fUWIywehEOiuaBWpnoIary3ZLtdzmbe wqiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MapCcG3rDVQikXJqKbCdGCP4OroaHsdmgZ0eMywfhvo=; b=WfY8SJ1xGsr6V6GcVOoXyRk/x31lWNFmEaePovHy2FOrHZMOWnGZclDUe+f8hb/wi8 avPHaXr7MH5Md6cy3NupsA2cRz551wrnZB74pA36eAO099SWEQdxIPqmx8+MRQ+6Aqnl zSz6rRZkGsvftIJYIoTDV1RsBqVxHoQEmn2hTjm73T72m9CuH2cGC02dSTHT6dIdHxf3 XTWvDq62i9V/EWEO5f7j4JWtX1JlBJ3an8j/xT50WzNMihglUeAJPcfjQX0NCPw6yaM0 zkg+poyUVdybLmdsSoLJrvZE02vFkmvROsHS7xFi9bMvmKznhTq3CouQaRbjZzgpVDLq Pc7Q== X-Gm-Message-State: AOAM532nDOgRC7TDjScAxJaGKdvbSKa77OEcJiOaUKjOqGEpdfGypgs4 7rkOZVuJy/Decb0ei3wl1NteG27+eeI= X-Google-Smtp-Source: ABdhPJyYiQY3Yg+GVngUKq8upYFLSVlPdZN7M3IOkn6T6KYxUqF4vxpJrpXMojoLP5kf1UftjSSbdg== X-Received: by 2002:aa7:da8a:: with SMTP id q10mr12000439eds.139.1594331504896; Thu, 09 Jul 2020 14:51:44 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:44 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/6] drivers: thermal: tsens: load regmap from phandle for 8960 Date: Thu, 9 Jul 2020 23:51:31 +0200 Message-Id: <20200709215136.28044-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Devices based on 8060 tsens driver (ipq8064) use the reg of the gcc driver. Permit to load the regmap from a syscon phandle instead of fail as the reg are already used by another driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2a28a5af209e..890baf1b5542 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -168,8 +169,12 @@ static int init_8960(struct tsens_priv *priv) u32 reg_cntl; priv->tm_map = dev_get_regmap(priv->dev, NULL); - if (!priv->tm_map) - return -ENODEV; + if (!priv->tm_map) { + priv->tm_map = syscon_regmap_lookup_by_phandle( + priv->dev->of_node, "regmap"); + if (IS_ERR(priv->tm_map)) + return -ENODEV; + } /* * The status registers for each sensor are discontiguous From patchwork Thu Jul 9 21:51:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655175 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EEAA414E3 for ; Thu, 9 Jul 2020 21:52:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D3F302078B for ; Thu, 9 Jul 2020 21:52:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="r5h0iFWj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726893AbgGIVvt (ORCPT ); Thu, 9 Jul 2020 17:51:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726872AbgGIVvs (ORCPT ); Thu, 9 Jul 2020 17:51:48 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E3D0C08C5CE; Thu, 9 Jul 2020 14:51:48 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id g20so3021006edm.4; Thu, 09 Jul 2020 14:51:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=r5h0iFWjZ7yH13ovMinMCtA81sozhr/xHJCZRQYGfsl91fLXkpE1CuLVOxJ1JNIMa6 5HvQUA6Or0vxyQmrWQsPDrllVOYBZG5miYMMVGZbFfATIuUm+if3QjFPsuxcRUTUVW4o uNIUjL/HfLVCikDzSBVX33hnZV9sVtaVIKJbsqWhaWxQWnBT3NXEGIRQ43ZwOG5TwG82 FqodmZ4y9htxX4Irot9gr8t6kZG1+56A2sSU7hHNTjAbTf3Clvxi8TmXmfRjx6Hg51gK D1Z5jWo6nQFHOz080HwvQFzgdJCIrJ3DzTDRkVgRGyyFbluD+leUHJQeP9RvPN/3b/GO 01Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=Xyidy+WW44el7zOHzjq2DXr8w6TIHp9pFiVkhigFOnGEFjIEQ9U6vozBmWN/LClj3P 2U+ZO41C4jezmAri4B9ZzucWevRFfPBd1ITHSCEJf46KoRMBKVHgcVz0rPbqMAca3jut mNQ3NZKke/7cPwIbwNS6cuqKt8vMpFawRQAu6eRAGqg7nWqvzxe4Mq7URwSp2V9uGNQy iXm9ssozeMIyLEzTiCROxgoyasQjj1is60jKEzUb4pWuqadlAAhV5IVusp3nMfEcyeqe v+7dP3FfChg860LecjbRTheLw+fSSCwnC913pXQaxdDq8mN16kwRXjjmL11dub+LStGz 0qFw== X-Gm-Message-State: AOAM532ErIpcGOHOPEng2bSrWXEjCics5NLGgulucHjNdDEhJSEh+SWY iHlX6vE52yi3HjFiCduDRBtyIxMfPcI= X-Google-Smtp-Source: ABdhPJzTQNAbhhjqi6NgjyNS5C5PZWM2vFRNRRB4kJ09PuTvqqBriaUIP7PlkcdMJTSmRai8ioRf7w== X-Received: by 2002:aa7:d049:: with SMTP id n9mr69202956edo.39.1594331506867; Thu, 09 Jul 2020 14:51:46 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:46 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] drivers: thermal: tsens: add ipq8064 support Date: Thu, 9 Jul 2020 23:51:32 +0200 Message-Id: <20200709215136.28044-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Ipq8064 SoCs based use the same 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 39c4462e38f6..2985a064a0d1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -907,6 +907,9 @@ static const struct of_device_id tsens_table[] = { .compatible = "qcom,msm8996-tsens", .data = &data_8996, }, { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8060, + } { .compatible = "qcom,tsens-v1", .data = &data_tsens_v1, }, { From patchwork Thu Jul 9 21:51:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655171 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C89D86C1 for ; Thu, 9 Jul 2020 21:52:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF2752076A for ; Thu, 9 Jul 2020 21:52:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gigcSDuZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726923AbgGIVvv (ORCPT ); Thu, 9 Jul 2020 17:51:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726872AbgGIVvu (ORCPT ); Thu, 9 Jul 2020 17:51:50 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ABE3C08C5CE; Thu, 9 Jul 2020 14:51:50 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id f12so3842114eja.9; Thu, 09 Jul 2020 14:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Hc4W3Js1OftAK/QTedCJSjWZ8huqh9WCdiCmuDtrwg=; b=gigcSDuZHB3jHtEQaZXocB2czt9wFU3H/z8E+3rF8NKJmU1HOisO/kqGIRjRQujkBC FGDwZFBzUwHKajoe3osHcrEOzBNUMLgQH9+VO3w/9bnji3ugqjbwkFZlCwjudJkEIh7V s797lbsoTzH0KzjeU1pLFCdRAbAqNRVW5iQH/SxyiuTx/k06JR/ZcVTH47jxvPMbMbpr SmqAuPG6yqQHhE+PU8IEVT5lkZsOB4EO9OkuKDPQXj7Z4Wc41EYYx5OxUcvhHIgMe17h lj35Tld+GwKEmNEXk11nIncoQejSmffsTyCstb8LOVfs47yL9o0I7na2b2VsQQ+xHObB uhvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Hc4W3Js1OftAK/QTedCJSjWZ8huqh9WCdiCmuDtrwg=; b=qPNkasUHIgNwnvSzWkymO9HrXS4Xx50NIceKQ2GcOFyAoJAalTBBiDIA7tYIuo8fXK WKFuzX7I4Sk3iPmcmI7YEQQlHCCh/OUUts5Z8ZN6CPtExUEeUfxq8Q1pn+3aHdoYF6iP nQj4vorKZUvsk2+MpAGNyBGl/cospOvbNCr8f+cpVin/0PRQhPT9tQAEpaFkvf6M4TJ/ Elg1GKgq/1aV5mLAPdiYH+kgvQqju7eSnzOi9+bXc9WxV2FmvURS9vhJqnX9aJikqo+z 70dMmBpxdYEa7huW8kU3Cn8iCkB7e/oIMybTx2OUHdHAgQfcwj3S4pwGn/Igab4OHeqt a55g== X-Gm-Message-State: AOAM532ghaEibkjTLktrhSe9Q8YM5PnbCPRT2Vz4Au1KsEJyEEahH9XM E94w6tJwJknv4btbDgdLTFY= X-Google-Smtp-Source: ABdhPJwOcYX2QYznh3ZcvNVgFGDLNt77XVMVqpavPLymkdeUeAIVxVaOiwnFl8Trth5eBSHt8su4rA== X-Received: by 2002:a17:906:2505:: with SMTP id i5mr57304428ejb.545.1594331508944; Thu, 09 Jul 2020 14:51:48 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:48 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] dt-bindings: thermal: tsens: document ipq8064 bindings Date: Thu, 9 Jul 2020 23:51:33 +0200 Message-Id: <20200709215136.28044-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the use of regmap phandle for ipq8064 SoCs Signed-off-by: Ansuel Smith --- .../bindings/thermal/qcom-tsens.yaml | 51 ++++++++++++++++--- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index d7be931b42d2..5ceb5d720e16 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -24,6 +24,7 @@ properties: - enum: - qcom,msm8916-tsens - qcom,msm8974-tsens + - qcom,ipq8064-tsens - const: qcom,tsens-v0_1 - description: v1 of TSENS @@ -47,6 +48,11 @@ properties: - description: TM registers - description: SROT registers + regmap: + description: + Phandle to the gcc. On ipq8064 SoCs gcc and tsense share the same regs. + $ref: /schemas/types.yaml#/definitions/phandle + interrupts: minItems: 1 items: @@ -111,17 +117,48 @@ allOf: interrupt-names: minItems: 2 -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-tsens + then: + required: + - compatible + - regmap + - "#qcom,sensors" + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + + else: + required: + - compatible + - reg + - "#qcom,sensors" + - interrupts + - interrupt-names + - "#thermal-sensor-cells" additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + tsens: thermal-sensor@900000 { + compatible = "qcom,ipq8064-tsens"; + regmap = <&gcc>; + + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + - | #include // Example 1 (legacy: for pre v1 IP): From patchwork Thu Jul 9 21:51:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655163 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C5116C1 for ; Thu, 9 Jul 2020 21:52:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 474412080D for ; Thu, 9 Jul 2020 21:52:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MGsAKPOe" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726991AbgGIVv4 (ORCPT ); Thu, 9 Jul 2020 17:51:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726935AbgGIVvw (ORCPT ); Thu, 9 Jul 2020 17:51:52 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5606AC08C5CE; Thu, 9 Jul 2020 14:51:52 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id d15so2997691edm.10; Thu, 09 Jul 2020 14:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rujU6IuUKyP/qpmu9fxGZQc5R/2dPvNSFc6+rG5kang=; b=MGsAKPOeaHvuWHlopnqYbmaTbZXu4TLmIhZSmA7GYtK1msm7XTfF1ClebJ8IlVtnMN P2qF49j4pmXtZgD5m0YN4JeYgmUydgSjCS8qDjj2MVyG7tYqSd3EKbI8gYpeH2X/ecKM R/L9jvs3wNnNLT121hEHWsMQUslhdiqGe9XH2LdeqIqrbvTzSWj+xE8eo6hz19AuuL7B YFiR0DBign7rXiMtEbQWdUFwxNzKerVE9KhoC8bqzTHjFpbTafiIcFAFlIbKy+IF6n87 J/pBCLafZC+uxKC0tWbw9+MzQtCbHrVVlXrQq35JcOcWsbrv7fZPvitZXFbACA5uP3P0 S71w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rujU6IuUKyP/qpmu9fxGZQc5R/2dPvNSFc6+rG5kang=; b=fNjanbjoRKjxjjSBvTn+eGd+wY/rZzHQgeNhAiGKVzYPBSbNX0PL9WpgIBva0fVmmS GW20wSqQw7qcwQWrGUFYEcYsj6WPbSXOLY2au01T5N4EZajRvbVv3K/QTuaaGrOe1kh3 d1v6kgWBBQzjfGlz4QuZLlUlUZhrm6ENMBbg8Bb2Mgg0zydy+tmd1eLK/g9ebVHOpO2t uKVXq1rUvtqeaUW97ZUU77o0NBQSSITS+gsheWADhxYj1FHgH2MfNhn9m/MqKW0DaXwJ 04ERKnIgrhIDRuWHAaf4pVeszxeor1Fnvx4e3mKE7cBeiHurvI+bDJqx8p7jF6FbtrR3 8nFg== X-Gm-Message-State: AOAM5332ix0H6TJEanePcQpO0yIgp0Z4VtKaaH/CCJCPFOjWqGwbgHiJ aZa3zWDCr0VeekowBiTbAP7Ytj97VDk= X-Google-Smtp-Source: ABdhPJyb/wbopOhZ3AEUXaNOhNif4H0kDQiTFUkPGzGC2B/ydsUrgprxHHsxyxOCAuOEdLVhZ2709w== X-Received: by 2002:a05:6402:22f0:: with SMTP id dn16mr75165270edb.83.1594331510980; Thu, 09 Jul 2020 14:51:50 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:50 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] drivers: thermal: tsens: add interrupt support for 9860 driver Date: Thu, 9 Jul 2020 23:51:34 +0200 Message-Id: <20200709215136.28044-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add interrupt support for 9860 tsens driver used to set thermal trip point for the system. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 196 +++++++++++++++++++++++++++--- drivers/thermal/qcom/tsens.h | 1 + 2 files changed, 183 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 890baf1b5542..2dc670206896 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -27,7 +28,6 @@ /* CNTL_ADDR bitmasks */ #define EN BIT(0) #define SW_RST BIT(1) -#define SENSOR0_EN BIT(3) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) #define MEASURE_PERIOD 1 @@ -41,14 +41,26 @@ #define THRESHOLD_ADDR 0x3624 /* THRESHOLD_ADDR bitmasks */ +#define THRESHOLD_MAX_CODE 0x20000 +#define THRESHOLD_MIN_CODE 0 #define THRESHOLD_MAX_LIMIT_SHIFT 24 #define THRESHOLD_MIN_LIMIT_SHIFT 16 #define THRESHOLD_UPPER_LIMIT_SHIFT 8 #define THRESHOLD_LOWER_LIMIT_SHIFT 0 +#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MAX_LIMIT_SHIFT) +#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MIN_LIMIT_SHIFT) +#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_UPPER_LIMIT_SHIFT) +#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_LOWER_LIMIT_SHIFT) /* Initial temperature threshold values */ -#define LOWER_LIMIT_TH 0x50 -#define UPPER_LIMIT_TH 0xdf +#define LOWER_LIMIT_TH_8960 0x50 +#define UPPER_LIMIT_TH_8960 0xdf +#define LOWER_LIMIT_TH_8064 0x9d /* 95C */ +#define UPPER_LIMIT_TH_8064 0xa6 /* 105C */ #define MIN_LIMIT_TH 0x0 #define MAX_LIMIT_TH 0xff @@ -57,6 +69,169 @@ #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 +#define TSENS_EN BIT(0) +#define TSENS_SW_RST BIT(1) +#define TSENS_ADC_CLK_SEL BIT(2) +#define SENSOR0_EN BIT(3) +#define SENSOR1_EN BIT(4) +#define SENSOR2_EN BIT(5) +#define SENSOR3_EN BIT(6) +#define SENSOR4_EN BIT(7) +#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \ + SENSOR2_EN | SENSOR3_EN | SENSOR4_EN) +#define TSENS_8064_SENSOR5_EN BIT(8) +#define TSENS_8064_SENSOR6_EN BIT(9) +#define TSENS_8064_SENSOR7_EN BIT(10) +#define TSENS_8064_SENSOR8_EN BIT(11) +#define TSENS_8064_SENSOR9_EN BIT(12) +#define TSENS_8064_SENSOR10_EN BIT(13) +#define TSENS_8064_SENSORS_EN (SENSORS_EN | \ + TSENS_8064_SENSOR5_EN | \ + TSENS_8064_SENSOR6_EN | \ + TSENS_8064_SENSOR7_EN | \ + TSENS_8064_SENSOR8_EN | \ + TSENS_8064_SENSOR9_EN | \ + TSENS_8064_SENSOR10_EN) + +u32 tsens_8960_slope[] = { + 1176, 1176, 1154, 1176, + 1111, 1132, 1132, 1199, + 1132, 1199, 1132 + }; + +/* Temperature on y axis and ADC-code on x-axis */ +static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return adc_code * slope + offset; +} + +static void notify_uspace_tsens_fn(struct work_struct *work) +{ + struct tsens_sensor *s = container_of(work, struct tsens_sensor, + notify_work); + + sysfs_notify(&s->tzd->device.kobj, NULL, "type"); +} + +static void tsens_scheduler_fn(struct work_struct *work) +{ + struct tsens_priv *priv = + container_of(work, struct tsens_priv, tsens_work); + unsigned int threshold, threshold_low, code, reg, sensor, mask; + bool upper_th_x, lower_th_x; + int ret; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR; + ret = regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg); + if (ret) + return; + + mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR); + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold); + if (ret) + return; + threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK) >> + THRESHOLD_LOWER_LIMIT_SHIFT; + threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK) >> + THRESHOLD_UPPER_LIMIT_SHIFT; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + + ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor); + if (ret) + return; + sensor &= (uint32_t)TSENS_8064_SENSORS_EN; + sensor >>= SENSOR0_SHIFT; + + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + + /* Skip if the sensor is disabled */ + if (sensor & 1) { + ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code); + if (ret) + return; + upper_th_x = code >= threshold; + lower_th_x = code <= threshold_low; + if (upper_th_x) + mask |= UPPER_STATUS_CLR; + if (lower_th_x) + mask |= LOWER_STATUS_CLR; + if (upper_th_x || lower_th_x) { + /* Notify user space */ + schedule_work(&priv->sensor[0].notify_work); + pr_debug("Trigger (%d degrees) for sensor %d\n", + code_to_mdegC(code, &priv->sensor[0]), 0); + } + } + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg & mask); +} + +static irqreturn_t tsens_isr(int irq, void *data) +{ + struct tsens_priv *priv = data; + + schedule_work(&priv->tsens_work); + return IRQ_HANDLED; +} + +static void hw_init(struct tsens_priv *priv) +{ + int ret; + unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0; + unsigned int reg_status_cntl = 0; + + regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST); + + reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18) | + (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_status_cntl); + reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR | + MIN_STATUS_MASK | MAX_STATUS_MASK; + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg_status_cntl); + reg_cntl |= TSENS_EN; + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + + regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg); + if (priv->num_sensors > 1) + reg_cfg = (reg_cfg & ~CONFIG_MASK) | CONFIG; + else + reg_cfg = (reg_cfg & ~CONFIG_MASK) | + (CONFIG << CONFIG_SHIFT_8660); + regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg); + + reg_thr |= (LOWER_LIMIT_TH_8064 << THRESHOLD_LOWER_LIMIT_SHIFT) | + (UPPER_LIMIT_TH_8064 << THRESHOLD_UPPER_LIMIT_SHIFT) | + (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT) | + (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT); + + regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr); + + ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr, + IRQF_TRIGGER_RISING, "tsens_interrupt", priv); + if (ret < 0) { + dev_err(priv->dev, "request_irq FAIL: %d", ret); + return; + } + + INIT_WORK(&priv->tsens_work, tsens_scheduler_fn); +} + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -186,6 +361,8 @@ static int init_8960(struct tsens_priv *priv) if (i >= 5) priv->sensor[i].status = S0_STATUS_ADDR + 40; priv->sensor[i].status += i * 4; + priv->sensor[i].slope = tsens_8960_slope[i]; + INIT_WORK(&priv->sensor[i].notify_work, notify_uspace_tsens_fn); } reg_cntl = SW_RST; @@ -236,18 +413,9 @@ static int calibrate_8960(struct tsens_priv *priv) kfree(data); - return 0; -} - -/* Temperature on y axis and ADC-code on x-axis */ -static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) -{ - int slope, offset; + hw_init(priv); - slope = thermal_zone_get_slope(s->tzd); - offset = CAL_MDEGC - slope * s->offset; - - return adc_code * slope + offset; + return 0; } static int get_temp_8960(const struct tsens_sensor *s, int *temp) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 59d01162c66a..2f145001e4d5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,6 +48,7 @@ enum tsens_irq_type { struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; + struct work_struct notify_work; int offset; unsigned int hw_id; int slope; From patchwork Thu Jul 9 21:51:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655167 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D2D3C14E3 for ; Thu, 9 Jul 2020 21:52:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B67052076A for ; Thu, 9 Jul 2020 21:52:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lpqg4hSj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726962AbgGIVv4 (ORCPT ); Thu, 9 Jul 2020 17:51:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726872AbgGIVvy (ORCPT ); Thu, 9 Jul 2020 17:51:54 -0400 Received: from mail-ed1-x544.google.com (mail-ed1-x544.google.com [IPv6:2a00:1450:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E5ACC08C5CE; Thu, 9 Jul 2020 14:51:54 -0700 (PDT) Received: by mail-ed1-x544.google.com with SMTP id d18so3013945edv.6; Thu, 09 Jul 2020 14:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JK4Zw9j/9Nb+LcGFZ1W5eUWt8QvNlgcbGlicFgmNlgc=; b=lpqg4hSjr3FxFCd1jZMnDK108KGA0tHFf1qXzQG+VrSwbdNGCgdgwyg3bN9SuEyrYr IHuNFzM0j+Vp4egvYZrgZCYaJuuhWLYbTcwHUFvTtbMamU1GYtPh9WqEGjkuRtiIEVaz iRdcI0tv5/BAximGo6Abtro+C2yaafWTRje2+u9vxGPSmcDLdt44J3VzUAEotua+6y+D xacLOnOxwhn2tldxB4xvOYbSqUNjpVlpdNeIrx6qY1Nf7gs2YN6mR+njvZWiYTvb3p74 bPD33a4Z0zr+bho1UzU3ClY3jEuLobtR9ldj8ZRiqWD2g6+UrBw8t3UET/F858WZ48Eu qzWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JK4Zw9j/9Nb+LcGFZ1W5eUWt8QvNlgcbGlicFgmNlgc=; b=W0XXAOE9ClQcVvggHd2WXhicHQNfrz/xsfWjjDD7HbBQiVan4aTolNPHPmwkV1oSed sHQjNn0eCZ1Bs3nr1PPtxj5zcaI8UcAL/ucs+0TSLlN3R2/id3nimQt8xR94FoZUQMBI h1hw6SQs8IZc/+0L9TPviGBi/zkRBnpz5MJtXouH6t5pAGXkwKfGoHowniKSmaa6vjjD tTehsOqww/PPSNhHwSK1ujsEimPUkUxIFbDDvVZsdzNKb/ePG95Ol14M4tU3/JcxHR67 w4f4B2WtCtaVxVees3Cp9HO9bby45k0blKr+q7qidSjYftDcEj+i5WqLS/YOKZhF8un6 Zuxg== X-Gm-Message-State: AOAM533QQfgAUyfyBAurbjKPsm8O1XqfALE4tRD3aiqmlBO+kZrw/BWj WSpi4hRdGroPt9e1JpbHJk4= X-Google-Smtp-Source: ABdhPJydKjHsm+/9nDCCgVV1a1f67AlisMviUtWQEEFcnf/Ig/0aJhwmWvC4Xet7z5KsL0fDYFfoKA== X-Received: by 2002:a50:ee01:: with SMTP id g1mr65996830eds.264.1594331513117; Thu, 09 Jul 2020 14:51:53 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:52 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] drivers: thermal: tsens: add support for custom set_trip function Date: Thu, 9 Jul 2020 23:51:35 +0200 Message-Id: <20200709215136.28044-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org 8960 tsens driver have a custom implementation to set set_trip function. Permit the generic driver to use the custom function if provided. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 4 ++++ drivers/thermal/qcom/tsens.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 2985a064a0d1..2b55b34d66fb 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -530,6 +530,10 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + // Use the driver set_trips if present + if (priv->ops->set_trip_temp) + return priv->ops->set_trip_temp(_sensor, low, high); + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2f145001e4d5..c27fae39d542 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -65,6 +65,7 @@ struct tsens_sensor { * @suspend: Function to suspend the tsens device * @resume: Function to resume the tsens device * @get_trend: Function to get the thermal/temp trend + * @set_trip_temp: Function to get trip temp */ struct tsens_ops { /* mandatory callbacks */ @@ -77,6 +78,7 @@ struct tsens_ops { int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); + int (*set_trip_temp)(void *data, int trip, int temp); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ From patchwork Thu Jul 9 21:51:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11655161 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D21CA6C1 for ; Thu, 9 Jul 2020 21:51:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B42082078B for ; Thu, 9 Jul 2020 21:51:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZxPgT4AU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727024AbgGIVv6 (ORCPT ); Thu, 9 Jul 2020 17:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726989AbgGIVv4 (ORCPT ); Thu, 9 Jul 2020 17:51:56 -0400 Received: from mail-ed1-x541.google.com (mail-ed1-x541.google.com [IPv6:2a00:1450:4864:20::541]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66D7EC08C5DC; Thu, 9 Jul 2020 14:51:56 -0700 (PDT) Received: by mail-ed1-x541.google.com with SMTP id d15so2997801edm.10; Thu, 09 Jul 2020 14:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ItfQ8L/Er3Hk4c2uSxofOAEu4o/bM64EAYLfz2K5ECQ=; b=ZxPgT4AUp2+vo6mZ57j8c7IbaQnpm3m6ie3CigiT9z5eT/38nTYREAtriLTnkq8Lwf 4GpfBUCR+F4TwwtJDKmTMikAA1mYDkCtZnvenE0cd5r25is63mIL2oMDAwCJfIi7kttm J/1DTMkeonJSRMV9ua+TFSTSS1Y8Qjsr5GUALrcsfDmNmX1QW7LyP6AxMSx3wp04RxdP nTHeNyEh7Yd7TMelPlk+WfgjOwiAjrEYG2zHWnWX+mIMjXc7maFTPWUgQnKpQMV70x+o IYPo6KlxpBxCqrrTZAcNZconvzQTlE3xHJpZbTfvic42kgu5iYu35H+grluIU4UdG/M8 DvgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ItfQ8L/Er3Hk4c2uSxofOAEu4o/bM64EAYLfz2K5ECQ=; b=oDoHhkjQIHTQzV/vPY3ZGXH0mFSut5L6Jumyy9ANpZmhdiKPYw93K5ZqsZoYXCXdTx fwGYNtRyFX/+2InFzypRkV0VyB3EFZ8X8geuVSC5pPvmKrfw7h79bUmvkxgcrKGyVCHT 5hSIgTJ0Sx7o+1QAObc22j31L7l/+dYdDfV4bTNLXez3tys+Tgz9sZfSziWrxokYhSVu io5FJGii7O+jADOGTVYMH2CQFatFBHg7ZNjTPNRKOWs51Xtpp8VWHVyn+7MnNwk8rqtk S+sTIPnlIjao0/WaXkO/mUp97Cqx5DWIZkaLH34fImEmaoAKF84n/yTM+hQKE5HeSghx kIsQ== X-Gm-Message-State: AOAM531wbWz/FEjk/K2ZyfLJTRndWVT8aUcxFYJOj0fCTjUS+tsEV3fg qZuIsBbV/CvaYVdtuiPvlME= X-Google-Smtp-Source: ABdhPJz3P5Adz2dZxyYUEZXHp3Fcl0wTBk1V3i80J7DWD2gRIAxKKfpvDMvc+IKU01B3QLekYTH+sA== X-Received: by 2002:aa7:d285:: with SMTP id w5mr46413518edq.174.1594331515142; Thu, 09 Jul 2020 14:51:55 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id e16sm2498260ejt.14.2020.07.09.14.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 14:51:54 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] drivers: thermal: tsens: add set_trip support for 8960 Date: Thu, 9 Jul 2020 23:51:36 +0200 Message-Id: <20200709215136.28044-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200709215136.28044-1-ansuelsmth@gmail.com> References: <20200709215136.28044-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add custom set_trip function for 8960 needed to set trip point to the tsens driver for 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2dc670206896..321791b8aabf 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -93,6 +93,15 @@ TSENS_8064_SENSOR9_EN | \ TSENS_8064_SENSOR10_EN) +/* Trips: from very hot to very cold */ +enum tsens_trip_type { + TSENS_TRIP_STAGE3 = 0, + TSENS_TRIP_STAGE2, + TSENS_TRIP_STAGE1, + TSENS_TRIP_STAGE0, + TSENS_TRIP_NUM, +}; + u32 tsens_8960_slope[] = { 1176, 1176, 1154, 1176, 1111, 1132, 1132, 1199, @@ -110,6 +119,16 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } +static int mdegC_to_code(int degC, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return degC / slope - offset; +} + static void notify_uspace_tsens_fn(struct work_struct *work) { struct tsens_sensor *s = container_of(work, struct tsens_sensor, @@ -442,6 +461,64 @@ static int get_temp_8960(const struct tsens_sensor *s, int *temp) return -ETIMEDOUT; } +static int set_trip_temp_ipq8064(void *data, int trip, int temp) +{ + unsigned int reg_th, reg_cntl; + int ret, code, code_chk, hi_code, lo_code; + const struct tsens_sensor *s = data; + struct tsens_priv *priv = s->priv; + + code = mdegC_to_code(temp, s); + code_chk = code; + + if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE) + return -EINVAL; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_cntl); + if (ret) + return ret; + + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th); + if (ret) + return ret; + + hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK) + >> THRESHOLD_UPPER_LIMIT_SHIFT; + lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK) + >> THRESHOLD_LOWER_LIMIT_SHIFT; + + switch (trip) { + case TSENS_TRIP_STAGE3: + code <<= THRESHOLD_MAX_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MAX_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE2: + if (code_chk <= lo_code) + return -EINVAL; + code <<= THRESHOLD_UPPER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE1: + if (code_chk >= hi_code) + return -EINVAL; + code <<= THRESHOLD_LOWER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE0: + code <<= THRESHOLD_MIN_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MIN_LIMIT_MASK; + break; + default: + return -EINVAL; + } + + ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code); + if (ret) + return ret; + + return 0; +} + static const struct tsens_ops ops_8960 = { .init = init_8960, .calibrate = calibrate_8960, @@ -450,6 +527,7 @@ static const struct tsens_ops ops_8960 = { .disable = disable_8960, .suspend = suspend_8960, .resume = resume_8960, + .set_trip_temp = set_trip_temp_ipq8064, }; struct tsens_plat_data data_8960 = {