From patchwork Fri Jul 10 19:45:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657329 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3740013BD for ; Fri, 10 Jul 2020 19:46:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1942A20853 for ; Fri, 10 Jul 2020 19:46:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sFqj3VWs" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728534AbgGJTqM (ORCPT ); Fri, 10 Jul 2020 15:46:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728535AbgGJTqJ (ORCPT ); Fri, 10 Jul 2020 15:46:09 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900EBC08C5DC; Fri, 10 Jul 2020 12:46:08 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id l12so7288944ejn.10; Fri, 10 Jul 2020 12:46:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MapCcG3rDVQikXJqKbCdGCP4OroaHsdmgZ0eMywfhvo=; b=sFqj3VWsrm76BzKIOMnLfmJvaMAqKXp1P4/5CpT5DwgTy3BhBvsBvqJpqrrf91VJJm LRAo2Wi/adJcTO+0PtFX7iXLe9TG9Xu0DwhKbK9LvP0qvwyfQq9snm03EqxNiMJbVK1w t9l90w9zMVmGvLmgCiFODb7/IuRPm8kM5d2qr4uAU/LHuUAMk3RSeP5v6gx5cT8L9Lbk 7fv1+C9kv0NltibnHjby+5bJkih44Mrr2ifkD3zA26ji5F8m+x9oybw01nv0tR4FLzWa RzHyT6XAO43QnCu6/TLHbax1fpd2VxdY8RS2ND/a3qTkTqEcB08p96agDvjPP/RdlViK zz3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MapCcG3rDVQikXJqKbCdGCP4OroaHsdmgZ0eMywfhvo=; b=CDYK5oLx/mFdwAeGThguofhtgsoiBaCb4dfar1hGjDrrPZZfZSxuSjRsdxi9Gy3SQA tITv81VJhsiBNMO//dmNZxYrT4y70aYlSFcg/UvraFHK+7Y/1gfmm+dIuNqCGZDp8Uop gP1slRtpOKSVjStvskgcSa+HW8CCk0cR20Nz8bYSV3fmKUWP0fvejtFZxrgEvtH2dlBd 2vZfeaCvEnxFZLD2fl8ueA/88E5WLnuu3iFZ3DQFfWqbXtGmskFyhW1mTBLcyY4BeNzt yjq1LDTJLZO7ndfZHJm3crX+lYWBeOTAxmdSvvsjo7a1knlfaW/DyEMKvBq6FXc+7ru/ lULQ== X-Gm-Message-State: AOAM532FDk6fQSYro0I8JxGD8ewKF/UGu7blvK/d/TZ4JgUkMsu4ZYWf CadjSjD8k/KJgM7TS2Kv4FI= X-Google-Smtp-Source: ABdhPJyjeBCtVLAvL+QcjeWmyjyJ130OGzPm5THEkcOG8tUsCE7Tz0Y+MoqkD4O/M+IA9BN1RdJeIA== X-Received: by 2002:a17:906:2b9b:: with SMTP id m27mr51778565ejg.19.1594410367046; Fri, 10 Jul 2020 12:46:07 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:06 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] drivers: thermal: tsens: load regmap from phandle for 8960 Date: Fri, 10 Jul 2020 21:45:52 +0200 Message-Id: <20200710194558.26487-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Devices based on 8060 tsens driver (ipq8064) use the reg of the gcc driver. Permit to load the regmap from a syscon phandle instead of fail as the reg are already used by another driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2a28a5af209e..890baf1b5542 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -168,8 +169,12 @@ static int init_8960(struct tsens_priv *priv) u32 reg_cntl; priv->tm_map = dev_get_regmap(priv->dev, NULL); - if (!priv->tm_map) - return -ENODEV; + if (!priv->tm_map) { + priv->tm_map = syscon_regmap_lookup_by_phandle( + priv->dev->of_node, "regmap"); + if (IS_ERR(priv->tm_map)) + return -ENODEV; + } /* * The status registers for each sensor are discontiguous From patchwork Fri Jul 10 19:45:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657337 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2630013BD for ; Fri, 10 Jul 2020 19:46:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B5BE207FB for ; Fri, 10 Jul 2020 19:46:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UN7Gn4uP" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728454AbgGJTqj (ORCPT ); Fri, 10 Jul 2020 15:46:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728276AbgGJTqK (ORCPT ); Fri, 10 Jul 2020 15:46:10 -0400 Received: from mail-ed1-x542.google.com (mail-ed1-x542.google.com [IPv6:2a00:1450:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7EA14C08C5DD; Fri, 10 Jul 2020 12:46:10 -0700 (PDT) Received: by mail-ed1-x542.google.com with SMTP id by13so5512438edb.11; Fri, 10 Jul 2020 12:46:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=UN7Gn4uPQtMnfHppgaJpBhNkiEB9r7978G3WIOnisLXwrh2OI9cn0BCtUqf1MPwZVY W2ZJhJmz2/t842wvrC1Jhh1tusoJ5T8+hffg2jWdu+jG4pSdsmJ6vN5kJQTE8OsGz8hq 2jPSCCNk5NziX1RpxRuwApyp5Hjfhl6pjGAxGswNZO7WmH6pQnYgP2iD28RlrSVNMmvv fjErgvT8SBbvPO2YdmtXeYgIvVQsEVzur9GXwGZeZdijnTZI+eFOZW5rQBepuqlw80pj XT+1icbJI2CMn155prTr+XDtVeRsyDWmi78OBlqjGCBdLZ9yk5rE8QqAAOmd9C4B2qUx 2sMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z7hfnd49qzQu+v3pW4+QTWy4zDs6kHByKCCdtVpj2B8=; b=guyEsEUiJhmYPhXjqS6YezBLnaYZ0OPE0eP8HuuI5z3yLcXgoR8NAUFl7dFd3tFLm+ qPc61xscULmTErOt8Yaaj5/10PrJ0skxPNqBVI6cYYPPZJ+POuGKhsHnzaiOjOXwBki2 Nn2V1KMUDgUb1//6zdVRsdOhtm6KAifLjp3duaGpZD2FtlwMU/OKW4G54JMCM+tHv4QJ PhWoSeF2LlNineVeETFfo8eqVmZrC8ZEImvKiVI67+ZlBRmkIpOBu7V7oJUTJF+BjvGj TdfNo3IoVAUOOQ8dIpKhIH29x3TiAjuH2zb9tzqKB08By2hk6++q8J6+6qBVVQCUGC0B cSFw== X-Gm-Message-State: AOAM533QTsOb3Xj1KCyv6ukkj1PrCe0es3oH7tFWYtYzly/f8mdIhyaa bATBehaXjEBqqJTu6ifNHrs= X-Google-Smtp-Source: ABdhPJykPK6hXQIbX7d3fld79E3i/oUJKENzcBCVYhZYKx1YdcxH769O2NWFAYLrpNr/TrdEOTIbWA== X-Received: by 2002:a05:6402:134e:: with SMTP id y14mr79734387edw.4.1594410369165; Fri, 10 Jul 2020 12:46:09 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:08 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] drivers: thermal: tsens: add ipq8064 support Date: Fri, 10 Jul 2020 21:45:53 +0200 Message-Id: <20200710194558.26487-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Ipq8064 SoCs based use the same 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 39c4462e38f6..2985a064a0d1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -907,6 +907,9 @@ static const struct of_device_id tsens_table[] = { .compatible = "qcom,msm8996-tsens", .data = &data_8996, }, { + .compatible = "qcom,ipq8064-tsens", + .data = &data_8060, + } { .compatible = "qcom,tsens-v1", .data = &data_tsens_v1, }, { From patchwork Fri Jul 10 19:45:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657317 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 51F8213BD for ; Fri, 10 Jul 2020 19:46:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38A852078D for ; Fri, 10 Jul 2020 19:46:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="sFQFMa5M" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728560AbgGJTqQ (ORCPT ); Fri, 10 Jul 2020 15:46:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728535AbgGJTqN (ORCPT ); Fri, 10 Jul 2020 15:46:13 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9524DC08E6DC; Fri, 10 Jul 2020 12:46:13 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id w6so7305356ejq.6; Fri, 10 Jul 2020 12:46:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Neukk5Ha30hw7xCMR87weS6wdEy4yDg0uzyL5tr2Zk=; b=sFQFMa5MwgkhmWpwuF4Tqu66g6+70VZ96IG1D1bGOW/13LYgHhxJDi/ScNr7F4cOfm zEl3/5l6Apw9O73pIeE5+lQe4qnkH1ciwhbT9i3Gm/gzJsuuJXzyYcleBgPMxL1U2ZQq Ex6LqNDV36UVm92LsCTd0raOaa2EG/qu4hr/2BHUPEAJKdQEmWUnC2NRPe+BRYCYulcX mS+NXXobRtQ/ddxIQjffZbLH3OX7TKHt7R25J0CYuWzDu82AZWSfcqDptDL20vnKVkWu x5stIIGSsCCPGsoni3+cNFG1pYsulANcwnXpCXSoqbtc2elCcE5NfQ78Ik1CpcqgsoX3 Jw/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Neukk5Ha30hw7xCMR87weS6wdEy4yDg0uzyL5tr2Zk=; b=p9YN4paKmw9yz0gNgcP2+0XJ302oh9OBX3HxEapXIM/cWPETNukpCH4YusAdI7O7TP YBPQwB2fFTJMogzYC9Vdpos7NYu06biuTg/4TTJifFnrV6s2RgrRqlNBLHAAUgOFBoqH uE3eCJm8Wt8NrXgd8fwgrEBbd1gDrSA39Q4zBDuqMBiQE/m0fIRet+cN2bUzItJyBHSq XsteVeplb+kaOJDQH4O0TnQPVHEP4pnuvsVnBxkkfRuZGrw2qHhANquTY2HwUESluuwZ jJoPAYgNjuLxmvDWGe3TpWGgg8u1Qkw9wEkNQ+wP9zNXKPTPsuYtvdUmAOsFHBWa3qOT VZLw== X-Gm-Message-State: AOAM530pglxR4WMn9a5lnVG352q7RsMyrtMxBiDidpmcg0yGUKz3CU6s PQl8ji+WQgHvbiqy14iwsM2z3Tivrtg= X-Google-Smtp-Source: ABdhPJz6Da6O0pPqNk+DasQ9vpu/01bXtZQv/a1Bp7pcRV30Cdw2jj2veKSqdoXlPu39xMduWFE1Mg== X-Received: by 2002:a17:906:391:: with SMTP id b17mr49916697eja.282.1594410371260; Fri, 10 Jul 2020 12:46:11 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:10 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: thermal: tsens: document ipq8064 bindings Date: Fri, 10 Jul 2020 21:45:54 +0200 Message-Id: <20200710194558.26487-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the use of regmap phandle for ipq8064 SoCs Signed-off-by: Ansuel Smith --- .../bindings/thermal/qcom-tsens.yaml | 53 ++++++++++++++++--- 1 file changed, 46 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index d7be931b42d2..964a68d194d2 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -19,6 +19,11 @@ description: | properties: compatible: oneOf: + - description: msm9860 TSENS based + items: + - enum: + - qcom,ipq8064-tsens + - description: v0.1 of TSENS items: - enum: @@ -47,6 +52,11 @@ properties: - description: TM registers - description: SROT registers + regmap: + description: + Phandle to the gcc. On ipq8064 SoCs gcc and tsense share the same regs. + $ref: /schemas/types.yaml#/definitions/phandle + interrupts: minItems: 1 items: @@ -85,12 +95,18 @@ properties: Number of cells required to uniquely identify the thermal sensors. Since we have multiple sensors this is set to 1 +required: + - compatible + - interrupts + - "#thermal-sensor-cells" + allOf: - if: properties: compatible: contains: enum: + - qcom,ipq8064-tsens - qcom,msm8916-tsens - qcom,msm8974-tsens - qcom,msm8976-tsens @@ -111,17 +127,40 @@ allOf: interrupt-names: minItems: 2 -required: - - compatible - - reg - - "#qcom,sensors" - - interrupts - - interrupt-names - - "#thermal-sensor-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-tsens + then: + required: + - regmap + + else: + required: + - reg + - interrupt-names + - "#qcom,sensors" additionalProperties: false examples: + - | + #include + // Example msm9860 based SoC (ipq8064): + tsens: thermal-sensor { + compatible = "qcom,ipq8064-tsens"; + regmap = <&gcc>; + + nvmem-cells = <&tsens_calib>, <&tsens_calsel>; + nvmem-cell-names = "calib", "calib_sel"; + + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + - | #include // Example 1 (legacy: for pre v1 IP): From patchwork Fri Jul 10 19:45:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657333 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92D7C14B7 for ; Fri, 10 Jul 2020 19:46:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 700E12078D for ; Fri, 10 Jul 2020 19:46:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="qJDGtpsH" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728612AbgGJTqc (ORCPT ); Fri, 10 Jul 2020 15:46:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728552AbgGJTqP (ORCPT ); Fri, 10 Jul 2020 15:46:15 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A852CC08C5DC; Fri, 10 Jul 2020 12:46:14 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id l12so7289259ejn.10; Fri, 10 Jul 2020 12:46:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rujU6IuUKyP/qpmu9fxGZQc5R/2dPvNSFc6+rG5kang=; b=qJDGtpsHkdF9sdjuRhmodvwWZCOnF/D1iW+KcIZ/G97kQcWxAUQQ6FbvdntbcDppxg QUKHOa76nVuncDuqQcgWKPTxbUlb7Bk3O3GhflzbvUwBV63zB/YTG9h1u8ytcU2BJ7Gv +i82XsE3idK3Pktog5jKIn5N5WshSqztxzNAiKsk0doleC2LQ0iy1yQw57NEIkkrmWVT 6nNPTzBxNELQTiZFRWKgo6xpGrLSqeIJlGyN2ewsYGs0SodHmeTbT9pFR+0CxQJgAi2t y5OprsIyFf3nNHHOROXcykdQ+4z8OVtJv7QiQniDCINtTVHDJVIf1RYb+evkYtvKCNfw 50sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rujU6IuUKyP/qpmu9fxGZQc5R/2dPvNSFc6+rG5kang=; b=pvtN+H7NrIUSyzH66/s8JxxA2vjC/Uq4SW8QUEHFjNMYHZz59owe1qUmGo+QZrdx7x 79CObwlpw0+rik77+/XqeqcwGSbrCkbWENxIXrp0p3GTORJSTYnLin4/ObCdv02x2xNt qdeaXjqUf3ibkw5cpxswjQhkuAhwto74vLQ0I/zYGef8DWYEnMinZ9BZ+rx6A7BySfbB IMXlp3YAOhQjDsJFBduCLBNb6a8zaQIccxk6leziwcxZtf7tfBIFLOy5ZZ0tp1UCnNTp bLSIs1RJ8bpD4YCfNbgcDq3P7kdZ3CSQhjZY4nkYNq8aJLXKf8SIZY96BGA8DFdgfLzW puBw== X-Gm-Message-State: AOAM530r57EbeM/a3OGXS3Xe1UhhddHz50Br1reGY/k1EmqoD0Gryq8t teIh0cr1v8My1Ip5GBndtaY= X-Google-Smtp-Source: ABdhPJw5qRU7e8mITfuQa57XmZonNT5IJKsE4n9E5ekJ0sXeJmzLfE0zkbCSHn8UIocnjMHE08uXuw== X-Received: by 2002:a17:906:f20d:: with SMTP id gt13mr38231087ejb.117.1594410373307; Fri, 10 Jul 2020 12:46:13 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:12 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] drivers: thermal: tsens: add interrupt support for 9860 driver Date: Fri, 10 Jul 2020 21:45:55 +0200 Message-Id: <20200710194558.26487-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interrupt support for 9860 tsens driver used to set thermal trip point for the system. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 196 +++++++++++++++++++++++++++--- drivers/thermal/qcom/tsens.h | 1 + 2 files changed, 183 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 890baf1b5542..2dc670206896 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "tsens.h" @@ -27,7 +28,6 @@ /* CNTL_ADDR bitmasks */ #define EN BIT(0) #define SW_RST BIT(1) -#define SENSOR0_EN BIT(3) #define SLP_CLK_ENA BIT(26) #define SLP_CLK_ENA_8660 BIT(24) #define MEASURE_PERIOD 1 @@ -41,14 +41,26 @@ #define THRESHOLD_ADDR 0x3624 /* THRESHOLD_ADDR bitmasks */ +#define THRESHOLD_MAX_CODE 0x20000 +#define THRESHOLD_MIN_CODE 0 #define THRESHOLD_MAX_LIMIT_SHIFT 24 #define THRESHOLD_MIN_LIMIT_SHIFT 16 #define THRESHOLD_UPPER_LIMIT_SHIFT 8 #define THRESHOLD_LOWER_LIMIT_SHIFT 0 +#define THRESHOLD_MAX_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MAX_LIMIT_SHIFT) +#define THRESHOLD_MIN_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_MIN_LIMIT_SHIFT) +#define THRESHOLD_UPPER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_UPPER_LIMIT_SHIFT) +#define THRESHOLD_LOWER_LIMIT_MASK (THRESHOLD_MAX_CODE << \ + THRESHOLD_LOWER_LIMIT_SHIFT) /* Initial temperature threshold values */ -#define LOWER_LIMIT_TH 0x50 -#define UPPER_LIMIT_TH 0xdf +#define LOWER_LIMIT_TH_8960 0x50 +#define UPPER_LIMIT_TH_8960 0xdf +#define LOWER_LIMIT_TH_8064 0x9d /* 95C */ +#define UPPER_LIMIT_TH_8064 0xa6 /* 105C */ #define MIN_LIMIT_TH 0x0 #define MAX_LIMIT_TH 0xff @@ -57,6 +69,169 @@ #define TRDY_MASK BIT(7) #define TIMEOUT_US 100 +#define TSENS_EN BIT(0) +#define TSENS_SW_RST BIT(1) +#define TSENS_ADC_CLK_SEL BIT(2) +#define SENSOR0_EN BIT(3) +#define SENSOR1_EN BIT(4) +#define SENSOR2_EN BIT(5) +#define SENSOR3_EN BIT(6) +#define SENSOR4_EN BIT(7) +#define SENSORS_EN (SENSOR0_EN | SENSOR1_EN | \ + SENSOR2_EN | SENSOR3_EN | SENSOR4_EN) +#define TSENS_8064_SENSOR5_EN BIT(8) +#define TSENS_8064_SENSOR6_EN BIT(9) +#define TSENS_8064_SENSOR7_EN BIT(10) +#define TSENS_8064_SENSOR8_EN BIT(11) +#define TSENS_8064_SENSOR9_EN BIT(12) +#define TSENS_8064_SENSOR10_EN BIT(13) +#define TSENS_8064_SENSORS_EN (SENSORS_EN | \ + TSENS_8064_SENSOR5_EN | \ + TSENS_8064_SENSOR6_EN | \ + TSENS_8064_SENSOR7_EN | \ + TSENS_8064_SENSOR8_EN | \ + TSENS_8064_SENSOR9_EN | \ + TSENS_8064_SENSOR10_EN) + +u32 tsens_8960_slope[] = { + 1176, 1176, 1154, 1176, + 1111, 1132, 1132, 1199, + 1132, 1199, 1132 + }; + +/* Temperature on y axis and ADC-code on x-axis */ +static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return adc_code * slope + offset; +} + +static void notify_uspace_tsens_fn(struct work_struct *work) +{ + struct tsens_sensor *s = container_of(work, struct tsens_sensor, + notify_work); + + sysfs_notify(&s->tzd->device.kobj, NULL, "type"); +} + +static void tsens_scheduler_fn(struct work_struct *work) +{ + struct tsens_priv *priv = + container_of(work, struct tsens_priv, tsens_work); + unsigned int threshold, threshold_low, code, reg, sensor, mask; + bool upper_th_x, lower_th_x; + int ret; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + reg = reg | LOWER_STATUS_CLR | UPPER_STATUS_CLR; + ret = regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg); + if (ret) + return; + + mask = ~(LOWER_STATUS_CLR | UPPER_STATUS_CLR); + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, &threshold); + if (ret) + return; + threshold_low = (threshold & THRESHOLD_LOWER_LIMIT_MASK) >> + THRESHOLD_LOWER_LIMIT_SHIFT; + threshold = (threshold & THRESHOLD_UPPER_LIMIT_MASK) >> + THRESHOLD_UPPER_LIMIT_SHIFT; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®); + if (ret) + return; + + ret = regmap_read(priv->tm_map, CNTL_ADDR, &sensor); + if (ret) + return; + sensor &= (uint32_t)TSENS_8064_SENSORS_EN; + sensor >>= SENSOR0_SHIFT; + + /* Constraint: There is only 1 interrupt control register for all + * 11 temperature sensor. So monitoring more than 1 sensor based + * on interrupts will yield inconsistent result. To overcome this + * issue we will monitor only sensor 0 which is the master sensor. + */ + + /* Skip if the sensor is disabled */ + if (sensor & 1) { + ret = regmap_read(priv->tm_map, priv->sensor[0].status, &code); + if (ret) + return; + upper_th_x = code >= threshold; + lower_th_x = code <= threshold_low; + if (upper_th_x) + mask |= UPPER_STATUS_CLR; + if (lower_th_x) + mask |= LOWER_STATUS_CLR; + if (upper_th_x || lower_th_x) { + /* Notify user space */ + schedule_work(&priv->sensor[0].notify_work); + pr_debug("Trigger (%d degrees) for sensor %d\n", + code_to_mdegC(code, &priv->sensor[0]), 0); + } + } + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg & mask); +} + +static irqreturn_t tsens_isr(int irq, void *data) +{ + struct tsens_priv *priv = data; + + schedule_work(&priv->tsens_work); + return IRQ_HANDLED; +} + +static void hw_init(struct tsens_priv *priv) +{ + int ret; + unsigned int reg_cntl = 0, reg_cfg = 0, reg_thr = 0; + unsigned int reg_status_cntl = 0; + + regmap_read(priv->tm_map, CNTL_ADDR, ®_cntl); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl | TSENS_SW_RST); + + reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18) | + (((1 << priv->num_sensors) - 1) << SENSOR0_SHIFT); + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_status_cntl); + reg_status_cntl |= LOWER_STATUS_CLR | UPPER_STATUS_CLR | + MIN_STATUS_MASK | MAX_STATUS_MASK; + regmap_write(priv->tm_map, STATUS_CNTL_ADDR_8064, reg_status_cntl); + reg_cntl |= TSENS_EN; + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + + regmap_read(priv->tm_map, CONFIG_ADDR, ®_cfg); + if (priv->num_sensors > 1) + reg_cfg = (reg_cfg & ~CONFIG_MASK) | CONFIG; + else + reg_cfg = (reg_cfg & ~CONFIG_MASK) | + (CONFIG << CONFIG_SHIFT_8660); + regmap_write(priv->tm_map, CONFIG_ADDR, reg_cfg); + + reg_thr |= (LOWER_LIMIT_TH_8064 << THRESHOLD_LOWER_LIMIT_SHIFT) | + (UPPER_LIMIT_TH_8064 << THRESHOLD_UPPER_LIMIT_SHIFT) | + (MIN_LIMIT_TH << THRESHOLD_MIN_LIMIT_SHIFT) | + (MAX_LIMIT_TH << THRESHOLD_MAX_LIMIT_SHIFT); + + regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_thr); + + ret = devm_request_irq(priv->dev, priv->tsens_irq, tsens_isr, + IRQF_TRIGGER_RISING, "tsens_interrupt", priv); + if (ret < 0) { + dev_err(priv->dev, "request_irq FAIL: %d", ret); + return; + } + + INIT_WORK(&priv->tsens_work, tsens_scheduler_fn); +} + static int suspend_8960(struct tsens_priv *priv) { int ret; @@ -186,6 +361,8 @@ static int init_8960(struct tsens_priv *priv) if (i >= 5) priv->sensor[i].status = S0_STATUS_ADDR + 40; priv->sensor[i].status += i * 4; + priv->sensor[i].slope = tsens_8960_slope[i]; + INIT_WORK(&priv->sensor[i].notify_work, notify_uspace_tsens_fn); } reg_cntl = SW_RST; @@ -236,18 +413,9 @@ static int calibrate_8960(struct tsens_priv *priv) kfree(data); - return 0; -} - -/* Temperature on y axis and ADC-code on x-axis */ -static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) -{ - int slope, offset; + hw_init(priv); - slope = thermal_zone_get_slope(s->tzd); - offset = CAL_MDEGC - slope * s->offset; - - return adc_code * slope + offset; + return 0; } static int get_temp_8960(const struct tsens_sensor *s, int *temp) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 59d01162c66a..2f145001e4d5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,6 +48,7 @@ enum tsens_irq_type { struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; + struct work_struct notify_work; int offset; unsigned int hw_id; int slope; From patchwork Fri Jul 10 19:45:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657325 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CA5F13BD for ; Fri, 10 Jul 2020 19:46:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 51F352078D for ; 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[87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:14 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] drivers: thermal: tsens: add support for custom set_trip function Date: Fri, 10 Jul 2020 21:45:56 +0200 Message-Id: <20200710194558.26487-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org 8960 tsens driver have a custom implementation to set set_trip function. Permit the generic driver to use the custom function if provided. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens.c | 4 ++++ drivers/thermal/qcom/tsens.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 2985a064a0d1..2b55b34d66fb 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -530,6 +530,10 @@ static int tsens_set_trips(void *_sensor, int low, int high) int high_val, low_val, cl_high, cl_low; u32 hw_id = s->hw_id; + // Use the driver set_trips if present + if (priv->ops->set_trip_temp) + return priv->ops->set_trip_temp(_sensor, low, high); + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", hw_id, __func__, low, high); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 2f145001e4d5..c27fae39d542 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -65,6 +65,7 @@ struct tsens_sensor { * @suspend: Function to suspend the tsens device * @resume: Function to resume the tsens device * @get_trend: Function to get the thermal/temp trend + * @set_trip_temp: Function to get trip temp */ struct tsens_ops { /* mandatory callbacks */ @@ -77,6 +78,7 @@ struct tsens_ops { int (*suspend)(struct tsens_priv *priv); int (*resume)(struct tsens_priv *priv); int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); + int (*set_trip_temp)(void *data, int trip, int temp); }; #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ From patchwork Fri Jul 10 19:45:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 11657319 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F1F5E14B7 for ; Fri, 10 Jul 2020 19:46:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D3982207D0 for ; Fri, 10 Jul 2020 19:46:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FHYMRFQO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728589AbgGJTqU (ORCPT ); Fri, 10 Jul 2020 15:46:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728572AbgGJTqT (ORCPT ); Fri, 10 Jul 2020 15:46:19 -0400 Received: from mail-ej1-x643.google.com (mail-ej1-x643.google.com [IPv6:2a00:1450:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CD61C08E6DC; Fri, 10 Jul 2020 12:46:19 -0700 (PDT) Received: by mail-ej1-x643.google.com with SMTP id l12so7289446ejn.10; Fri, 10 Jul 2020 12:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ItfQ8L/Er3Hk4c2uSxofOAEu4o/bM64EAYLfz2K5ECQ=; b=FHYMRFQOPQBahtYhgz8M1TfOZPMyoiEsVlfldmypxKAHVYOe/DPRNk9hocDMdZBXbL Xp8/QHddPGFWBsp/EzId0hEm/PBFZHHy+SylzYzP0Nm2y+dbCDepU/81bNe3FD/+BrwU q7WxCE+3AT8aLGvvBZvT2bKG6qL0LJwb7Erju6Ox5h98vhLfOLgShWBHscBGOAy53Et3 5stZvE08xLJc0R88/1KtZLrQJpX6MO5g7ZCHzd0SAGOSgz8DvXeRHCQK9KRekyrdXkTh 2hG11a9n7P8CpiQHQg4BVJYidFhgZuHt6GEOuCpwccEU1iOePvwIUsdtWUMn3XQoTMLN cvKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ItfQ8L/Er3Hk4c2uSxofOAEu4o/bM64EAYLfz2K5ECQ=; b=bXk9LklmwWjZ72r4rYNZkd2GHr+p3+reLmSjJPO+R+p84owtwBUaFdnK8RdCG9bkjk fzqRvGdaBGtttzYHXZ1gCDlnDvI+aw/KUNJoPEynTKgd+dhNDvjOvF+DNO0GjiMAglCp LsiQGSboDPPARpCWGYDj9JkJrzvMJoR3w2wjH+maOW8cniJYPJS7inuWJhhzyVV9QBb2 QGhBnEoyQ++ghNCWpMmHjWYTF91KrJRbvn/Rn+sAD2kM/sGm/hhOICf1WtBKXAIwPP1J /81DS4frqkN8c0eU/jjoJASPENZxQWNJcOy1Iw0xgHsvpFqlmNe2HlWF/+F4+1PBw2bN n5uA== X-Gm-Message-State: AOAM53270Hysim7ZJpjlHjSoj8ZPFolHHWKT1F/cKWKNeWDlG95YhwDM 5WLNGuW554SGafeJOyeJDhE= X-Google-Smtp-Source: ABdhPJyegOvV7pWaDXp0wHvfbYv+3ypu27dlyWQ1uNiRjTQ2sOXdeePRRXUtVRAURro7V1LfQcouwQ== X-Received: by 2002:a17:906:b353:: with SMTP id cd19mr55772899ejb.395.1594410377750; Fri, 10 Jul 2020 12:46:17 -0700 (PDT) Received: from Ansuel-XPS.localdomain (host-87-16-250-164.retail.telecomitalia.it. [87.16.250.164]) by smtp.googlemail.com with ESMTPSA id kt4sm4155768ejb.48.2020.07.10.12.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2020 12:46:17 -0700 (PDT) From: Ansuel Smith To: Amit Kucheria Cc: Ansuel Smith , Andy Gross , Bjorn Andersson , Zhang Rui , Daniel Lezcano , Rob Herring , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] drivers: thermal: tsens: add set_trip support for 8960 Date: Fri, 10 Jul 2020 21:45:57 +0200 Message-Id: <20200710194558.26487-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200710194558.26487-1-ansuelsmth@gmail.com> References: <20200710194558.26487-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add custom set_trip function for 8960 needed to set trip point to the tsens driver for 8960 driver. Signed-off-by: Ansuel Smith --- drivers/thermal/qcom/tsens-8960.c | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 2dc670206896..321791b8aabf 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -93,6 +93,15 @@ TSENS_8064_SENSOR9_EN | \ TSENS_8064_SENSOR10_EN) +/* Trips: from very hot to very cold */ +enum tsens_trip_type { + TSENS_TRIP_STAGE3 = 0, + TSENS_TRIP_STAGE2, + TSENS_TRIP_STAGE1, + TSENS_TRIP_STAGE0, + TSENS_TRIP_NUM, +}; + u32 tsens_8960_slope[] = { 1176, 1176, 1154, 1176, 1111, 1132, 1132, 1199, @@ -110,6 +119,16 @@ static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) return adc_code * slope + offset; } +static int mdegC_to_code(int degC, const struct tsens_sensor *s) +{ + int slope, offset; + + slope = thermal_zone_get_slope(s->tzd); + offset = CAL_MDEGC - slope * s->offset; + + return degC / slope - offset; +} + static void notify_uspace_tsens_fn(struct work_struct *work) { struct tsens_sensor *s = container_of(work, struct tsens_sensor, @@ -442,6 +461,64 @@ static int get_temp_8960(const struct tsens_sensor *s, int *temp) return -ETIMEDOUT; } +static int set_trip_temp_ipq8064(void *data, int trip, int temp) +{ + unsigned int reg_th, reg_cntl; + int ret, code, code_chk, hi_code, lo_code; + const struct tsens_sensor *s = data; + struct tsens_priv *priv = s->priv; + + code = mdegC_to_code(temp, s); + code_chk = code; + + if (code < THRESHOLD_MIN_CODE || code > THRESHOLD_MAX_CODE) + return -EINVAL; + + ret = regmap_read(priv->tm_map, STATUS_CNTL_ADDR_8064, ®_cntl); + if (ret) + return ret; + + ret = regmap_read(priv->tm_map, THRESHOLD_ADDR, ®_th); + if (ret) + return ret; + + hi_code = (reg_th & THRESHOLD_UPPER_LIMIT_MASK) + >> THRESHOLD_UPPER_LIMIT_SHIFT; + lo_code = (reg_th & THRESHOLD_LOWER_LIMIT_MASK) + >> THRESHOLD_LOWER_LIMIT_SHIFT; + + switch (trip) { + case TSENS_TRIP_STAGE3: + code <<= THRESHOLD_MAX_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MAX_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE2: + if (code_chk <= lo_code) + return -EINVAL; + code <<= THRESHOLD_UPPER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_UPPER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE1: + if (code_chk >= hi_code) + return -EINVAL; + code <<= THRESHOLD_LOWER_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_LOWER_LIMIT_MASK; + break; + case TSENS_TRIP_STAGE0: + code <<= THRESHOLD_MIN_LIMIT_SHIFT; + reg_th &= ~THRESHOLD_MIN_LIMIT_MASK; + break; + default: + return -EINVAL; + } + + ret = regmap_write(priv->tm_map, THRESHOLD_ADDR, reg_th | code); + if (ret) + return ret; + + return 0; +} + static const struct tsens_ops ops_8960 = { .init = init_8960, .calibrate = calibrate_8960, @@ -450,6 +527,7 @@ static const struct tsens_ops ops_8960 = { .disable = disable_8960, .suspend = suspend_8960, .resume = resume_8960, + .set_trip_temp = set_trip_temp_ipq8064, }; struct tsens_plat_data data_8960 = {