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Sun, 12 Jul 2020 17:25:17 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, s.hauer@pengutronix.de Subject: [PATCH v1 1/5] ARM: mach-imx6q: do not select enet PTP clock source on QuadPlus Date: Sun, 12 Jul 2020 20:25:08 -0400 Message-Id: <20200713002512.28742-2-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713002512.28742-1-TheSven73@gmail.com> References: <20200713002512.28742-1-TheSven73@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200712_202521_660807_7677DBD1 X-CRM114-Status: GOOD ( 13.38 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:842 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On QuadPlus, the enet PTP clock source is selected via the clocktree. Therefore it should not be set in the machine layer (mach-imx6q). Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc4 To: Shawn Guo To: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org arch/arm/mach-imx/mach-imx6q.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..fcf211492f6f 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -169,6 +169,10 @@ static void __init imx6q_1588_init(void) struct regmap *gpr; u32 clksel; + /* QuadPlus selects PTP clock source via clocktree */ + if (of_machine_is_compatible("fsl,imx6qp")) + return; + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (!np) { pr_warn("%s: failed to find fec node\n", __func__); From patchwork Mon Jul 13 00:25:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Van Asbroeck X-Patchwork-Id: 11658473 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0133617C5 for ; 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Sun, 12 Jul 2020 17:25:18 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id u5sm17044309qke.32.2020.07.12.17.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2020 17:25:18 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, s.hauer@pengutronix.de Subject: [PATCH v1 2/5] clk: imx: add simple regmap-backed clock mux Date: Sun, 12 Jul 2020 20:25:09 -0400 Message-Id: <20200713002512.28742-3-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713002512.28742-1-TheSven73@gmail.com> References: <20200713002512.28742-1-TheSven73@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200712_202520_733862_29677151 X-CRM114-Status: GOOD ( 21.59 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:844 listed in] [list.dnswl.org] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On the imx6 QuadPlus, some clocktree muxes have control bits located in the GPR area. This area is already modelled as a syscon regmap. To control these muxes, add a simple regmap-backed clock mux. Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc4 To: Shawn Guo To: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-mux-regmap.c | 110 +++++++++++++++++++++++++++++++ drivers/clk/imx/clk.h | 7 ++ 3 files changed, 118 insertions(+) create mode 100644 drivers/clk/imx/clk-mux-regmap.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 928f874c73d2..3d36740c1efd 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MXC_CLK) += \ clk-pllv3.o \ clk-pllv4.o \ clk-sscg-pll.o \ + clk-mux-regmap.o \ clk-pll14xx.o obj-$(CONFIG_MXC_CLK_SCU) += \ diff --git a/drivers/clk/imx/clk-mux-regmap.c b/drivers/clk/imx/clk-mux-regmap.c new file mode 100644 index 000000000000..ba5fde525999 --- /dev/null +++ b/drivers/clk/imx/clk-mux-regmap.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Sven Van Asbroeck + * + * Simple clock multiplexer, backed by a regmap + */ + +#include +#include +#include + +#include "clk.h" + +struct clk_mux_regmap { + struct clk_hw hw; + struct regmap *regmap; + unsigned int reg; + u8 shift; + u32 mask; +}; + +#define to_clk_mux_regmap(_hw) container_of(_hw, struct clk_mux_regmap, hw) + +static u8 clk_regmap_read_index(struct clk_mux_regmap *clk) +{ + unsigned int val; + + if (regmap_read(clk->regmap, clk->reg, &val)) + return 0; + + val >>= clk->shift; + val &= clk->mask; + + return (u8)val; +} + +static u8 clk_mux_regmap_get_parent(struct clk_hw *hw) +{ + struct clk_mux_regmap *clk = to_clk_mux_regmap(hw); + + return clk_regmap_read_index(clk); +} + +static int clk_mux_regmap_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_mux_regmap *clk = to_clk_mux_regmap(hw); + + return regmap_update_bits(clk->regmap, clk->reg, + clk->mask << clk->shift, + (unsigned int)index << clk->shift); +} + +static int clk_mux_regmap_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_mux_regmap *clk = to_clk_mux_regmap(hw); + struct clk_hw *parent; + u8 index; + + index = clk_regmap_read_index(clk); + parent = clk_hw_get_parent_by_index(hw, index); + if (!parent) + return -EINVAL; + req->rate = clk_hw_get_rate(parent); + + return 0; +} + +static const struct clk_ops clk_mux_regmap_ops = { + .get_parent = clk_mux_regmap_get_parent, + .set_parent = clk_mux_regmap_set_parent, + .determine_rate = clk_mux_regmap_determine_rate, +}; + +struct clk_hw * +imx_clk_hw_mux_regmap(const char *name, struct regmap *regmap, unsigned int reg, + u8 shift, u8 width, const char * const *parent_names, + int num_parents) +{ + struct clk_mux_regmap *clk_regmap; + struct clk_init_data init = {}; + struct clk_hw *hw; + int ret; + + if (num_parents > (1 << width)) + return ERR_PTR(-EINVAL); + + clk_regmap = kzalloc(sizeof(*clk_regmap), GFP_KERNEL); + if (!clk_regmap) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.parent_names = parent_names; + init.num_parents = num_parents; + init.ops = &clk_mux_regmap_ops; + clk_regmap->regmap = regmap; + clk_regmap->reg = reg; + clk_regmap->shift = shift; + clk_regmap->mask = BIT(width) - 1; + clk_regmap->hw.init = &init; + + hw = &clk_regmap->hw; + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(clk_regmap); + hw = ERR_PTR(ret); + } + + return hw; +} diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 16adbc34e05f..4df766abbe16 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -5,6 +5,8 @@ #include #include +struct regmap; + #define IMX_CLK_GATE2_SINGLE_BIT 1 extern spinlock_t imx_ccm_lock; @@ -447,6 +449,11 @@ static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev, reg, shift, width, 0, &imx_ccm_lock); } +struct clk_hw * +imx_clk_hw_mux_regmap(const char *name, struct regmap *regmap, unsigned int reg, + u8 shift, u8 width, const char * const *parent_names, + int num_parents); + static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents) From patchwork Mon Jul 13 00:25:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sven Van Asbroeck X-Patchwork-Id: 11658479 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1EC1960D for ; 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Sun, 12 Jul 2020 17:25:19 -0700 (PDT) Received: from localhost.localdomain ([72.53.229.195]) by smtp.gmail.com with ESMTPSA id u5sm17044309qke.32.2020.07.12.17.25.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2020 17:25:19 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, s.hauer@pengutronix.de Subject: [PATCH v1 3/5] dt-bindings: imx6qdl-clock: add QuadPlus enet clocks Date: Sun, 12 Jul 2020 20:25:10 -0400 Message-Id: <20200713002512.28742-4-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713002512.28742-1-TheSven73@gmail.com> References: <20200713002512.28742-1-TheSven73@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200712_202521_669280_260BF4C0 X-CRM114-Status: GOOD ( 12.78 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:844 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On the QuadPlus, hardware designers have improved the enet clocking. Add these QuadPlus-specific clocks to the dt-bindings. Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc4 To: Shawn Guo To: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Documentation/devicetree/bindings/clock/imx6q-clock.yaml | 2 ++ include/dt-bindings/clock/imx6qdl-clock.h | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml index 92a8e545e212..ecd28403eeff 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.yaml @@ -34,6 +34,7 @@ properties: - description: ckih1 clock input - description: anaclk1 clock input - description: anaclk2 clock input + - description: anaclk3 clock input clock-names: items: @@ -42,6 +43,7 @@ properties: - const: ckih1 - const: anaclk1 - const: anaclk2 + - const: anaclk3 fsl,pmic-stby-poweroff: $ref: /schemas/types.yaml#/definitions/flag diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index e20c43cc36f6..afc6b7b1e3e6 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -273,6 +273,9 @@ #define IMX6QDL_CLK_MMDC_P0_IPG 263 #define IMX6QDL_CLK_DCIC1 264 #define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 +#define IMX6QDL_CLK_ENET_PAD 266 +#define IMX6QDL_CLK_ENET_PTP 267 +#define IMX6QDL_CLK_ANACLK3 268 +#define IMX6QDL_CLK_END 269 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ From patchwork Mon Jul 13 00:25:11 2020 Content-Type: text/plain; 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Sun, 12 Jul 2020 17:25:20 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, s.hauer@pengutronix.de Subject: [PATCH v1 4/5] clk: imx6q: support improved enet clocking on QuadPlus Date: Sun, 12 Jul 2020 20:25:11 -0400 Message-Id: <20200713002512.28742-5-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713002512.28742-1-TheSven73@gmail.com> References: <20200713002512.28742-1-TheSven73@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200712_202522_538321_D221095E X-CRM114-Status: GOOD ( 20.13 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:842 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On the imx6q QuadPlus, hardware designers have improved the enet clocking: _ anaclk3---------| \ | | _ |M |--enet_pad-->| \ | | | | enet_ref---o--->|_/ |M |----enet_ptp | | | o---------------------|_/ Where anaclk3 is an external clock fed into the imx6q via a pad, typically RGMII_TX_CTL or GPIO_16, when these are configured in mux mode ENET_REF_CLK. Board designers can now change the clock tree (via the devicetree) to choose between all three supported enet clocking methods. See follow-up devicetree patch for details. Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc4 To: Shawn Guo To: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org drivers/clk/imx/clk-imx6q.c | 46 +++++++++++++++++++++ include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 + 2 files changed, 47 insertions(+) diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index ba33c79158de..0edffa306a28 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include "clk.h" @@ -87,6 +89,8 @@ static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; +static const char * const enet_pad_sels[] = { "anaclk3", "enet_ref", }; +static const char * const enet_ptp_sels[] = { "enet_pad", "enet_ref", }; static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; @@ -436,6 +440,7 @@ static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np, static void __init imx6q_clocks_init(struct device_node *ccm_node) { + struct regmap *gpr; struct device_node *np; void __iomem *anatop_base, *base; int ret; @@ -464,6 +469,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) WARN_ON(!base); of_node_put(np); + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + WARN_ON(IS_ERR_OR_NULL(gpr)); + /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { post_div_table[1].div = 1; @@ -959,6 +967,44 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* Audio-related clocks configuration */ clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); + /* + * The QuadPlus has improved enet clocking: + * _ + * anaclk3---------| \ + * | | _ + * |M |--enet_pad-->| \ + * | | | | + * enet_ref---o--->|_/ |M |----enet_ptp + * | | | + * o---------------------|_/ + * + * On the plus, three options to generate the enet ptp clock: + * + * a) route enet_ref externally from pad to pad (the default): + * enet_ptp from enet_pad + * enet_pad from enet_ref + * b) route internally on SoC from enet_ref: + * enet_ptp from enet_ref + * c) route external clock (from PHY or oscillator) via pad: + * enet_ptp from enet_pad + * enet_pad from anaclk3 + * anaclk3 from PHY or oscillator, add devicetree node + */ + if (clk_on_imx6qp()) { + /* + * anaclk3: clock source from external clock via: + * - RGMII_TX_CTL PAD (mux mode ENET_REF_CLK), or + * - GPIO_16 PAD (mux mode ENET_REF_CLK) + */ + hws[IMX6QDL_CLK_ANACLK3] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk3", 0); + hws[IMX6QDL_CLK_ENET_PAD] = imx_clk_hw_mux_regmap("enet_pad", gpr, IOMUXC_GPR1, ffs(IMX6Q_GPR1_ENET_CLK_SEL_MASK) - 1, + 1, enet_pad_sels, ARRAY_SIZE(enet_pad_sels)); + hws[IMX6QDL_CLK_ENET_PTP] = imx_clk_hw_mux_regmap("enet_ptp", gpr, IOMUXC_GPR5, ffs(IMX6Q_GPR5_ENET_TXCLK_SEL_MASK) - 1, + 1, enet_ptp_sels, ARRAY_SIZE(enet_ptp_sels)); + clk_set_parent(hws[IMX6QDL_CLK_ENET_PAD]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk); + clk_set_parent(hws[IMX6QDL_CLK_ENET_PTP]->clk, hws[IMX6QDL_CLK_ENET_PAD]->clk); + } + /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk); diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..ac1bb3695933 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -240,6 +240,7 @@ #define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) +#define IMX6Q_GPR5_ENET_TXCLK_SEL_MASK BIT(9) #define IMX6Q_GPR5_SATA_SW_PD BIT(10) #define IMX6Q_GPR5_SATA_SW_RST BIT(11) From patchwork Mon Jul 13 00:25:12 2020 Content-Type: text/plain; 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Sun, 12 Jul 2020 17:25:21 -0700 (PDT) From: Sven Van Asbroeck X-Google-Original-From: Sven Van Asbroeck To: shawnguo@kernel.org, s.hauer@pengutronix.de Subject: [PATCH v1 5/5] ARM: dts: imx6qp: support improved enet clocking on QuadPlus Date: Sun, 12 Jul 2020 20:25:12 -0400 Message-Id: <20200713002512.28742-6-TheSven73@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200713002512.28742-1-TheSven73@gmail.com> References: <20200713002512.28742-1-TheSven73@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200712_202523_962077_73FBD534 X-CRM114-Status: GOOD ( 13.23 ) X-Spam-Score: 0.1 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:841 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider [thesven73[at]gmail.com] 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit [thesven73[at]gmail.com] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Board designers are now able to choose between all three supported enet clocking methods, by changing the clocktree via the devicetree: a) route enet_ref externally from pad to pad (the default): no clock tree changes required b) route internally on SoC from enet_ref &fec { assigned-clocks = <&clks IMX6QDL_CLK_ENET_PTP>, <&clks IMX6QDL_CLK_ENET_REF>; assigned-clock-parents = <&clks IMX6QDL_CLK_ENET_REF>; assigned-clock-rates = <0>, <125000000>; }; c) route external clock (from PHY or oscillator) via pad / { clocks { phy_osc: anaclk3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; }; }; &fec { assigned-clocks = <&clks IMX6QDL_CLK_ENET_PTP>, <&clks IMX6QDL_CLK_ENET_PAD>; assigned-clock-parents = <&clks IMX6QDL_CLK_ENET_PAD>, <&clks IMX6QDL_CLK_ANACLK3>; }; Signed-off-by: Sven Van Asbroeck --- Tree: v5.8-rc4 To: Shawn Guo To: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org arch/arm/boot/dts/imx6qp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index b310f13a53f2..7f81d35f56c9 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -79,6 +79,9 @@ &fec { interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, <0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_PTP>; }; &gpc {