From patchwork Tue Jul 14 01:27:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11661303 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D902D913 for ; Tue, 14 Jul 2020 01:50:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BEA7B2186A for ; Tue, 14 Jul 2020 01:50:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BEA7B2186A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D52BB6E870; Tue, 14 Jul 2020 01:50:50 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id E0D116E86F; Tue, 14 Jul 2020 01:50:48 +0000 (UTC) IronPort-SDR: EhFCygawjTxnbSmujQ8c04vIJaqiYn3bcZtrBBJ1UEbEOEl0usc6zYOlyQBv0gsamlfo9JwMPg vrrl8ci+7Axg== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="136245058" X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="136245058" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 18:50:48 -0700 IronPort-SDR: UW+6cfd7MEyykSdkF9xRZgoLPbLPSedNMmJDIjzy106MTJAEa9QfmU3Uaq2rvJuZpv87eVn7jH 36+YqkUF+IKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="307680190" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by fmsmga004.fm.intel.com with ESMTP; 13 Jul 2020 18:50:45 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 1/5] drm/i915: Add enable/disable flip done and flip done handler Date: Tue, 14 Jul 2020 06:57:21 +0530 Message-Id: <20200714012725.18383-2-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200714012725.18383-1-karthik.b.s@intel.com> References: <20200714012725.18383-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add enable/disable flip done functions and the flip done handler function which handles the flip done interrupt. Enable the flip done interrupt in IER. Enable flip done function is called before writing the surface address register as the write to this register triggers the flip done interrupt Flip done handler is used to send the page flip event as soon as the surface address is written as per the requirement of async flips. The interrupt is disabled after the event is sent. v2: -Change function name from icl_* to skl_* (Paulo) -Move flip handler to this patch (Paulo) -Remove vblank_put() (Paulo) -Enable flip done interrupt for gen9+ only (Paulo) -Enable flip done interrupt in power_well_post_enable hook (Paulo) -Removed the event check in flip done handler to handle async flips without pageflip events. v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) -Make the pending vblank event NULL in the begining of flip_done_handler to remove sporadic WARN_ON that is seen. v4: -Calculate timestamps using flip done time stamp and current timestamp for async flips (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni Reported-by: kernel test robot Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++ drivers/gpu/drm/i915/i915_irq.c | 83 ++++++++++++++++++-- drivers/gpu/drm/i915/i915_irq.h | 2 + drivers/gpu/drm/i915/i915_reg.h | 4 +- 4 files changed, 91 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 729ec6e0d43a..d2c04770dd6a 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -15552,6 +15552,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_dbuf_pre_plane_update(state); + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) { + skl_enable_flip_done(&crtc->base); + break; + } + } + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); @@ -15573,6 +15580,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) drm_atomic_helper_wait_for_flip_done(dev, &state->base); for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + skl_disable_flip_done(&crtc->base); + if (new_crtc_state->hw.active && !needs_modeset(new_crtc_state) && !new_crtc_state->preload_luts && diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 562b43ed077f..9812a8051c5e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -697,14 +697,24 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; } +u32 g4x_get_flip_counter(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + return I915_READ(PIPE_FLIPCOUNT_G4X(pipe)); +} + u32 g4x_get_vblank_counter(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); enum pipe pipe = to_intel_crtc(crtc)->pipe; + if (crtc->state->async_flip) + return g4x_get_flip_counter(crtc); + return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); } - /* * On certain encoders on certain platforms, pipe * scanline register will not work to get the scanline, @@ -737,17 +747,24 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) * pipe frame time stamp. The time stamp value * is sampled at every start of vertical blank. */ - scan_prev_time = intel_de_read_fw(dev_priv, - PIPE_FRMTMSTMP(crtc->pipe)); - + if (!crtc->config->uapi.async_flip) + scan_prev_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); + else + scan_prev_time = intel_de_read_fw(dev_priv, + PIPE_FLIPTMSTMP(crtc->pipe)); /* * The TIMESTAMP_CTR register has the current * time stamp value. */ scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); - scan_post_time = intel_de_read_fw(dev_priv, - PIPE_FRMTMSTMP(crtc->pipe)); + if (!crtc->config->uapi.async_flip) + scan_post_time = intel_de_read_fw(dev_priv, + PIPE_FRMTMSTMP(crtc->pipe)); + else + scan_post_time = intel_de_read_fw(dev_priv, + PIPE_FLIPTMSTMP(crtc->pipe)); } while (scan_post_time != scan_prev_time); scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, @@ -937,7 +954,6 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, *vpos = position / htotal; *hpos = position - (*vpos * htotal); } - return true; } @@ -1295,6 +1311,24 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 crc4) {} #endif +static void flip_done_handler(struct drm_i915_private *dev_priv, + unsigned int pipe) +{ + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + struct drm_crtc_state *crtc_state = crtc->base.state; + struct drm_pending_vblank_event *e = crtc_state->event; + struct drm_device *dev = &dev_priv->drm; + unsigned long irqflags; + + crtc_state->event = NULL; + + drm_crtc_accurate_vblank_count(&crtc->base); + spin_lock_irqsave(&dev->event_lock, irqflags); + + drm_crtc_send_vblank_event(&crtc->base, e); + + spin_unlock_irqrestore(&dev->event_lock, irqflags); +} static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -2389,6 +2423,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_VBLANK) intel_handle_vblank(dev_priv, pipe); + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE) + flip_done_handler(dev_priv, pipe); + if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe); @@ -2670,6 +2707,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc) return 0; } +void skl_enable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ @@ -2730,6 +2780,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } +void skl_disable_flip_done(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->dev); + enum pipe pipe = to_intel_crtc(crtc)->pipe; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->irq_lock, irqflags); + + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE); + + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); +} + static void ibx_irq_reset(struct drm_i915_private *dev_priv) { struct intel_uncore *uncore = &dev_priv->uncore; @@ -2937,6 +3000,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; enum pipe pipe; + if (INTEL_GEN(dev_priv) >= 9) + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE; + spin_lock_irq(&dev_priv->irq_lock); if (!intel_irqs_enabled(dev_priv)) { @@ -3414,6 +3480,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; + if (INTEL_GEN(dev_priv) >= 9) + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE; + de_port_enables = de_port_masked; if (IS_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h index 25f25cd95818..2f10c8135116 100644 --- a/drivers/gpu/drm/i915/i915_irq.h +++ b/drivers/gpu/drm/i915/i915_irq.h @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc); int i965_enable_vblank(struct drm_crtc *crtc); int ilk_enable_vblank(struct drm_crtc *crtc); int bdw_enable_vblank(struct drm_crtc *crtc); +void skl_enable_flip_done(struct drm_crtc *crtc); void i8xx_disable_vblank(struct drm_crtc *crtc); void i915gm_disable_vblank(struct drm_crtc *crtc); void i965_disable_vblank(struct drm_crtc *crtc); void ilk_disable_vblank(struct drm_crtc *crtc); void bdw_disable_vblank(struct drm_crtc *crtc); +void skl_disable_flip_done(struct drm_crtc *crtc); void gen2_irq_reset(struct intel_uncore *uncore); void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 86a23ced051b..3c4480172e84 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -11113,9 +11113,11 @@ enum skl_power_gate { #define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) #define _PIPE_FRMTMSTMP_A 0x70048 +#define _PIPE_FLIPTMSTMP_A 0x7004C #define PIPE_FRMTMSTMP(pipe) \ _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A) - +#define PIPE_FLIPTMSTMP(pipe) \ + _MMIO_PIPE2(pipe, _PIPE_FLIPTMSTMP_A) /* BXT MIPI clock controls */ #define BXT_MAX_VAR_OUTPUT_KHZ 39500 From patchwork Tue Jul 14 01:27:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11661307 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ED6DF913 for ; Tue, 14 Jul 2020 01:50:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D46522186A for ; Tue, 14 Jul 2020 01:50:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D46522186A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A14296E872; Tue, 14 Jul 2020 01:50:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F2DD6E86F; Tue, 14 Jul 2020 01:50:52 +0000 (UTC) IronPort-SDR: DbKPap4oapn3C3GcJyzRD2FYsDt9nm5PmZ2nVkSACpjLSTKwTMfRYGv5AUIp2/AG2sOTIxrcFw jiZuIFJg9skw== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="136245068" X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="136245068" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 18:50:51 -0700 IronPort-SDR: 5GYEK13dXAcw+t+BmCQHF6fSEnWNBaiZsE+jziB8wPQ0y1/x+JxnwMsm2KDpROwgcfN+GIAKFs N4ccjTZjZOfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="307680195" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by fmsmga004.fm.intel.com with ESMTP; 13 Jul 2020 18:50:48 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 2/5] drm/i915: Add support for async flips in I915 Date: Tue, 14 Jul 2020 06:57:22 +0530 Message-Id: <20200714012725.18383-3-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200714012725.18383-1-karthik.b.s@intel.com> References: <20200714012725.18383-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Set the Async Address Update Enable bit in plane ctl when async flip is requested. v2: -Move the Async flip enablement to individual patch (Paulo) v3: -Rebased. v4: -Add separate plane hook for async flip case (Ville) Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++ drivers/gpu/drm/i915/display/intel_sprite.c | 25 ++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d2c04770dd6a..aa0eebeca7ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4765,6 +4765,12 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; u32 plane_ctl; + /* During Async flip, no other updates are allowed */ + if (crtc_state->uapi.async_flip) { + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + return plane_ctl; + } + plane_ctl = PLANE_CTL_ENABLE; if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index d03860fef2d7..7cffdb48e6df 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -603,6 +603,24 @@ icl_program_input_csc(struct intel_plane *plane, PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } +static void +skl_program_async_surface_address(struct drm_i915_private *dev_priv, + const struct intel_plane_state *plane_state, + enum pipe pipe, enum plane_id plane_id, + u32 surf_addr) +{ + unsigned long irqflags; + u32 plane_ctl = plane_state->ctl; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + static void skl_program_plane(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, @@ -631,6 +649,13 @@ skl_program_plane(struct intel_plane *plane, u32 keymsk, keymax; u32 plane_ctl = plane_state->ctl; + /* During Async flip, no other updates are allowed */ + if (crtc_state->uapi.async_flip) { + skl_program_async_surface_address(dev_priv, plane_state, + pipe, plane_id, surf_addr); + return; + } + plane_ctl |= skl_plane_ctl_crtc(crtc_state); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3c4480172e84..879aaeaf093a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6916,6 +6916,7 @@ enum { #define PLANE_CTL_TILED_X (1 << 10) #define PLANE_CTL_TILED_Y (4 << 10) #define PLANE_CTL_TILED_YF (5 << 10) +#define PLANE_CTL_ASYNC_FLIP (1 << 9) #define PLANE_CTL_FLIP_HORIZONTAL (1 << 8) #define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */ #define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */ From patchwork Tue Jul 14 01:27:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11661311 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADB05138C for ; Tue, 14 Jul 2020 01:50:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 94EA121D79 for ; Tue, 14 Jul 2020 01:50:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 94EA121D79 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C6A3C6E874; Tue, 14 Jul 2020 01:50:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 46E8F6E873; Tue, 14 Jul 2020 01:50:55 +0000 (UTC) IronPort-SDR: zaaQNxBj3uAMuka4mi0xS3+kH+Nx6V/sGp6d44ycYZYs/9hZbl1FncPoC9xMlCygseYbR08NZB ftVCvAVeZ//Q== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="136245077" X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="136245077" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 18:50:54 -0700 IronPort-SDR: wQ2jZzw83e5L1JPM09BLdwZSuLvtCA/bO4+Px/sfU2YIE9FY2Z3Q/7mkL0Uw5Ij0PSRnjXEr8N tRohT3bzWiiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="307680234" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by fmsmga004.fm.intel.com with ESMTP; 13 Jul 2020 18:50:52 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 3/5] drm/i915: Add checks specific to async flips Date: Tue, 14 Jul 2020 06:57:23 +0530 Message-Id: <20200714012725.18383-4-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200714012725.18383-1-karthik.b.s@intel.com> References: <20200714012725.18383-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Support added only for async flips on primary plane. If flip is requested on any other plane, reject it. Make sure there is no change in fbc, offset and framebuffer modifiers when async flip is requested. If any of these are modified, reject async flip. v2: -Replace DRM_ERROR (Paulo) -Add check for changes in OFFSET, FBC, RC(Paulo) v3: -Removed TODO as benchmarking tests have been run now. v4: -Added more state checks for async flip (Ville) -Moved intel_atomic_check_async to the end of intel_atomic_check as the plane checks needs to pass before this. (Ville) -Removed crtc_state->enable_fbc check. (Ville) -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async flip case as scanline counter is not reliable here. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 103 +++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index aa0eebeca7ff..fe06db9cf38e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14825,6 +14825,101 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, return false; } +static int intel_atomic_check_async(struct intel_atomic_state *state) +{ + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_plane_state *new_plane_state, *old_plane_state; + struct intel_crtc *crtc; + struct intel_plane *intel_plane; + int i, n_planes = 0; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (needs_modeset(new_crtc_state)) { + DRM_DEBUG_KMS("Modeset Requried. Async flip not supported\n"); + return -EINVAL; + } + + if (!new_crtc_state->uapi.active) { + DRM_DEBUG_KMS("CRTC inactive\n"); + return -EINVAL; + } + if (old_crtc_state->active_planes != new_crtc_state->active_planes) { + DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n"); + return -EINVAL; + } + } + + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state, + new_plane_state, i) { + /*TODO: Async flip is only supported through the page flip IOCTL + * as of now. So support currently added for primary plane only. + * Support for other planes should be added when async flip is + * enabled in the atomic IOCTL path. + */ + if (intel_plane->id != PLANE_PRIMARY) + return -EINVAL; + + if ((old_plane_state->color_plane[0].x != + new_plane_state->color_plane[0].x) || + (old_plane_state->color_plane[0].y != + new_plane_state->color_plane[0].y)) { + DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.fb->modifier != + new_plane_state->uapi.fb->modifier) { + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.fb->format != + new_plane_state->uapi.fb->format) { + DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n"); + return -EINVAL; + } + + if (intel_wm_need_update(old_plane_state, new_plane_state)) { + DRM_DEBUG_KMS("WM update not allowed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.alpha != new_plane_state->uapi.alpha) { + DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.pixel_blend_mode != new_plane_state->uapi.pixel_blend_mode) { + DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.color_encoding != new_plane_state->uapi.color_encoding) { + DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n"); + return -EINVAL; + } + + if (old_plane_state->uapi.color_range != new_plane_state->uapi.color_range) { + DRM_DEBUG_KMS("Color range cannot be changed in async flip\n"); + return -EINVAL; + } + + n_planes++; + } + + if (n_planes != 1) + return -EINVAL; + + /*Scan line registers cannot be trusted for async flip */ + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) + crtc->mode_flags |= I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; + } + + return 0; +} + /** * intel_atomic_check - validate state object * @dev: drm device @@ -15004,6 +15099,14 @@ static int intel_atomic_check(struct drm_device *dev, "[modeset]" : "[fastset]"); } + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->uapi.async_flip) { + ret = intel_atomic_check_async(state); + + if (ret) + goto fail; + } + } return 0; fail: From patchwork Tue Jul 14 01:27:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11661315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4AF69913 for ; Tue, 14 Jul 2020 01:51:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 32B6D2186A for ; Tue, 14 Jul 2020 01:51:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32B6D2186A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9DE3E6E877; Tue, 14 Jul 2020 01:50:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A4B56E876; Tue, 14 Jul 2020 01:50:58 +0000 (UTC) IronPort-SDR: 02gHXYgNc0zlhclh0cnwb3tkxT4iWycWUlbxwzjzJNJtXDUq2dN9g5Bziw/Zkc2JhFWV0HMRuz lBN12BZTaGpw== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="136245085" X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="136245085" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 18:50:57 -0700 IronPort-SDR: 1iaNDK/A8E6w8S1IL3+eUblbhoVrA8WyaaNQYA0ZdcyEfWe5mL22lNdmBt+WOSjAP2NLxOkDVh 2IhePOwUFTXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="307680298" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by fmsmga004.fm.intel.com with ESMTP; 13 Jul 2020 18:50:55 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 4/5] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips Date: Tue, 14 Jul 2020 06:57:24 +0530 Message-Id: <20200714012725.18383-5-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200714012725.18383-1-karthik.b.s@intel.com> References: <20200714012725.18383-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the flip done event will be sent in the flip_done_handler, no need to add the event to the list and delay it for later. v2: -Moved the async check above vblank_get as it was causing issues for PSR. v3: -No need to wait for vblank to pass, as this wait was causing a 16ms delay once every few flips. v4: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 7cffdb48e6df..2f1bc8bde516 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) DEFINE_WAIT(wait); u32 psr_status; + if (new_crtc_state->uapi.async_flip) + goto irq_disable; + vblank_start = adjusted_mode->crtc_vblank_start; if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) vblank_start = DIV_ROUND_UP(vblank_start, 2); @@ -206,7 +209,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) * Would be slightly nice to just grab the vblank count and arm the * event outside of the critical section - the spinlock might spin for a * while ... */ - if (new_crtc_state->uapi.event) { + if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) { drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base) != 0); @@ -220,6 +223,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) local_irq_enable(); + if (new_crtc_state->uapi.async_flip) + return; + if (intel_vgpu_active(dev_priv)) return; From patchwork Tue Jul 14 01:27:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karthik B S X-Patchwork-Id: 11661317 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 335B7913 for ; Tue, 14 Jul 2020 01:51:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B05E2186A for ; Tue, 14 Jul 2020 01:51:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B05E2186A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 959BE6E878; Tue, 14 Jul 2020 01:51:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 32A7D6E878; Tue, 14 Jul 2020 01:51:01 +0000 (UTC) IronPort-SDR: ODJT/sgzUunBfYk4LU/JiqUf5krjZnRV0WnJ/PnkCkJ3bzKpeBTZnNgsYuZikt2VAjaO9UBFAn hj+6hatiNlNw== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="136245095" X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="136245095" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2020 18:51:00 -0700 IronPort-SDR: I7G9wDHubCxKUN0A3kJ6sM9XNQGdcn/Uj0BHXgjV8wkdDrmvArUgS1CO4dj9Qrq7m6B8HS+LmU GdDeGdPy3xVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,349,1589266800"; d="scan'208";a="307680310" Received: from unknown (HELO karthik-2012-Client-Platform.iind.intel.com) ([10.223.74.217]) by fmsmga004.fm.intel.com with ESMTP; 13 Jul 2020 18:50:58 -0700 From: Karthik B S To: intel-gfx@lists.freedesktop.org Subject: [PATCH v4 5/5] drm/i915: Enable async flips in i915 Date: Tue, 14 Jul 2020 06:57:25 +0530 Message-Id: <20200714012725.18383-6-karthik.b.s@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200714012725.18383-1-karthik.b.s@intel.com> References: <20200714012725.18383-1-karthik.b.s@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, Karthik B S , dri-devel@lists.freedesktop.org, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, nicholas.kazlauskas@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable asynchronous flips in i915 for gen9+ platforms. v2: -Async flip enablement should be a stand alone patch (Paulo) v3: -Move the patch to the end of the serires (Paulo) v4: -Rebased. Signed-off-by: Karthik B S Signed-off-by: Vandita Kulkarni --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index fe06db9cf38e..c9abba98ad22 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -17886,6 +17886,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915) mode_config->funcs = &intel_mode_funcs; + if (INTEL_GEN(i915) >= 9) + mode_config->async_page_flip = true; + /* * Maximum framebuffer dimensions, chosen to match * the maximum render engine surface size on gen4+.